Re: [PATCH] perf, x86: Support full width counting v3

Re: [PATCH] perf, x86: Support full width counting v3

[Ingo Molnar]

* Andi Kleen <andi@firstfloor.org> wrote:

> From: Andi Kleen <ak@linux.intel.com>
> 
> Recent Intel CPUs like Haswell and IvyBridge have a new alternative MSR
> range for perfctrs that allows writing the full counter width. Enable this
> range if the hardware reports it using a new capability bit.
> 
> This lowers the overhead of perf stat slightly because it has to do less
> interrupts to accumulate the counter value. On Haswell it also avoids some
> problems with TSX aborting when the end of the counter range is reached.

Looks good - the changelog needs more work: please first outline the 
current behavior (how we can only write 32 bit values into the counter, 
even though the counter range is larger on most CPUs).

Then also outline the Haswell problems more precisely. What happens, why, 
with what probability and why do we care?

Thanks,

	Ingo

Re: [PATCH] perf, x86: Support full width counting v3

[Ingo Molnar]

* Ingo Molnar <mingo@kernel.org> wrote:

> Looks good - the changelog needs more work: please first outline the 
> current behavior (how we can only write 32 bit values into the counter, 
> even though the counter range is larger on most CPUs).
> 
> Then also outline the Haswell problems more precisely. What happens, 
> why, with what probability and why do we care?

For the latter it's enough to put a reference like this into the 
changelog:

  See the patch "perf/x86/intel: Avoid checkpointed counters causing 
  excessive TSX aborts" for more details.

Thanks,

	Ingo