From: Youquan Song <youquan.song@linux.intel.com>
To: Ingo Molnar <mingo@kernel.org>
Cc: Youquan Song <youquan.song@intel.com>,
linux-kernel@vger.kernel.org, hpa@linux.intel.com,
yinghai@kernel.org, tglx@linutronix.de,
Youquan Song <youquan.song@linux.intel.com>
Subject: Re: [PATCH] x86, apic: Enable x2APIC physical when cpu < 256 native
Date: Wed, 24 Jul 2013 10:04:40 -0400 [thread overview]
Message-ID: <20130724140440.GA13987@linux-youquan.bj.intel.com> (raw)
In-Reply-To: <20130723091729.GA19786@gmail.com>
On Tue, Jul 23, 2013 at 11:17:29AM +0200, Ingo Molnar wrote:
>
> * Youquan Song <youquan.song@intel.com> wrote:
>
> > x2APIC extends APICID from 8 bits to 32 bits, but the device interrupt
> > routed from IOAPIC or delivered in MSI mode will keep 8 bits destination
> > APICID. In order to support x2APIC, the VT-d interrupt remapping is
> > introduced to translate the destination APICID to 32 bits in x2APIC mode
> > and keep the device compatible in this way.
> >
> > x2APIC support both logical and physical mode in destination mode. In
> > logical destination mode, the 32 bits Logical APICID has 2 sub-fields:
> > 16 bits cluster ID and 16 bits logical ID within the cluster and it is
> > required VT-d interrupt remapping in x2APIC cluster mode. In physical
> > destination mode, the 8 bits physical id is compatible with 32 bits
> > physical id when CPU number < 256. When interrupt remapping
> > initialization fail on platform with CPU number < 256, current kernel
> > only enables x2APIC physical mode in virutalization environment, while
> > we also can enable x2APIC physcial mode in native kernel this situation,
> > and the device interrupt will use 8 bits destination APICID in physical
> > mode and be compatible with x2APIC physical when < 256 CPUs.
> >
> > So we can benefit from x2APIC vs xAPIC MMIO:
> > - x2APIC MSR read/write is faster than xAPIC mmio
> > - x2APIC only ICR write to deliver interrupt without polling ICR deliver
> > status bit and xAPIC need poll to read ICR deliver status bit.
> > - x2APIC 64 bits ICR access instead of xAPIC two 32 bits access.
>
> That looks interesting. How many systems are affected by this change in
> practice? Have you tested it on affected hardware?
Thanks Ingo!
The machines will be affected: CPU support x2APIC and CPU number < 256,
chipset does not support VT-d2 or VT-d is disabled in BIOS.
I have tested on one of affected hardware, it works.
Thanks
-Youquan
next prev parent reply other threads:[~2013-07-24 2:19 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-07-12 1:22 [PATCH] x86, apic: Enable x2APIC physical when cpu < 256 native Youquan Song
2013-07-23 9:17 ` Ingo Molnar
2013-07-24 14:04 ` Youquan Song [this message]
2013-07-25 22:01 ` Ingo Molnar
2013-07-29 16:48 ` Youquan Song
2013-07-24 3:55 ` [tip:x86/apic] x86/apic: Enable x2APIC physical mode on native hardware too, when there are fewer than 256 CPUs tip-bot for Youquan Song
2013-07-24 4:24 ` [PATCH] x86, apic: Enable x2APIC physical when cpu < 256 native Yinghai Lu
2013-07-24 6:22 ` Gleb Natapov
2013-07-25 14:05 ` Yinghai Lu
2013-07-29 17:05 ` Youquan Song
2013-08-14 18:40 ` Youquan Song
2013-08-14 11:11 ` Ingo Molnar
2013-08-17 13:44 ` Youquan Song
2013-08-17 7:42 ` Ingo Molnar
2013-08-17 8:24 ` Borislav Petkov
2013-08-17 9:03 ` Joe Perches
2013-08-17 15:44 ` Borislav Petkov
2013-08-17 16:26 ` Joe Perches
2013-08-18 10:02 ` Borislav Petkov
2013-08-17 19:52 ` Youquan Song
2013-08-19 7:11 ` Ingo Molnar
2013-08-02 19:12 ` Konrad Rzeszutek Wilk
2013-07-24 14:45 ` Konrad Rzeszutek Wilk
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