* [PATCHv2 0/2] clk: sunxi: Add clock support for the A10s
@ 2013-08-05 20:39 Maxime Ripard
2013-08-05 20:39 ` [PATCHv2 1/2] clk: sunxi: Add A10s gates Maxime Ripard
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Maxime Ripard @ 2013-08-05 20:39 UTC (permalink / raw)
To: Mike Turquette
Cc: Emilio Lopez, kevin.z.m.zh, sunny, shuge, linux-arm-kernel,
linux-kernel, linux-sunxi, Maxime Ripard
Hi,
This small patchset adds support for the gates found in the Allwinner A10s SoC.
Since the gates are the only clock that differ from the other supported
Allwinner SoCs so far, the two patches are quite trivial.
Thanks,
Maxime
Changes from v1:
- Added missing documentation
Maxime Ripard (2):
clk: sunxi: Add A10s gates
ARM: sun5i: dt: Use the A10s gates in the DTSI
Documentation/devicetree/bindings/clock/sunxi.txt | 3 +
.../bindings/clock/sunxi/sun5i-a10s-gates.txt | 75 ++++++++++++++++++++++
arch/arm/boot/dts/sun5i-a10s.dtsi | 36 ++++-------
drivers/clk/sunxi/clk-sunxi.c | 15 +++++
4 files changed, 107 insertions(+), 22 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/sunxi/sun5i-a10s-gates.txt
--
1.8.3.4
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCHv2 1/2] clk: sunxi: Add A10s gates
2013-08-05 20:39 [PATCHv2 0/2] clk: sunxi: Add clock support for the A10s Maxime Ripard
@ 2013-08-05 20:39 ` Maxime Ripard
2013-08-05 20:39 ` [PATCHv2 2/2] ARM: sun5i: dt: Use the A10s gates in the DTSI Maxime Ripard
2013-08-12 8:38 ` [PATCHv2 0/2] clk: sunxi: Add clock support for the A10s Maxime Ripard
2 siblings, 0 replies; 4+ messages in thread
From: Maxime Ripard @ 2013-08-05 20:39 UTC (permalink / raw)
To: Mike Turquette
Cc: Emilio Lopez, kevin.z.m.zh, sunny, shuge, linux-arm-kernel,
linux-kernel, linux-sunxi, Maxime Ripard
The Allwinner A10s has a slightly different gates set than the A10 and
A13, so add these gates to the clk driver.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Emilio López <emilio@elopez.com.ar>
Reviewed-by: Emilio López <emilio@elopez.com.ar>
---
Documentation/devicetree/bindings/clock/sunxi.txt | 3 +
.../bindings/clock/sunxi/sun5i-a10s-gates.txt | 75 ++++++++++++++++++++++
drivers/clk/sunxi/clk-sunxi.c | 15 +++++
3 files changed, 93 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/sunxi/sun5i-a10s-gates.txt
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index d495521..b24de10 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -14,13 +14,16 @@ Required properties:
"allwinner,sun4i-ahb-clk" - for the AHB clock
"allwinner,sun4i-ahb-gates-clk" - for the AHB gates on A10
"allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
+ "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
"allwinner,sun4i-apb0-clk" - for the APB0 clock
"allwinner,sun4i-apb0-gates-clk" - for the APB0 gates on A10
"allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
+ "allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
"allwinner,sun4i-apb1-clk" - for the APB1 clock
"allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
"allwinner,sun4i-apb1-gates-clk" - for the APB1 gates on A10
"allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
+ "allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s
Required properties for all clocks:
- reg : shall be the control register address for the clock.
diff --git a/Documentation/devicetree/bindings/clock/sunxi/sun5i-a10s-gates.txt b/Documentation/devicetree/bindings/clock/sunxi/sun5i-a10s-gates.txt
new file mode 100644
index 0000000..d24279f
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/sunxi/sun5i-a10s-gates.txt
@@ -0,0 +1,75 @@
+Gate clock outputs
+------------------
+
+ * AXI gates ("allwinner,sun4i-axi-gates-clk")
+
+ DRAM 0
+
+ * AHB gates ("allwinner,sun5i-a10s-ahb-gates-clk")
+
+ USB0 0
+ EHCI0 1
+ OHCI0 2
+
+ SS 5
+ DMA 6
+ BIST 7
+ MMC0 8
+ MMC1 9
+ MMC2 10
+
+ NAND 13
+ SDRAM 14
+
+ EMAC 17
+ TS 18
+
+ SPI0 20
+ SPI1 21
+ SPI2 22
+
+ GPS 26
+
+ HSTIMER 28
+
+ VE 32
+
+ TVE 34
+
+ LCD 36
+
+ CSI 40
+
+ HDMI 43
+ DE_BE 44
+
+ DE_FE 46
+
+ IEP 51
+ MALI400 52
+
+ * APB0 gates ("allwinner,sun5i-a10s-apb0-gates-clk")
+
+ CODEC 0
+
+ IIS 3
+
+ PIO 5
+ IR 6
+
+ KEYPAD 10
+
+ * APB1 gates ("allwinner,sun5i-a10s-apb1-gates-clk")
+
+ I2C0 0
+ I2C1 1
+ I2C2 2
+
+ UART0 16
+ UART1 17
+ UART2 18
+ UART3 19
+
+Notation:
+ [*]: The datasheet didn't mention these, but they are present on AW code
+ [**]: The datasheet had this marked as "NC" but they are used on AW code
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 412912b..db1c45b 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -341,6 +341,10 @@ static const __initconst struct gates_data sun4i_ahb_gates_data = {
.mask = {0x7F77FFF, 0x14FB3F},
};
+static const __initconst struct gates_data sun5i_a10s_ahb_gates_data = {
+ .mask = {0x147667e7, 0x185915},
+};
+
static const __initconst struct gates_data sun5i_a13_ahb_gates_data = {
.mask = {0x107067e7, 0x185111},
};
@@ -349,6 +353,10 @@ static const __initconst struct gates_data sun4i_apb0_gates_data = {
.mask = {0x4EF},
};
+static const __initconst struct gates_data sun5i_a10s_apb0_gates_data = {
+ .mask = {0x469},
+};
+
static const __initconst struct gates_data sun5i_a13_apb0_gates_data = {
.mask = {0x61},
};
@@ -357,6 +365,10 @@ static const __initconst struct gates_data sun4i_apb1_gates_data = {
.mask = {0xFF00F7},
};
+static const __initconst struct gates_data sun5i_a10s_apb1_gates_data = {
+ .mask = {0xf0007},
+};
+
static const __initconst struct gates_data sun5i_a13_apb1_gates_data = {
.mask = {0xa0007},
};
@@ -442,10 +454,13 @@ static const __initconst struct of_device_id clk_mux_match[] = {
static const __initconst struct of_device_id clk_gates_match[] = {
{.compatible = "allwinner,sun4i-axi-gates-clk", .data = &sun4i_axi_gates_data,},
{.compatible = "allwinner,sun4i-ahb-gates-clk", .data = &sun4i_ahb_gates_data,},
+ {.compatible = "allwinner,sun5i-a10s-ahb-gates-clk", .data = &sun5i_a10s_ahb_gates_data,},
{.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,},
{.compatible = "allwinner,sun4i-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
+ {.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,},
{.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
{.compatible = "allwinner,sun4i-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
+ {.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,},
{.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
{}
};
--
1.8.3.4
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCHv2 2/2] ARM: sun5i: dt: Use the A10s gates in the DTSI
2013-08-05 20:39 [PATCHv2 0/2] clk: sunxi: Add clock support for the A10s Maxime Ripard
2013-08-05 20:39 ` [PATCHv2 1/2] clk: sunxi: Add A10s gates Maxime Ripard
@ 2013-08-05 20:39 ` Maxime Ripard
2013-08-12 8:38 ` [PATCHv2 0/2] clk: sunxi: Add clock support for the A10s Maxime Ripard
2 siblings, 0 replies; 4+ messages in thread
From: Maxime Ripard @ 2013-08-05 20:39 UTC (permalink / raw)
To: Mike Turquette
Cc: Emilio Lopez, kevin.z.m.zh, sunny, shuge, linux-arm-kernel,
linux-kernel, linux-sunxi, Maxime Ripard
The A10s has only a subset of the A10 gates. Now that the clock driver
has support for this gates set, switch to it in the DTSI.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Emilio López <emilio@elopez.com.ar>
---
arch/arm/boot/dts/sun5i-a10s.dtsi | 36 ++++++++++++++----------------------
1 file changed, 14 insertions(+), 22 deletions(-)
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 0f0881a..b8fc1c2 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -95,20 +95,16 @@
ahb_gates: ahb_gates@01c20060 {
#clock-cells = <1>;
- compatible = "allwinner,sun4i-ahb-gates-clk";
+ compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
reg = <0x01c20060 0x8>;
clocks = <&ahb>;
- clock-output-names = "ahb_usb0", "ahb_ehci0",
- "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
- "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
- "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
- "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
- "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
- "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
- "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
- "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
- "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
- "ahb_de_fe1", "ahb_mp", "ahb_mali400";
+ clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
+ "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
+ "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
+ "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
+ "ahb_spi2", "ahb_gps", "ahb_stimer", "ahb_ve",
+ "ahb_tve", "ahb_lcd", "ahb_csi", "ahb_hdmi",
+ "ahb_de_be", "ahb_de_fe", "ahb_iep", "ahb_mali400";
};
apb0: apb0@01c20054 {
@@ -120,12 +116,11 @@
apb0_gates: apb0_gates@01c20068 {
#clock-cells = <1>;
- compatible = "allwinner,sun4i-apb0-gates-clk";
+ compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
reg = <0x01c20068 0x4>;
clocks = <&apb0>;
- clock-output-names = "apb0_codec", "apb0_spdif",
- "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
- "apb0_ir1", "apb0_keypad";
+ clock-output-names = "apb0_codec", "apb0_iis", "apb0_pio",
+ "apb0_ir", "apb0_keypad";
};
/* dummy is pll62 */
@@ -145,15 +140,12 @@
apb1_gates: apb1_gates@01c2006c {
#clock-cells = <1>;
- compatible = "allwinner,sun4i-apb1-gates-clk";
+ compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
reg = <0x01c2006c 0x4>;
clocks = <&apb1>;
clock-output-names = "apb1_i2c0", "apb1_i2c1",
- "apb1_i2c2", "apb1_can", "apb1_scr",
- "apb1_ps20", "apb1_ps21", "apb1_uart0",
- "apb1_uart1", "apb1_uart2", "apb1_uart3",
- "apb1_uart4", "apb1_uart5", "apb1_uart6",
- "apb1_uart7";
+ "apb1_i2c2", "apb1_uart0", "apb1_uart1",
+ "apb1_uart2", "apb1_uart3";
};
};
--
1.8.3.4
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCHv2 0/2] clk: sunxi: Add clock support for the A10s
2013-08-05 20:39 [PATCHv2 0/2] clk: sunxi: Add clock support for the A10s Maxime Ripard
2013-08-05 20:39 ` [PATCHv2 1/2] clk: sunxi: Add A10s gates Maxime Ripard
2013-08-05 20:39 ` [PATCHv2 2/2] ARM: sun5i: dt: Use the A10s gates in the DTSI Maxime Ripard
@ 2013-08-12 8:38 ` Maxime Ripard
2 siblings, 0 replies; 4+ messages in thread
From: Maxime Ripard @ 2013-08-12 8:38 UTC (permalink / raw)
To: Mike Turquette
Cc: Emilio Lopez, kevin.z.m.zh, sunny, shuge, linux-arm-kernel,
linux-kernel, linux-sunxi
[-- Attachment #1: Type: text/plain, Size: 516 bytes --]
Hi Mike,
On Mon, Aug 05, 2013 at 10:39:24PM +0200, Maxime Ripard wrote:
> This small patchset adds support for the gates found in the Allwinner A10s SoC.
> Since the gates are the only clock that differ from the other supported
> Allwinner SoCs so far, the two patches are quite trivial.
It would be great if you could merge this in 3.12.
Do you have comments on this one?
Thanks,
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 836 bytes --]
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