[PATCH v4 0/4] ARM: OMAP: SATA support for OMAP5 & DRA7

[PATCH v4 0/4] ARM: OMAP: SATA support for OMAP5 & DRA7

[Roger Quadros]

Hi Tony,

These are the pending HWMOD and DTS patches to get SATA working
on OMAP5-uevm and DRA7-evm. Please queue them for -next. Thanks.

cheers,
-roger

---
Balaji T K (2):
  ARM: dts: omap5: add sata node
  ARM: dts: dra7: add OCP2SCP3 and SATA nodes

Keshava Munegowda (1):
  ARM: OMAP5: hwmod: Add ocp2scp3 and sata hwmods

Nikhil Devshatwar (1):
  ARM: DRA7: hwmod: Add ocp2scp3 and sata hwmods

 arch/arm/boot/dts/dra7.dtsi                | 39 ++++++++++++++++
 arch/arm/boot/dts/omap5.dtsi               | 40 ++++++++++++++++
 arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 73 ++++++++++++++++++++++++++++++
 arch/arm/mach-omap2/omap_hwmod_7xx_data.c  | 31 +++++++++++--
 4 files changed, 178 insertions(+), 5 deletions(-)

-- 
1.8.3.2

[PATCH v4 1/4] ARM: OMAP5: hwmod: Add ocp2scp3 and sata hwmods

[Roger Quadros]

From: Keshava Munegowda <keshava_mgowda@ti.com>

Create hwmods for ocp2scp3 and sata modules.

[Roger Q] Clean up.

CC: Benoit Cousson <bcousson@baylibre.com>
Acked-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Balaji T K <balajitk@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 73 ++++++++++++++++++++++++++++++
 1 file changed, 73 insertions(+)

diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
index 8923172..e169f90 100644
--- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
@@ -1791,6 +1791,77 @@ static struct omap_hwmod omap54xx_wd_timer2_hwmod = {
 	},
 };
 
+/*
+ * 'ocp2scp' class
+ * bridge to transform ocp interface protocol to scp (serial control port)
+ * protocol
+ */
+/* ocp2scp3 */
+static struct omap_hwmod omap54xx_ocp2scp3_hwmod;
+/* l4_cfg -> ocp2scp3 */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp3 = {
+	.master		= &omap54xx_l4_cfg_hwmod,
+	.slave		= &omap54xx_ocp2scp3_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod omap54xx_ocp2scp3_hwmod = {
+	.name		= "ocp2scp3",
+	.class		= &omap54xx_ocp2scp_hwmod_class,
+	.clkdm_name	= "l3init_clkdm",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_HWCTRL,
+		},
+	},
+};
+
+/*
+ * 'sata' class
+ * sata:  serial ata interface  gen2 compliant   ( 1 rx/ 1 tx)
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_sata_sysc = {
+	.sysc_offs	= 0x0000,
+	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+	.sysc_fields	= &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap54xx_sata_hwmod_class = {
+	.name	= "sata",
+	.sysc	= &omap54xx_sata_sysc,
+};
+
+/* sata */
+static struct omap_hwmod omap54xx_sata_hwmod = {
+	.name		= "sata",
+	.class		= &omap54xx_sata_hwmod_class,
+	.clkdm_name	= "l3init_clkdm",
+	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
+	.main_clk	= "func_48m_fclk",
+	.mpu_rt_idx	= 1,
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
+			.context_offs = OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+/* l4_cfg -> sata */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__sata = {
+	.master		= &omap54xx_l4_cfg_hwmod,
+	.slave		= &omap54xx_sata_hwmod,
+	.clk		= "l3_iclk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
 
 /*
  * Interfaces
@@ -2482,6 +2553,8 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
 	&omap54xx_l4_cfg__usb_tll_hs,
 	&omap54xx_l4_cfg__usb_otg_ss,
 	&omap54xx_l4_wkup__wd_timer2,
+	&omap54xx_l4_cfg__ocp2scp3,
+	&omap54xx_l4_cfg__sata,
 	NULL,
 };
 
-- 
1.8.3.2

[PATCH v4 2/4] ARM: dts: omap5: add sata node

[Roger Quadros]

From: Balaji T K <balajitk@ti.com>

Add support for sata.

[Roger Q] Clean up.

CC: Benoit Cousson <bcousson@baylibre.com>
CC: Tony Lindgren <tony@atomide.com>
Signed-off-by: Balaji T K <balajitk@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 arch/arm/boot/dts/omap5.dtsi | 40 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 6f3de22..8ab6721 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -863,6 +863,46 @@
 
 			#thermal-sensor-cells = <1>;
 		};
+
+		omap_control_sata: control-phy@4a002374 {
+			compatible = "ti,control-phy-pipe3";
+			reg = <0x4a002374 0x4>;
+			reg-names = "power";
+			clocks = <&sys_clkin>;
+			clock-names = "sysclk";
+		};
+
+		/* OCP2SCP3 */
+		ocp2scp@4a090000 {
+			compatible = "ti,omap-ocp2scp";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x4a090000 0x20>;
+			ranges;
+			ti,hwmods = "ocp2scp3";
+			sata_phy: phy@4a096000 {
+				compatible = "ti,phy-pipe3-sata";
+				reg = <0x4A096000 0x80>, /* phy_rx */
+				      <0x4A096400 0x64>, /* phy_tx */
+				      <0x4A096800 0x40>; /* pll_ctrl */
+				reg-names = "phy_rx", "phy_tx", "pll_ctrl";
+				ctrl-module = <&omap_control_sata>;
+				clocks = <&sys_clkin>;
+				clock-names = "sysclk";
+				#phy-cells = <0>;
+			};
+		};
+
+		sata: sata@4a141100 {
+			compatible = "snps,dwc-ahci";
+			reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
+			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+			phys = <&sata_phy>;
+			phy-names = "sata-phy";
+			clocks = <&sata_ref_clk>;
+			ti,hwmods = "sata";
+		};
+
 	};
 };
 
-- 
1.8.3.2

[PATCH v4 3/4] ARM: DRA7: hwmod: Add ocp2scp3 and sata hwmods

[Roger Quadros]

From: Nikhil Devshatwar <nikhil.nd@ti.com>

Add hwmods for ocp2scp3 and sata modules.

[Roger Q] Clean up.

CC: Benoit Cousson <bcousson@baylibre.com>
CC: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Balaji T K <balajitk@ti.com>
Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 31 ++++++++++++++++++++++++++-----
 1 file changed, 26 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 810c205..b02a4ab 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1215,6 +1215,30 @@ static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
 	},
 };
 
+/* ocp2scp3 */
+static struct omap_hwmod dra7xx_ocp2scp3_hwmod;
+
+/* l4_cfg -> ocp2scp3 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
+	.master		= &dra7xx_l4_cfg_hwmod,
+	.slave		= &dra7xx_ocp2scp3_hwmod,
+	.clk		= "l4_root_clk_div",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
+	.name		= "ocp2scp3",
+	.class		= &dra7xx_ocp2scp_hwmod_class,
+	.clkdm_name	= "l3init_clkdm",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
+			.context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
+			.modulemode   = MODULEMODE_HWCTRL,
+		},
+	},
+};
+
 /*
  * 'qspi' class
  *
@@ -1268,9 +1292,6 @@ static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
 };
 
 /* sata */
-static struct omap_hwmod_opt_clk sata_opt_clks[] = {
-	{ .role = "ref_clk", .clk = "sata_ref_clk" },
-};
 
 static struct omap_hwmod dra7xx_sata_hwmod = {
 	.name		= "sata",
@@ -1278,6 +1299,7 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
 	.clkdm_name	= "l3init_clkdm",
 	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 	.main_clk	= "func_48m_fclk",
+	.mpu_rt_idx	= 1,
 	.prcm = {
 		.omap4 = {
 			.clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
@@ -1285,8 +1307,6 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
 			.modulemode   = MODULEMODE_SWCTRL,
 		},
 	},
-	.opt_clks	= sata_opt_clks,
-	.opt_clks_cnt	= ARRAY_SIZE(sata_opt_clks),
 };
 
 /*
@@ -2682,6 +2702,7 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
 	&dra7xx_l4_per1__mmc4,
 	&dra7xx_l4_cfg__mpu,
 	&dra7xx_l4_cfg__ocp2scp1,
+	&dra7xx_l4_cfg__ocp2scp3,
 	&dra7xx_l3_main_1__qspi,
 	&dra7xx_l4_cfg__sata,
 	&dra7xx_l4_cfg__smartreflex_core,
-- 
1.8.3.2

[PATCH v4 4/4] ARM: dts: dra7: add OCP2SCP3 and SATA nodes

[Roger Quadros]

From: Balaji T K <balajitk@ti.com>

Add nodes for OCP2SCP3 bus, SATA controller and SATA PHY.

[Roger Q] Clean up.

CC: Benoit Cousson <bcousson@baylibre.com>
Signed-off-by: Balaji T K <balajitk@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 arch/arm/boot/dts/dra7.dtsi | 39 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 1c0f8e1..084f42e 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -789,6 +789,45 @@
 			dma-names = "tx0", "rx0";
 			status = "disabled";
 		};
+
+		omap_control_sata: control-phy@4a002374 {
+			compatible = "ti,control-phy-pipe3";
+			reg = <0x4a002374 0x4>;
+			reg-names = "power";
+			clocks = <&sys_clkin1>;
+			clock-names = "sysclk";
+		};
+
+		/* OCP2SCP3 */
+		ocp2scp@4a090000 {
+			compatible = "ti,omap-ocp2scp";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			reg = <0x4a090000 0x20>;
+			ti,hwmods = "ocp2scp3";
+			sata_phy: phy@4A096000 {
+				compatible = "ti,phy-pipe3-sata";
+				reg = <0x4A096000 0x80>, /* phy_rx */
+				      <0x4A096400 0x64>, /* phy_tx */
+				      <0x4A096800 0x40>; /* pll_ctrl */
+				reg-names = "phy_rx", "phy_tx", "pll_ctrl";
+				ctrl-module = <&omap_control_sata>;
+				clocks = <&sys_clkin1>;
+				clock-names = "sysclk";
+				#phy-cells = <0>;
+			};
+		};
+
+		sata: sata@4a141100 {
+			compatible = "snps,dwc-ahci";
+			reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
+			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+			phys = <&sata_phy>;
+			phy-names = "sata-phy";
+			clocks = <&sata_ref_clk>;
+			ti,hwmods = "sata";
+		};
 	};
 };
 
-- 
1.8.3.2

Re: [PATCH v4 0/4] ARM: OMAP: SATA support for OMAP5 & DRA7

[Roger Quadros]

Hi Tony,

On 04/23/2014 08:30 PM, Roger Quadros wrote:
> Hi Tony,
> 
> These are the pending HWMOD and DTS patches to get SATA working
> on OMAP5-uevm and DRA7-evm. Please queue them for -next. Thanks.

gentle reminder. Thanks.

cheers,
-roger

> 
> ---
> Balaji T K (2):
>   ARM: dts: omap5: add sata node
>   ARM: dts: dra7: add OCP2SCP3 and SATA nodes
> 
> Keshava Munegowda (1):
>   ARM: OMAP5: hwmod: Add ocp2scp3 and sata hwmods
> 
> Nikhil Devshatwar (1):
>   ARM: DRA7: hwmod: Add ocp2scp3 and sata hwmods
> 
>  arch/arm/boot/dts/dra7.dtsi                | 39 ++++++++++++++++
>  arch/arm/boot/dts/omap5.dtsi               | 40 ++++++++++++++++
>  arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 73 ++++++++++++++++++++++++++++++
>  arch/arm/mach-omap2/omap_hwmod_7xx_data.c  | 31 +++++++++++--
>  4 files changed, 178 insertions(+), 5 deletions(-)
> 

Re: [PATCH v4 4/4] ARM: dts: dra7: add OCP2SCP3 and SATA nodes

[Roger Quadros]

Tony,

On 04/23/2014 08:36 PM, Roger Quadros wrote:
> From: Balaji T K <balajitk@ti.com>
> 
> Add nodes for OCP2SCP3 bus, SATA controller and SATA PHY.
> 
> [Roger Q] Clean up.
> 
> CC: Benoit Cousson <bcousson@baylibre.com>
> Signed-off-by: Balaji T K <balajitk@ti.com>
> Signed-off-by: Roger Quadros <rogerq@ti.com>
> ---
>  arch/arm/boot/dts/dra7.dtsi | 39 +++++++++++++++++++++++++++++++++++++++
>  1 file changed, 39 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
> index 1c0f8e1..084f42e 100644
> --- a/arch/arm/boot/dts/dra7.dtsi
> +++ b/arch/arm/boot/dts/dra7.dtsi
> @@ -789,6 +789,45 @@
>  			dma-names = "tx0", "rx0";
>  			status = "disabled";
>  		};
> +
> +		omap_control_sata: control-phy@4a002374 {
> +			compatible = "ti,control-phy-pipe3";
> +			reg = <0x4a002374 0x4>;
> +			reg-names = "power";
> +			clocks = <&sys_clkin1>;
> +			clock-names = "sysclk";
> +		};
> +
> +		/* OCP2SCP3 */
> +		ocp2scp@4a090000 {
> +			compatible = "ti,omap-ocp2scp";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +			reg = <0x4a090000 0x20>;
> +			ti,hwmods = "ocp2scp3";
> +			sata_phy: phy@4A096000 {
> +				compatible = "ti,phy-pipe3-sata";
> +				reg = <0x4A096000 0x80>, /* phy_rx */
> +				      <0x4A096400 0x64>, /* phy_tx */
> +				      <0x4A096800 0x40>; /* pll_ctrl */
> +				reg-names = "phy_rx", "phy_tx", "pll_ctrl";
> +				ctrl-module = <&omap_control_sata>;
> +				clocks = <&sys_clkin1>;
> +				clock-names = "sysclk";
> +				#phy-cells = <0>;
> +			};
> +		};
> +
> +		sata: sata@4a141100 {
> +			compatible = "snps,dwc-ahci";
> +			reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
> +			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;

This will need to be changed like so if the IRQ crossbar changes [1] go in 

+			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;

cheers,
-roger

[1] - http://article.gmane.org/gmane.linux.documentation/23293

> +			phys = <&sata_phy>;
> +			phy-names = "sata-phy";
> +			clocks = <&sata_ref_clk>;
> +			ti,hwmods = "sata";
> +		};
>  	};
>  };
>  
> 

[PATCH v5 4/4] ARM: dts: dra7: add OCP2SCP3 and SATA nodes

[Roger Quadros]

From: Balaji T K <balajitk@ti.com>

Add nodes for OCP2SCP3 bus, SATA controller and SATA PHY.

[Roger Q] Clean up. Updated IRQ for interrupt crossbar.

CC: Benoit Cousson <bcousson@baylibre.com>
Signed-off-by: Balaji T K <balajitk@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 arch/arm/boot/dts/dra7.dtsi | 39 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index cec826f..1f42e72 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -798,6 +798,45 @@
 			dma-names = "tx0", "rx0";
 			status = "disabled";
 		};
+
+		omap_control_sata: control-phy@4a002374 {
+			compatible = "ti,control-phy-pipe3";
+			reg = <0x4a002374 0x4>;
+			reg-names = "power";
+			clocks = <&sys_clkin1>;
+			clock-names = "sysclk";
+		};
+
+		/* OCP2SCP3 */
+		ocp2scp@4a090000 {
+			compatible = "ti,omap-ocp2scp";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			reg = <0x4a090000 0x20>;
+			ti,hwmods = "ocp2scp3";
+			sata_phy: phy@4A096000 {
+				compatible = "ti,phy-pipe3-sata";
+				reg = <0x4A096000 0x80>, /* phy_rx */
+				      <0x4A096400 0x64>, /* phy_tx */
+				      <0x4A096800 0x40>; /* pll_ctrl */
+				reg-names = "phy_rx", "phy_tx", "pll_ctrl";
+				ctrl-module = <&omap_control_sata>;
+				clocks = <&sys_clkin1>;
+				clock-names = "sysclk";
+				#phy-cells = <0>;
+			};
+		};
+
+		sata: sata@4a141100 {
+			compatible = "snps,dwc-ahci";
+			reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
+			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+			phys = <&sata_phy>;
+			phy-names = "sata-phy";
+			clocks = <&sata_ref_clk>;
+			ti,hwmods = "sata";
+		};
 	};
 
 	crossbar_mpu: crossbar@4a020000 {
-- 
1.8.3.2

Re: [PATCH v4 2/4] ARM: dts: omap5: add sata node

[Tony Lindgren]

* Roger Quadros <rogerq@ti.com> [140423 10:36]:
> From: Balaji T K <balajitk@ti.com>
> 
> Add support for sata.

Adding this into omap-for-v3.16/dt thanks.

Tony 

Re: [PATCH v4 4/4] ARM: dts: dra7: add OCP2SCP3 and SATA nodes

[Tony Lindgren]

* Roger Quadros <rogerq@ti.com> [140507 01:15]:
> Tony,
> 
> On 04/23/2014 08:36 PM, Roger Quadros wrote:
> > From: Balaji T K <balajitk@ti.com>
> > 
> > Add nodes for OCP2SCP3 bus, SATA controller and SATA PHY.

> > +		sata: sata@4a141100 {
> > +			compatible = "snps,dwc-ahci";
> > +			reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
> > +			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
> 
> This will need to be changed like so if the IRQ crossbar changes [1] go in 
> 
> +			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
> 

Adding this as is into omap-for-v3.16/dt thanks. Sounds like the crossbar
needs more work.

Tony

Re: [PATCH v5 4/4] ARM: dts: dra7: add OCP2SCP3 and SATA nodes

[Tony Lindgren]

* Roger Quadros <rogerq@ti.com> [140507 04:59]:
> From: Balaji T K <balajitk@ti.com>
> 
> Add nodes for OCP2SCP3 bus, SATA controller and SATA PHY.
> 
> [Roger Q] Clean up. Updated IRQ for interrupt crossbar.

Adding this too into omap-for-v3.16/dt.

Regards,

Tony

Re: [PATCH v4 0/4] ARM: OMAP: SATA support for OMAP5 & DRA7

[Tony Lindgren]

* Roger Quadros <rogerq@ti.com> [140506 01:44]:
> Hi Tony,
> 
> On 04/23/2014 08:30 PM, Roger Quadros wrote:
> > Hi Tony,
> > 
> > These are the pending HWMOD and DTS patches to get SATA working
> > on OMAP5-uevm and DRA7-evm. Please queue them for -next. Thanks.
> 
> gentle reminder. Thanks.

I picked up the .dts changes. Paul is queueing the various hwmod
changes separately.

Regards,

Tony

Re: [PATCH v4 1/4] ARM: OMAP5: hwmod: Add ocp2scp3 and sata hwmods

[Roger Quadros]

Tony,

Looks like we've missed this for 3.16.

cheers,
-roger

On 04/23/2014 08:34 PM, Roger Quadros wrote:
> From: Keshava Munegowda <keshava_mgowda@ti.com>
> 
> Create hwmods for ocp2scp3 and sata modules.
> 
> [Roger Q] Clean up.
> 
> CC: Benoit Cousson <bcousson@baylibre.com>
> Acked-by: Paul Walmsley <paul@pwsan.com>
> Signed-off-by: Balaji T K <balajitk@ti.com>
> Signed-off-by: Roger Quadros <rogerq@ti.com>
> ---
>  arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 73 ++++++++++++++++++++++++++++++
>  1 file changed, 73 insertions(+)
> 
> diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
> index 8923172..e169f90 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
> @@ -1791,6 +1791,77 @@ static struct omap_hwmod omap54xx_wd_timer2_hwmod = {
>  	},
>  };
>  
> +/*
> + * 'ocp2scp' class
> + * bridge to transform ocp interface protocol to scp (serial control port)
> + * protocol
> + */
> +/* ocp2scp3 */
> +static struct omap_hwmod omap54xx_ocp2scp3_hwmod;
> +/* l4_cfg -> ocp2scp3 */
> +static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp3 = {
> +	.master		= &omap54xx_l4_cfg_hwmod,
> +	.slave		= &omap54xx_ocp2scp3_hwmod,
> +	.clk		= "l4_root_clk_div",
> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +static struct omap_hwmod omap54xx_ocp2scp3_hwmod = {
> +	.name		= "ocp2scp3",
> +	.class		= &omap54xx_ocp2scp_hwmod_class,
> +	.clkdm_name	= "l3init_clkdm",
> +	.prcm = {
> +		.omap4 = {
> +			.clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
> +			.context_offs = OMAP54XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
> +			.modulemode   = MODULEMODE_HWCTRL,
> +		},
> +	},
> +};
> +
> +/*
> + * 'sata' class
> + * sata:  serial ata interface  gen2 compliant   ( 1 rx/ 1 tx)
> + */
> +
> +static struct omap_hwmod_class_sysconfig omap54xx_sata_sysc = {
> +	.sysc_offs	= 0x0000,
> +	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
> +	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
> +			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
> +			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
> +	.sysc_fields	= &omap_hwmod_sysc_type2,
> +};
> +
> +static struct omap_hwmod_class omap54xx_sata_hwmod_class = {
> +	.name	= "sata",
> +	.sysc	= &omap54xx_sata_sysc,
> +};
> +
> +/* sata */
> +static struct omap_hwmod omap54xx_sata_hwmod = {
> +	.name		= "sata",
> +	.class		= &omap54xx_sata_hwmod_class,
> +	.clkdm_name	= "l3init_clkdm",
> +	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
> +	.main_clk	= "func_48m_fclk",
> +	.mpu_rt_idx	= 1,
> +	.prcm = {
> +		.omap4 = {
> +			.clkctrl_offs = OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
> +			.context_offs = OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
> +			.modulemode   = MODULEMODE_SWCTRL,
> +		},
> +	},
> +};
> +
> +/* l4_cfg -> sata */
> +static struct omap_hwmod_ocp_if omap54xx_l4_cfg__sata = {
> +	.master		= &omap54xx_l4_cfg_hwmod,
> +	.slave		= &omap54xx_sata_hwmod,
> +	.clk		= "l3_iclk_div",
> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
> +};
>  
>  /*
>   * Interfaces
> @@ -2482,6 +2553,8 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
>  	&omap54xx_l4_cfg__usb_tll_hs,
>  	&omap54xx_l4_cfg__usb_otg_ss,
>  	&omap54xx_l4_wkup__wd_timer2,
> +	&omap54xx_l4_cfg__ocp2scp3,
> +	&omap54xx_l4_cfg__sata,
>  	NULL,
>  };
>  
> 

Re: [PATCH v4 3/4] ARM: DRA7: hwmod: Add ocp2scp3 and sata hwmods

[Roger Quadros]

Tony,

We need this one as well for 3.16.

cheers,
-roger

On 04/23/2014 08:35 PM, Roger Quadros wrote:
> From: Nikhil Devshatwar <nikhil.nd@ti.com>
> 
> Add hwmods for ocp2scp3 and sata modules.
> 
> [Roger Q] Clean up.
> 
> CC: Benoit Cousson <bcousson@baylibre.com>
> CC: Paul Walmsley <paul@pwsan.com>
> Signed-off-by: Balaji T K <balajitk@ti.com>
> Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
> Signed-off-by: Roger Quadros <rogerq@ti.com>
> ---
>  arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 31 ++++++++++++++++++++++++++-----
>  1 file changed, 26 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> index 810c205..b02a4ab 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> @@ -1215,6 +1215,30 @@ static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
>  	},
>  };
>  
> +/* ocp2scp3 */
> +static struct omap_hwmod dra7xx_ocp2scp3_hwmod;
> +
> +/* l4_cfg -> ocp2scp3 */
> +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
> +	.master		= &dra7xx_l4_cfg_hwmod,
> +	.slave		= &dra7xx_ocp2scp3_hwmod,
> +	.clk		= "l4_root_clk_div",
> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
> +	.name		= "ocp2scp3",
> +	.class		= &dra7xx_ocp2scp_hwmod_class,
> +	.clkdm_name	= "l3init_clkdm",
> +	.prcm = {
> +		.omap4 = {
> +			.clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
> +			.context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
> +			.modulemode   = MODULEMODE_HWCTRL,
> +		},
> +	},
> +};
> +
>  /*
>   * 'qspi' class
>   *
> @@ -1268,9 +1292,6 @@ static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
>  };
>  
>  /* sata */
> -static struct omap_hwmod_opt_clk sata_opt_clks[] = {
> -	{ .role = "ref_clk", .clk = "sata_ref_clk" },
> -};
>  
>  static struct omap_hwmod dra7xx_sata_hwmod = {
>  	.name		= "sata",
> @@ -1278,6 +1299,7 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
>  	.clkdm_name	= "l3init_clkdm",
>  	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
>  	.main_clk	= "func_48m_fclk",
> +	.mpu_rt_idx	= 1,
>  	.prcm = {
>  		.omap4 = {
>  			.clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
> @@ -1285,8 +1307,6 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
>  			.modulemode   = MODULEMODE_SWCTRL,
>  		},
>  	},
> -	.opt_clks	= sata_opt_clks,
> -	.opt_clks_cnt	= ARRAY_SIZE(sata_opt_clks),
>  };
>  
>  /*
> @@ -2682,6 +2702,7 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
>  	&dra7xx_l4_per1__mmc4,
>  	&dra7xx_l4_cfg__mpu,
>  	&dra7xx_l4_cfg__ocp2scp1,
> +	&dra7xx_l4_cfg__ocp2scp3,
>  	&dra7xx_l3_main_1__qspi,
>  	&dra7xx_l4_cfg__sata,
>  	&dra7xx_l4_cfg__smartreflex_core,
> 

Re: [PATCH v4 1/4] ARM: OMAP5: hwmod: Add ocp2scp3 and sata hwmods

[Sekhar Nori]

On Thursday 12 June 2014 06:16 PM, Roger Quadros wrote:
> Tony,
> 
> Looks like we've missed this for 3.16.

Without these SATA support will be broken for DRA7x and OMAP5 so can
they be queued for -rc2?

Thanks,
Sekhar

Re: [PATCH v4 3/4] ARM: DRA7: hwmod: Add ocp2scp3 and sata hwmods

[Paul Walmsley]

Hi Roger,

On Wed, 23 Apr 2014, Roger Quadros wrote:

> From: Nikhil Devshatwar <nikhil.nd@ti.com>
> 
> Add hwmods for ocp2scp3 and sata modules.
> 
> [Roger Q] Clean up.

Sorry for the delay on this.  Have been corresponding with TI to figure 
out what to do about these DRA7xx/AM43xx patches, since I don't have 
boards or public documentation for these devices, so it's impossible for 
me to meaningfully review the patches.  Looks like boards and/or public 
docs won't be coming any time soon.

So for my part, here's what I'll need to merge any hwmod patches that 
involve AM437x or DRA7xx:

1. A Reviewed-by: from one of the following folks (which should come from 
a different person than who is submitting the patches):

Roger Quadros
Nishanth Menon
Rajendra Nayak
Kevin Hilman
Tony Lindgren

2. A Tested-by: from one of the following folks (who can be the same as 
the person who is the same as the person who is submitting the patches):

Nishanth Menon
Rajendra Nayak
Kevin Hilman 
Tony Lindgren

Once these are in place, I'd be happy to queue it for 3.16.


- Paul

Re: [PATCH v4 3/4] ARM: DRA7: hwmod: Add ocp2scp3 and sata hwmods

[Paul Walmsley]

On Fri, 13 Jun 2014, Paul Walmsley wrote:

> Hi Roger,
> 
> On Wed, 23 Apr 2014, Roger Quadros wrote:
> 
> > From: Nikhil Devshatwar <nikhil.nd@ti.com>
> > 
> > Add hwmods for ocp2scp3 and sata modules.
> > 
> > [Roger Q] Clean up.
> 
> Sorry for the delay on this.  Have been corresponding with TI to figure 
> out what to do about these DRA7xx/AM43xx patches, since I don't have 
> boards or public documentation for these devices, so it's impossible for 
> me to meaningfully review the patches.  Looks like boards and/or public 
> docs won't be coming any time soon.
> 
> So for my part, here's what I'll need to merge any hwmod patches that 
> involve AM437x or DRA7xx:
> 
> 1. A Reviewed-by: from one of the following folks (which should come from 
> a different person than who is submitting the patches):
> 
> Roger Quadros
> Nishanth Menon
> Rajendra Nayak
> Kevin Hilman
> Tony Lindgren
> 
> 2. A Tested-by: from one of the following folks (who can be the same as 
> the person who is the same as the person who is submitting the patches):
> 
> Nishanth Menon
> Rajendra Nayak
> Kevin Hilman 
> Tony Lindgren
> 
> Once these are in place, I'd be happy to queue it for 3.16.

I've tried to clarify this a bit.  The update is below.


- Paul



For boards that I don't have access to, that I don't have 
documentation for, such as the AM43xx and DRA7xx), for me to merge or ack 
SoC infrastructure or PM-related patches, I want to have:

1. a Reviewed-by: from people who:

a. I think know something about SoC integration or PM in general, and 
about OMAP-style integration specifically; and

b. who have a track record of doing strong and detailed reviews of that 
code, or who have contributed significantly to that code in the past.

My initial list of those reviewers is listed above, and I am happy to 
consider extending it or modifying that list.


2. confidence that the patch or series has been tested against a mainline 
commit and isn't obviously breaking other things, like PM, and confidence 
that it's not adding new runtime warnings.

I've listed an initial set of people above who I feel have proven track 
records in testing who I'm happy to accept Tested-by:s without further 
explanation.  I'm sure I've missed some folks and if anyone who should be 
on that list is offended that I didn't mention them, please accept my 
apologies.  For other folks, like yourself, who aren't on that list (yet), 
please just specifically state:

a. what mainline commit they've tested the patch against,

b. what other prerequisite patches were needed for the patch to apply,

c. and a cut-and-paste of the serial console boot log from the boot 
portion of the test.

in such a way that myself or someone else can easily doublecheck it. 

And frankly, I'll probably be happy to merge it.

After someone has done these three things a few times, and I gain 
confidence that they're doing the right thing, I'm happy to add them to 
my list.

The testing doesn't have to be expressed via a Tested-by: tag in cases 
where you're testing as part of a Signed-off-by:.  Just be sure to state 
those three things above as part of the patch or series message.  The boot 
log can either be placed on a different page and linked to, or sent in 
another public E-mail.

If you can get two or three people to do the above, that's great - the 
more, the better.

...

These two steps do not apply to boards that I have in my testbed or which 
I have documentation for (although they would definitely be very welcome 
in those cases too).

Re: [PATCH v4 1/4] ARM: OMAP5: hwmod: Add ocp2scp3 and sata hwmods

[Paul Walmsley]

On Wed, 23 Apr 2014, Roger Quadros wrote:

> From: Keshava Munegowda <keshava_mgowda@ti.com>
> 
> Create hwmods for ocp2scp3 and sata modules.
> 
> [Roger Q] Clean up.
> 
> CC: Benoit Cousson <bcousson@baylibre.com>
> Acked-by: Paul Walmsley <paul@pwsan.com>
> Signed-off-by: Balaji T K <balajitk@ti.com>
> Signed-off-by: Roger Quadros <rogerq@ti.com>

Queued here; will try to get this into the early -rcs.

- Paul

Re: [PATCH v4 3/4] ARM: DRA7: hwmod: Add ocp2scp3 and sata hwmods

[Roger Quadros]

+ Rajendra, Nishant and Kevin.
as you were mentioned in the discussion.

cheers,
-roger

On 06/15/2014 06:33 AM, Paul Walmsley wrote:
> On Fri, 13 Jun 2014, Paul Walmsley wrote:
> 
>> Hi Roger,
>>
>> On Wed, 23 Apr 2014, Roger Quadros wrote:
>>
>>> From: Nikhil Devshatwar <nikhil.nd@ti.com>
>>>
>>> Add hwmods for ocp2scp3 and sata modules.
>>>
>>> [Roger Q] Clean up.
>>
>> Sorry for the delay on this.  Have been corresponding with TI to figure 
>> out what to do about these DRA7xx/AM43xx patches, since I don't have 
>> boards or public documentation for these devices, so it's impossible for 
>> me to meaningfully review the patches.  Looks like boards and/or public 
>> docs won't be coming any time soon.
>>
>> So for my part, here's what I'll need to merge any hwmod patches that 
>> involve AM437x or DRA7xx:
>>
>> 1. A Reviewed-by: from one of the following folks (which should come from 
>> a different person than who is submitting the patches):
>>
>> Roger Quadros
>> Nishanth Menon
>> Rajendra Nayak
>> Kevin Hilman
>> Tony Lindgren
>>
>> 2. A Tested-by: from one of the following folks (who can be the same as 
>> the person who is the same as the person who is submitting the patches):
>>
>> Nishanth Menon
>> Rajendra Nayak
>> Kevin Hilman 
>> Tony Lindgren
>>
>> Once these are in place, I'd be happy to queue it for 3.16.
> 
> I've tried to clarify this a bit.  The update is below.
> 
> 
> - Paul
> 
> 
> 
> For boards that I don't have access to, that I don't have 
> documentation for, such as the AM43xx and DRA7xx), for me to merge or ack 
> SoC infrastructure or PM-related patches, I want to have:
> 
> 1. a Reviewed-by: from people who:
> 
> a. I think know something about SoC integration or PM in general, and 
> about OMAP-style integration specifically; and
> 
> b. who have a track record of doing strong and detailed reviews of that 
> code, or who have contributed significantly to that code in the past.
> 
> My initial list of those reviewers is listed above, and I am happy to 
> consider extending it or modifying that list.
> 
> 
> 2. confidence that the patch or series has been tested against a mainline 
> commit and isn't obviously breaking other things, like PM, and confidence 
> that it's not adding new runtime warnings.
> 
> I've listed an initial set of people above who I feel have proven track 
> records in testing who I'm happy to accept Tested-by:s without further 
> explanation.  I'm sure I've missed some folks and if anyone who should be 
> on that list is offended that I didn't mention them, please accept my 
> apologies.  For other folks, like yourself, who aren't on that list (yet), 
> please just specifically state:
> 
> a. what mainline commit they've tested the patch against,
> 
> b. what other prerequisite patches were needed for the patch to apply,
> 
> c. and a cut-and-paste of the serial console boot log from the boot 
> portion of the test.
> 
> in such a way that myself or someone else can easily doublecheck it. 
> 
> And frankly, I'll probably be happy to merge it.
> 
> After someone has done these three things a few times, and I gain 
> confidence that they're doing the right thing, I'm happy to add them to 
> my list.
> 
> The testing doesn't have to be expressed via a Tested-by: tag in cases 
> where you're testing as part of a Signed-off-by:.  Just be sure to state 
> those three things above as part of the patch or series message.  The boot 
> log can either be placed on a different page and linked to, or sent in 
> another public E-mail.
> 
> If you can get two or three people to do the above, that's great - the 
> more, the better.
> 
> ...
> 
> These two steps do not apply to boards that I have in my testbed or which 
> I have documentation for (although they would definitely be very welcome 
> in those cases too).
> 

Re: [PATCH v4 3/4] ARM: DRA7: hwmod: Add ocp2scp3 and sata hwmods

[Roger Quadros]

On 04/23/2014 08:35 PM, Roger Quadros wrote:
> From: Nikhil Devshatwar <nikhil.nd@ti.com>
> 
> Add hwmods for ocp2scp3 and sata modules.
> 
> [Roger Q] Clean up.
> 
> CC: Benoit Cousson <bcousson@baylibre.com>
> CC: Paul Walmsley <paul@pwsan.com>
> Signed-off-by: Balaji T K <balajitk@ti.com>
> Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
> Signed-off-by: Roger Quadros <rogerq@ti.com>

Tested-by: Roger Quadros <rogerq@ti.com>
against 3.16-rc1, no dependency patches needed.

Nishant/Rajendra,

Could you please review this? We need this for 3.16 SATA support and
Paul won't take this in without your reviewed-by tag. Thanks.

cheers,
-roger

> ---
>  arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 31 ++++++++++++++++++++++++++-----
>  1 file changed, 26 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> index 810c205..b02a4ab 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> @@ -1215,6 +1215,30 @@ static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
>  	},
>  };
>  
> +/* ocp2scp3 */
> +static struct omap_hwmod dra7xx_ocp2scp3_hwmod;
> +
> +/* l4_cfg -> ocp2scp3 */
> +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
> +	.master		= &dra7xx_l4_cfg_hwmod,
> +	.slave		= &dra7xx_ocp2scp3_hwmod,
> +	.clk		= "l4_root_clk_div",
> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
> +	.name		= "ocp2scp3",
> +	.class		= &dra7xx_ocp2scp_hwmod_class,
> +	.clkdm_name	= "l3init_clkdm",
> +	.prcm = {
> +		.omap4 = {
> +			.clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
> +			.context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
> +			.modulemode   = MODULEMODE_HWCTRL,
> +		},
> +	},
> +};
> +
>  /*
>   * 'qspi' class
>   *
> @@ -1268,9 +1292,6 @@ static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
>  };
>  
>  /* sata */
> -static struct omap_hwmod_opt_clk sata_opt_clks[] = {
> -	{ .role = "ref_clk", .clk = "sata_ref_clk" },
> -};
>  
>  static struct omap_hwmod dra7xx_sata_hwmod = {
>  	.name		= "sata",
> @@ -1278,6 +1299,7 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
>  	.clkdm_name	= "l3init_clkdm",
>  	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
>  	.main_clk	= "func_48m_fclk",
> +	.mpu_rt_idx	= 1,
>  	.prcm = {
>  		.omap4 = {
>  			.clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
> @@ -1285,8 +1307,6 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
>  			.modulemode   = MODULEMODE_SWCTRL,
>  		},
>  	},
> -	.opt_clks	= sata_opt_clks,
> -	.opt_clks_cnt	= ARRAY_SIZE(sata_opt_clks),
>  };
>  
>  /*
> @@ -2682,6 +2702,7 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
>  	&dra7xx_l4_per1__mmc4,
>  	&dra7xx_l4_cfg__mpu,
>  	&dra7xx_l4_cfg__ocp2scp1,
> +	&dra7xx_l4_cfg__ocp2scp3,
>  	&dra7xx_l3_main_1__qspi,
>  	&dra7xx_l4_cfg__sata,
>  	&dra7xx_l4_cfg__smartreflex_core,
> 

Re: [PATCH v4 3/4] ARM: DRA7: hwmod: Add ocp2scp3 and sata hwmods

[Rajendra Nayak]

On Wednesday 18 June 2014 01:32 PM, Roger Quadros wrote:
> On 04/23/2014 08:35 PM, Roger Quadros wrote:
>> From: Nikhil Devshatwar <nikhil.nd@ti.com>
>>
>> Add hwmods for ocp2scp3 and sata modules.

>From what I see this is actually adding the ocp2scp3 data and fixing up some
of the sata data which is already added and erroneous.

It would help if this is split up and the changelog explains whats fixed up for
sata and why. Like for instance I see the opt clock data being removed but no
mention of why.
 
>>
>> [Roger Q] Clean up.
>>
>> CC: Benoit Cousson <bcousson@baylibre.com>
>> CC: Paul Walmsley <paul@pwsan.com>
>> Signed-off-by: Balaji T K <balajitk@ti.com>
>> Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
>> Signed-off-by: Roger Quadros <rogerq@ti.com>
> 
> Tested-by: Roger Quadros <rogerq@ti.com>
> against 3.16-rc1, no dependency patches needed.
> 
> Nishant/Rajendra,
> 
> Could you please review this? We need this for 3.16 SATA support and
> Paul won't take this in without your reviewed-by tag. Thanks.
> 
> cheers,
> -roger
> 
>> ---
>>  arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 31 ++++++++++++++++++++++++++-----
>>  1 file changed, 26 insertions(+), 5 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
>> index 810c205..b02a4ab 100644
>> --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
>> +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
>> @@ -1215,6 +1215,30 @@ static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
>>  	},
>>  };
>>  
>> +/* ocp2scp3 */
>> +static struct omap_hwmod dra7xx_ocp2scp3_hwmod;
>> +
>> +/* l4_cfg -> ocp2scp3 */
>> +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
>> +	.master		= &dra7xx_l4_cfg_hwmod,
>> +	.slave		= &dra7xx_ocp2scp3_hwmod,
>> +	.clk		= "l4_root_clk_div",
>> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
>> +};

All hwmod data files are organized in a certain way with all the hwmod/IP block info on top
and Interface structs at the bottom. Can we follow the same for ocp2scp3? It helps with better
readability.
 
>> +
>> +static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
>> +	.name		= "ocp2scp3",
>> +	.class		= &dra7xx_ocp2scp_hwmod_class,
>> +	.clkdm_name	= "l3init_clkdm",

No main_clk?

regards,
Rajendra

>> +	.prcm = {
>> +		.omap4 = {
>> +			.clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
>> +			.context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
>> +			.modulemode   = MODULEMODE_HWCTRL,
>> +		},
>> +	},
>> +};
>> +
>>  /*
>>   * 'qspi' class
>>   *
>> @@ -1268,9 +1292,6 @@ static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
>>  };
>>  
>>  /* sata */
>> -static struct omap_hwmod_opt_clk sata_opt_clks[] = {
>> -	{ .role = "ref_clk", .clk = "sata_ref_clk" },
>> -};
>>  
>>  static struct omap_hwmod dra7xx_sata_hwmod = {
>>  	.name		= "sata",
>> @@ -1278,6 +1299,7 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
>>  	.clkdm_name	= "l3init_clkdm",
>>  	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
>>  	.main_clk	= "func_48m_fclk",
>> +	.mpu_rt_idx	= 1,
>>  	.prcm = {
>>  		.omap4 = {
>>  			.clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
>> @@ -1285,8 +1307,6 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
>>  			.modulemode   = MODULEMODE_SWCTRL,
>>  		},
>>  	},
>> -	.opt_clks	= sata_opt_clks,
>> -	.opt_clks_cnt	= ARRAY_SIZE(sata_opt_clks),
>>  };
>>  
>>  /*
>> @@ -2682,6 +2702,7 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
>>  	&dra7xx_l4_per1__mmc4,
>>  	&dra7xx_l4_cfg__mpu,
>>  	&dra7xx_l4_cfg__ocp2scp1,
>> +	&dra7xx_l4_cfg__ocp2scp3,
>>  	&dra7xx_l3_main_1__qspi,
>>  	&dra7xx_l4_cfg__sata,
>>  	&dra7xx_l4_cfg__smartreflex_core,
>>
> 

Re: [PATCH v4 3/4] ARM: DRA7: hwmod: Add ocp2scp3 and sata hwmods

[Roger Quadros]

On 06/18/2014 01:29 PM, Rajendra Nayak wrote:
> On Wednesday 18 June 2014 01:32 PM, Roger Quadros wrote:
>> On 04/23/2014 08:35 PM, Roger Quadros wrote:
>>> From: Nikhil Devshatwar <nikhil.nd@ti.com>
>>>
>>> Add hwmods for ocp2scp3 and sata modules.
> 
> From what I see this is actually adding the ocp2scp3 data and fixing up some
> of the sata data which is already added and erroneous.
> 
> It would help if this is split up and the changelog explains whats fixed up for
> sata and why. Like for instance I see the opt clock data being removed but no
> mention of why.

OK. I will split this up into 2 patches, one to add ocp2scp3 data and the other to fix sata hwmod.

cheers,
-roger

>  
>>>
>>> [Roger Q] Clean up.
>>>
>>> CC: Benoit Cousson <bcousson@baylibre.com>
>>> CC: Paul Walmsley <paul@pwsan.com>
>>> Signed-off-by: Balaji T K <balajitk@ti.com>
>>> Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
>>> Signed-off-by: Roger Quadros <rogerq@ti.com>
>>
>> Tested-by: Roger Quadros <rogerq@ti.com>
>> against 3.16-rc1, no dependency patches needed.
>>
>> Nishant/Rajendra,
>>
>> Could you please review this? We need this for 3.16 SATA support and
>> Paul won't take this in without your reviewed-by tag. Thanks.
>>
>> cheers,
>> -roger
>>
>>> ---
>>>  arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 31 ++++++++++++++++++++++++++-----
>>>  1 file changed, 26 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
>>> index 810c205..b02a4ab 100644
>>> --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
>>> +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
>>> @@ -1215,6 +1215,30 @@ static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
>>>  	},
>>>  };
>>>  
>>> +/* ocp2scp3 */
>>> +static struct omap_hwmod dra7xx_ocp2scp3_hwmod;
>>> +
>>> +/* l4_cfg -> ocp2scp3 */
>>> +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
>>> +	.master		= &dra7xx_l4_cfg_hwmod,
>>> +	.slave		= &dra7xx_ocp2scp3_hwmod,
>>> +	.clk		= "l4_root_clk_div",
>>> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
>>> +};
> 
> All hwmod data files are organized in a certain way with all the hwmod/IP block info on top
> and Interface structs at the bottom. Can we follow the same for ocp2scp3? It helps with better
> readability.
>  
>>> +
>>> +static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
>>> +	.name		= "ocp2scp3",
>>> +	.class		= &dra7xx_ocp2scp_hwmod_class,
>>> +	.clkdm_name	= "l3init_clkdm",
> 
> No main_clk?
> 
> regards,
> Rajendra
> 
>>> +	.prcm = {
>>> +		.omap4 = {
>>> +			.clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
>>> +			.context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
>>> +			.modulemode   = MODULEMODE_HWCTRL,
>>> +		},
>>> +	},
>>> +};
>>> +
>>>  /*
>>>   * 'qspi' class
>>>   *
>>> @@ -1268,9 +1292,6 @@ static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
>>>  };
>>>  
>>>  /* sata */
>>> -static struct omap_hwmod_opt_clk sata_opt_clks[] = {
>>> -	{ .role = "ref_clk", .clk = "sata_ref_clk" },
>>> -};
>>>  
>>>  static struct omap_hwmod dra7xx_sata_hwmod = {
>>>  	.name		= "sata",
>>> @@ -1278,6 +1299,7 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
>>>  	.clkdm_name	= "l3init_clkdm",
>>>  	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
>>>  	.main_clk	= "func_48m_fclk",
>>> +	.mpu_rt_idx	= 1,
>>>  	.prcm = {
>>>  		.omap4 = {
>>>  			.clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
>>> @@ -1285,8 +1307,6 @@ static struct omap_hwmod dra7xx_sata_hwmod = {
>>>  			.modulemode   = MODULEMODE_SWCTRL,
>>>  		},
>>>  	},
>>> -	.opt_clks	= sata_opt_clks,
>>> -	.opt_clks_cnt	= ARRAY_SIZE(sata_opt_clks),
>>>  };
>>>  
>>>  /*
>>> @@ -2682,6 +2702,7 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
>>>  	&dra7xx_l4_per1__mmc4,
>>>  	&dra7xx_l4_cfg__mpu,
>>>  	&dra7xx_l4_cfg__ocp2scp1,
>>> +	&dra7xx_l4_cfg__ocp2scp3,
>>>  	&dra7xx_l3_main_1__qspi,
>>>  	&dra7xx_l4_cfg__sata,
>>>  	&dra7xx_l4_cfg__smartreflex_core,
>>>
>>
>