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From: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
To: Murali Karicheri <m-karicheri2@ti.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
	Richard Zhu <r65037@freescale.com>, Marek Vasut <marex@denx.de>,
	Randy Dunlap <rdunlap@infradead.org>,
	Russell King <linux@arm.linux.org.uk>,
	Pawel Moll <pawel.moll@arm.com>, Arnd Bergmann <arnd@arndb.de>,
	Ian Campbell <ijc+devicetree@hellion.org.uk>,
	linux-pci@vger.kernel.org, Jingoo Han <jg1.han@samsung.com>,
	linux-kernel@vger.kernel.org,
	Kishon Vijay Abraham I <kishon@ti.com>,
	Rob Herring <robh+dt@kernel.org>,
	Santosh Shilimkar <santosh.shilimkar@ti.com>,
	Kumar Gala <galak@codeaurora.org>,
	Grant Likely <grant.likely@linaro.org>,
	Mark Rutland <mark.rutland@arm.com>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v7 4/5] PCI: add PCI controller for keystone PCIe h/w
Date: Wed, 30 Jul 2014 14:05:13 -0600	[thread overview]
Message-ID: <20140730200513.GA11918@obsidianresearch.com> (raw)
In-Reply-To: <53D948D4.6080603@ti.com>

On Wed, Jul 30, 2014 at 03:34:44PM -0400, Murali Karicheri wrote:

> • Maximum remote read request size of 256 bytes

The PCI spec simply does not permit a completer to impose this
limitation.

See spec 2.3.1.1

It is not an option to error a read request because it is too
long. All requests must be completed. All completions must be segmented
according to the RCB and Max_Payload_Size.

> completion packets. So it seems to be able to segment up to maximum
> 256 bytes of read request. Where do I find the requirement in PCI
> spec that "read response segmentation at the host bridge does not
> work" ?

You just said it. Segmenting up to only 256 bytes is not a limitation
the completer can impose. Such a device is non-conformant.

> >So, the only fix is that every downstream device must always have a
> >MRSS set to less than the MPS of the host bridge.
> 
> Why this can't be the default behavior in the PCI core? Any cons?

It increases read request traffic and read response latency on the bus
for large transfers.

The MRSS is intented as a performance tuning knob, it is not something
that ever needs to be set properly for correct bus operation.

Jason

  reply	other threads:[~2014-07-30 20:05 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-07-21 16:58 [PATCH v7 0/5] Add Keystone PCIe controller driver Murali Karicheri
2014-07-21 16:58 ` [PATCH v7 1/5] PCI: designware: add rd[wr]_other_conf API Murali Karicheri
2014-07-21 16:58 ` [PATCH v7 2/5] PCI: designware: refactor MSI code to work with v3.65 dw hardware Murali Karicheri
2014-07-21 16:58 ` [PATCH v7 3/5] PCI: designware: enhance dw_pcie_host_init() to support v3.65 DW hardware Murali Karicheri
2014-07-23  1:27   ` Jingoo Han
2014-07-21 16:58 ` [PATCH v7 4/5] PCI: add PCI controller for keystone PCIe h/w Murali Karicheri
2014-07-22 22:35   ` Bjorn Helgaas
2014-07-22 22:52     ` Murali Karicheri
2014-07-22 23:52       ` Bjorn Helgaas
2014-07-23 17:42         ` Jason Gunthorpe
2014-07-30 19:34           ` Murali Karicheri
2014-07-30 20:05             ` Jason Gunthorpe [this message]
2014-08-06 14:38               ` Murali Karicheri
2014-07-21 16:58 ` [PATCH v7 5/5] PCI: keystone: Update maintainer information Murali Karicheri
2014-07-22 22:57 ` [PATCH v7 0/5] Add Keystone PCIe controller driver Bjorn Helgaas
2014-07-23 15:27   ` Murali Karicheri
2014-07-23 16:43     ` Bjorn Helgaas
2014-07-23 16:56       ` Murali Karicheri
2014-08-18 14:58       ` Murali Karicheri

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