From: Boris Brezillon <boris.brezillon@free-electrons.com>
To: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Gregory Clement <gregory.clement@free-electrons.com>,
Jason Cooper <jason@lakedaemon.net>, Andrew Lunn <andrew@lunn.ch>,
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
Ezequiel Garcia <ezequiel.garcia@free-electrons.com>,
Brian Norris <computersforpeace@gmail.com>,
linux-mtd@lists.infradead.org,
Boris Brezillon <boris@free-electrons.com>,
Thomas Petazzoni <thomas@free-electrons.com>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Tawfik Bayouk <tawfik@marvell.com>,
Nadav Haklai <nadavh@marvell.com>,
Lior Amsalem <alior@marvell.com>,
Sudhakar Gundubogula <sudhakar@marvell.com>,
Seif Mazareeb <seif@marvell.com>, <stable@vger.kernel.org>
Subject: Re: [PATCH v3 1/2] mtd: nand: pxa3xx: Fix PIO FIFO draining
Date: Mon, 16 Feb 2015 14:34:18 +0100 [thread overview]
Message-ID: <20150216143418.3984652c@bbrezillon> (raw)
In-Reply-To: <1424091072-7738-2-git-send-email-maxime.ripard@free-electrons.com>
Hi Maxime,
On Mon, 16 Feb 2015 13:51:11 +0100
Maxime Ripard <maxime.ripard@free-electrons.com> wrote:
> The NDDB register holds the data that are needed by the read and write
> commands.
>
> However, during a read PIO access, the datasheet specifies that after each 32
> bits read in that register, when BCH is enabled, we have to make sure that the
> RDDREQ bit is set in the NDSR register.
>
> This fixes an issue that was seen on the Armada 385, and presumably other mvebu
> SoCs, when a read on a newly erased page would end up in the driver reporting a
> timeout from the NAND.
>
> Cc: <stable@vger.kernel.org> # v3.14
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
> drivers/mtd/nand/pxa3xx_nand.c | 47 ++++++++++++++++++++++++++++++++++++------
> 1 file changed, 41 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
> index 96b0b1d27df1..b2d8d6960765 100644
> --- a/drivers/mtd/nand/pxa3xx_nand.c
> +++ b/drivers/mtd/nand/pxa3xx_nand.c
> @@ -480,6 +480,41 @@ static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
> nand_writel(info, NDCR, ndcr | int_mask);
> }
>
> +static void drain_fifo(struct pxa3xx_nand_info *info, void *data, int len)
> +{
> + if (info->ecc_bch) {
> + int index = 0;
> +
> + while (index < (len * 4)) {
> + u32 timeout;
> +
> + __raw_readsl(info->mmio_base + NDDB, data + index, 8);
> +
Shouldn't you break here if you've read all the data you were
expecting ?
As I said in my previous review, I don't know what's happening if you
wait for RDDREQ when the FIFO has been fully drained.
> + /*
> + * According to the datasheet, when reading
> + * from NDDB with BCH enabled, after each 32
> + * bytes reads, we have to make sure that the
> + * NDSR.RDDREQ bit is set
> + */
> + for (timeout = 0;
> + !(nand_readl(info, NDSR) & NDSR_RDDREQ);
> + timeout++) {
> + if (timeout >= 5) {
> + dev_err(&info->pdev->dev,
> + "Timeout on RDDREQ while draining the FIFO\n");
> + return;
> + }
> +
> + mdelay(1);
> + }
> +
> + index += 32;
> + }
> + } else {
> + __raw_readsl(info->mmio_base + NDDB, data, len);
> + }
> +}
Best Regards,
Boris
--
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
next prev parent reply other threads:[~2015-02-16 13:34 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-02-16 12:51 [PATCH v3 0/2] ARM: mvebu: a385-db-ap: Enable the NAND controller Maxime Ripard
2015-02-16 12:51 ` [PATCH v3 1/2] mtd: nand: pxa3xx: Fix PIO FIFO draining Maxime Ripard
2015-02-16 13:34 ` Boris Brezillon [this message]
2015-02-16 13:35 ` Ezequiel Garcia
2015-02-16 16:49 ` Maxime Ripard
2015-02-16 16:27 ` Thomas Petazzoni
2015-02-16 16:41 ` Maxime Ripard
2015-02-16 16:57 ` Ezequiel Garcia
2015-02-17 10:29 ` Maxime Ripard
2015-02-16 20:11 ` Robert Jarzmik
2015-02-16 20:58 ` Maxime Ripard
2015-02-16 21:36 ` Robert Jarzmik
2015-02-17 9:47 ` Maxime Ripard
2015-02-17 10:37 ` Maxime Ripard
2015-02-17 17:07 ` Robert Jarzmik
2015-02-17 17:16 ` Ezequiel Garcia
2015-02-24 3:45 ` Brian Norris
2015-02-24 8:17 ` Maxime Ripard
2015-02-16 12:51 ` [PATCH v3 2/2] ARM: mvebu: a385-db-ap: Enable the NAND Maxime Ripard
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