* [PATCH v3 1/7] ARM: at91: switch to multiplatform
2015-03-13 21:57 [PATCH v3 0/7] Switch mach-at91 to multiplatform Alexandre Belloni
@ 2015-03-13 21:57 ` Alexandre Belloni
2015-03-13 21:57 ` [PATCH v3 2/7] ARM: at91: switch at91_dt_defconfig " Alexandre Belloni
` (7 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Alexandre Belloni @ 2015-03-13 21:57 UTC (permalink / raw)
To: Nicolas Ferre
Cc: Boris Brezillon, Jean-Christophe Plagniol-Villard, Arnd Bergmann,
linux-kernel, linux-arm-kernel, Alexandre Belloni
Switch AT91 to multiplatform as all SoCs are properly handled.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/Kconfig | 13 -----
arch/arm/mach-at91/Kconfig | 119 +++++++++++++++++++-------------------------
arch/arm/mach-at91/Makefile | 2 +
3 files changed, 52 insertions(+), 82 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f6c5b05e8de8..a1d153098001 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -356,19 +356,6 @@ config ARCH_VERSATILE
help
This enables support for ARM Ltd Versatile board.
-config ARCH_AT91
- bool "Atmel AT91"
- select ARCH_REQUIRE_GPIOLIB
- select CLKDEV_LOOKUP
- select IRQ_DOMAIN
- select PINCTRL
- select PINCTRL_AT91
- select SOC_BUS
- select USE_OF
- help
- This enables support for systems based on Atmel
- AT91RM9200, AT91SAM9 and SAMA5 processors.
-
config ARCH_CLPS711X
bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
select ARCH_REQUIRE_GPIOLIB
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 4da6bae047f3..4662eae06753 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -1,55 +1,14 @@
-if ARCH_AT91
-
-config HAVE_AT91_UTMI
- bool
-
-config HAVE_AT91_USB_CLK
- bool
-
-config COMMON_CLK_AT91
- bool
- select COMMON_CLK
-
-config HAVE_AT91_SMD
- bool
-
-config HAVE_AT91_H32MX
- bool
-
-config SOC_SAMA5
- bool
- select ATMEL_AIC5_IRQ
+menuconfig ARCH_AT91
+ bool "Atmel SoCs"
+ select ARCH_REQUIRE_GPIOLIB
select COMMON_CLK_AT91
- select CPU_V7
- select GENERIC_CLOCKEVENTS
- select MEMORY
- select ATMEL_SDRAMC
- select SRAM if PM
-
-menu "Atmel AT91 System-on-Chip"
-
-choice
-
- prompt "Core type"
-
-config SOC_SAM_V4_V5
- bool "ARM9 AT91SAM9/AT91RM9200"
- help
- Select this if you are using one of Atmel's AT91SAM9 or
- AT91RM9200 SoC.
-
-config SOC_SAM_V7
- bool "Cortex A5"
- help
- Select this if you are using one of Atmel's SAMA5D3 SoC.
-
-endchoice
-
-comment "Atmel AT91 Processor"
+ select PINCTRL
+ select PINCTRL_AT91
+ select SOC_BUS
-if SOC_SAM_V7
+if ARCH_AT91
config SOC_SAMA5D3
- bool "SAMA5D3 family"
+ bool "SAMA5D3 family" if ARCH_MULTI_V7
select SOC_SAMA5
select HAVE_FB_ATMEL
select HAVE_AT91_UTMI
@@ -60,9 +19,8 @@ config SOC_SAMA5D3
This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36.
config SOC_SAMA5D4
- bool "SAMA5D4 family"
+ bool "SAMA5D4 family" if ARCH_MULTI_V7
select SOC_SAMA5
- select CLKSRC_MMIO
select CACHE_L2X0
select HAVE_FB_ATMEL
select HAVE_AT91_UTMI
@@ -71,31 +29,27 @@ config SOC_SAMA5D4
select HAVE_AT91_H32MX
help
Select this if you are using one of Atmel's SAMA5D4 family SoC.
-endif
-if SOC_SAM_V4_V5
config SOC_AT91RM9200
- bool "AT91RM9200"
+ bool "AT91RM9200" if ARCH_MULTI_V4T
select ATMEL_AIC_IRQ
- select COMMON_CLK_AT91
select CPU_ARM920T
- select GENERIC_CLOCKEVENTS
select HAVE_AT91_USB_CLK
select MIGHT_HAVE_PCI
+ select SOC_SAM_V4_V5
select SRAM if PM
config SOC_AT91SAM9
- bool "AT91SAM9"
+ bool "AT91SAM9" if ARCH_MULTI_V5
select ATMEL_AIC_IRQ
select ATMEL_SDRAMC
- select COMMON_CLK_AT91
select CPU_ARM926T
- select GENERIC_CLOCKEVENTS
select HAVE_AT91_SMD
select HAVE_AT91_USB_CLK
select HAVE_AT91_UTMI
select HAVE_FB_ATMEL
select MEMORY
+ select SOC_SAM_V4_V5
select SRAM if PM
help
Select this if you are using one of those Atmel SoC:
@@ -115,17 +69,46 @@ config SOC_AT91SAM9
AT91SAM9X25
AT91SAM9X35
AT91SAM9XE
-endif # SOC_SAM_V4_V5
-comment "AT91 Feature Selections"
+config HAVE_AT91_UTMI
+ bool
+
+config HAVE_AT91_USB_CLK
+ bool
+
+config COMMON_CLK_AT91
+ bool
+ select COMMON_CLK
+
+config HAVE_AT91_SMD
+ bool
+
+config HAVE_AT91_H32MX
+ bool
+
+config SOC_SAM_V4_V5
+ bool
+
+config SOC_SAM_V7
+ bool
+
+config SOC_SAMA5
+ bool
+ select ATMEL_AIC5_IRQ
+ select ATMEL_SDRAMC
+ select MEMORY
+ select SOC_SAM_V7
+ select SRAM if PM
+
+comment "Atmel SoCs Feature Selections"
config AT91_TIMER_HZ
- int "Kernel HZ (jiffies per second)"
- range 32 1024
- depends on ARCH_AT91
- default "128" if SOC_AT91RM9200
- default "100"
- help
+ int "Kernel HZ (jiffies per second)"
+ range 32 1024
+ depends on ARCH_AT91
+ default "128" if SOC_AT91RM9200
+ default "100"
+ help
On AT91rm9200 chips where you're using a system clock derived
from the 32768 Hz hardware clock, this tick rate should divide
it exactly: use a power-of-two value, such as 128 or 256, to
@@ -135,6 +118,4 @@ config AT91_TIMER_HZ
system clock (of at least several MHz), rounding is less of a
problem so it can be safer to use a decimal values like 100.
-endmenu
-
endif
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index ea54c9824d89..78d521e93ce9 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -1,6 +1,8 @@
#
# Makefile for the linux kernel.
#
+ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
+asflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
obj-y := soc.o
--
2.1.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v3 2/7] ARM: at91: switch at91_dt_defconfig to multiplatform
2015-03-13 21:57 [PATCH v3 0/7] Switch mach-at91 to multiplatform Alexandre Belloni
2015-03-13 21:57 ` [PATCH v3 1/7] ARM: at91: switch " Alexandre Belloni
@ 2015-03-13 21:57 ` Alexandre Belloni
2015-03-13 21:57 ` [PATCH v3 3/7] ARM: at91: remove unused headers Alexandre Belloni
` (6 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Alexandre Belloni @ 2015-03-13 21:57 UTC (permalink / raw)
To: Nicolas Ferre
Cc: Boris Brezillon, Jean-Christophe Plagniol-Villard, Arnd Bergmann,
linux-kernel, linux-arm-kernel, Alexandre Belloni
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/configs/at91_dt_defconfig | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig
index 811e72bbe642..bcef49a21801 100644
--- a/arch/arm/configs/at91_dt_defconfig
+++ b/arch/arm/configs/at91_dt_defconfig
@@ -13,10 +13,13 @@ CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
+CONFIG_ARCH_MULTI_V4T=y
+CONFIG_ARCH_MULTI_V5=y
+# CONFIG_ARCH_MULTI_V7 is not set
CONFIG_ARCH_AT91=y
+CONFIG_SOC_SAM_V4_V5=y
CONFIG_SOC_AT91RM9200=y
CONFIG_SOC_AT91SAM9=y
-CONFIG_AT91_TIMER_HZ=128
CONFIG_AEABI=y
CONFIG_UACCESS_WITH_MEMCPY=y
CONFIG_ZBOOT_ROM_TEXT=0x0
--
2.1.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v3 3/7] ARM: at91: remove unused headers
2015-03-13 21:57 [PATCH v3 0/7] Switch mach-at91 to multiplatform Alexandre Belloni
2015-03-13 21:57 ` [PATCH v3 1/7] ARM: at91: switch " Alexandre Belloni
2015-03-13 21:57 ` [PATCH v3 2/7] ARM: at91: switch at91_dt_defconfig " Alexandre Belloni
@ 2015-03-13 21:57 ` Alexandre Belloni
2015-03-13 21:57 ` [PATCH v3 4/7] ARM: at91: remove useless mach/cpu.h Alexandre Belloni
` (5 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Alexandre Belloni @ 2015-03-13 21:57 UTC (permalink / raw)
To: Nicolas Ferre
Cc: Boris Brezillon, Jean-Christophe Plagniol-Villard, Arnd Bergmann,
linux-kernel, linux-arm-kernel, Alexandre Belloni
Following the switch to multiplatform, uncompress.h is not used anymore. Remove
it.
at91_dbgu.h is also not used anymore
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/mach-at91/include/mach/at91_dbgu.h | 63 --------
arch/arm/mach-at91/include/mach/uncompress.h | 218 ---------------------------
2 files changed, 281 deletions(-)
delete mode 100644 arch/arm/mach-at91/include/mach/at91_dbgu.h
delete mode 100644 arch/arm/mach-at91/include/mach/uncompress.h
diff --git a/arch/arm/mach-at91/include/mach/at91_dbgu.h b/arch/arm/mach-at91/include/mach/at91_dbgu.h
deleted file mode 100644
index 42925e8f78e4..000000000000
--- a/arch/arm/mach-at91/include/mach/at91_dbgu.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91_dbgu.h
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- *
- * Debug Unit (DBGU) - System peripherals registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_DBGU_H
-#define AT91_DBGU_H
-
-#define AT91_DBGU_CR (0x00) /* Control Register */
-#define AT91_DBGU_MR (0x04) /* Mode Register */
-#define AT91_DBGU_IER (0x08) /* Interrupt Enable Register */
-#define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */
-#define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */
-#define AT91_DBGU_IDR (0x0c) /* Interrupt Disable Register */
-#define AT91_DBGU_IMR (0x10) /* Interrupt Mask Register */
-#define AT91_DBGU_SR (0x14) /* Status Register */
-#define AT91_DBGU_RHR (0x18) /* Receiver Holding Register */
-#define AT91_DBGU_THR (0x1c) /* Transmitter Holding Register */
-#define AT91_DBGU_BRGR (0x20) /* Baud Rate Generator Register */
-
-#define AT91_DBGU_CIDR (0x40) /* Chip ID Register */
-#define AT91_DBGU_EXID (0x44) /* Chip ID Extension Register */
-#define AT91_DBGU_FNR (0x48) /* Force NTRST Register [SAM9 only] */
-#define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */
-
-/*
- * Some AT91 parts that don't have full DEBUG units still support the ID
- * and extensions register.
- */
-#define AT91_CIDR_VERSION (0x1f << 0) /* Version of the Device */
-#define AT91_CIDR_EPROC (7 << 5) /* Embedded Processor */
-#define AT91_CIDR_NVPSIZ (0xf << 8) /* Nonvolatile Program Memory Size */
-#define AT91_CIDR_NVPSIZ2 (0xf << 12) /* Second Nonvolatile Program Memory Size */
-#define AT91_CIDR_SRAMSIZ (0xf << 16) /* Internal SRAM Size */
-#define AT91_CIDR_SRAMSIZ_1K (1 << 16)
-#define AT91_CIDR_SRAMSIZ_2K (2 << 16)
-#define AT91_CIDR_SRAMSIZ_112K (4 << 16)
-#define AT91_CIDR_SRAMSIZ_4K (5 << 16)
-#define AT91_CIDR_SRAMSIZ_80K (6 << 16)
-#define AT91_CIDR_SRAMSIZ_160K (7 << 16)
-#define AT91_CIDR_SRAMSIZ_8K (8 << 16)
-#define AT91_CIDR_SRAMSIZ_16K (9 << 16)
-#define AT91_CIDR_SRAMSIZ_32K (10 << 16)
-#define AT91_CIDR_SRAMSIZ_64K (11 << 16)
-#define AT91_CIDR_SRAMSIZ_128K (12 << 16)
-#define AT91_CIDR_SRAMSIZ_256K (13 << 16)
-#define AT91_CIDR_SRAMSIZ_96K (14 << 16)
-#define AT91_CIDR_SRAMSIZ_512K (15 << 16)
-#define AT91_CIDR_ARCH (0xff << 20) /* Architecture Identifier */
-#define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */
-#define AT91_CIDR_EXT (1 << 31) /* Extension Flag */
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/uncompress.h b/arch/arm/mach-at91/include/mach/uncompress.h
deleted file mode 100644
index 4ebb609369e3..000000000000
--- a/arch/arm/mach-at91/include/mach/uncompress.h
+++ /dev/null
@@ -1,218 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/uncompress.h
- *
- * Copyright (C) 2003 SAN People
- * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_UNCOMPRESS_H
-#define __ASM_ARCH_UNCOMPRESS_H
-
-#include <linux/io.h>
-#include <linux/atmel_serial.h>
-#include <mach/hardware.h>
-
-#include <mach/at91_dbgu.h>
-#include <mach/cpu.h>
-
-void __iomem *at91_uart;
-
-static const u32 uarts_rm9200[] = {
- AT91_BASE_DBGU0,
- AT91RM9200_BASE_US0,
- AT91RM9200_BASE_US1,
- AT91RM9200_BASE_US2,
- AT91RM9200_BASE_US3,
- 0,
-};
-
-static const u32 uarts_sam9260[] = {
- AT91_BASE_DBGU0,
- AT91SAM9260_BASE_US0,
- AT91SAM9260_BASE_US1,
- AT91SAM9260_BASE_US2,
- AT91SAM9260_BASE_US3,
- AT91SAM9260_BASE_US4,
- AT91SAM9260_BASE_US5,
- 0,
-};
-
-static const u32 uarts_sam9261[] = {
- AT91_BASE_DBGU0,
- AT91SAM9261_BASE_US0,
- AT91SAM9261_BASE_US1,
- AT91SAM9261_BASE_US2,
- 0,
-};
-
-static const u32 uarts_sam9263[] = {
- AT91_BASE_DBGU1,
- AT91SAM9263_BASE_US0,
- AT91SAM9263_BASE_US1,
- AT91SAM9263_BASE_US2,
- 0,
-};
-
-static const u32 uarts_sam9g45[] = {
- AT91_BASE_DBGU1,
- AT91SAM9G45_BASE_US0,
- AT91SAM9G45_BASE_US1,
- AT91SAM9G45_BASE_US2,
- AT91SAM9G45_BASE_US3,
- 0,
-};
-
-static const u32 uarts_sam9rl[] = {
- AT91_BASE_DBGU0,
- AT91SAM9RL_BASE_US0,
- AT91SAM9RL_BASE_US1,
- AT91SAM9RL_BASE_US2,
- AT91SAM9RL_BASE_US3,
- 0,
-};
-
-static const u32 uarts_sam9x5[] = {
- AT91_BASE_DBGU0,
- AT91SAM9X5_BASE_USART0,
- AT91SAM9X5_BASE_USART1,
- AT91SAM9X5_BASE_USART2,
- 0,
-};
-
-static const u32 uarts_sama5d3[] = {
- AT91_BASE_DBGU1,
- SAMA5D3_BASE_USART0,
- SAMA5D3_BASE_USART1,
- SAMA5D3_BASE_USART2,
- SAMA5D3_BASE_USART3,
- 0,
-};
-
-static const u32 uarts_sama5d4[] = {
- AT91_BASE_DBGU2,
- SAMA5D4_BASE_USART3,
- 0,
-};
-
-static inline const u32* decomp_soc_detect(void __iomem *dbgu_base)
-{
- u32 cidr, socid;
-
- cidr = __raw_readl(dbgu_base + AT91_DBGU_CIDR);
- socid = cidr & ~AT91_CIDR_VERSION;
-
- switch (socid) {
- case ARCH_ID_AT91RM9200:
- return uarts_rm9200;
-
- case ARCH_ID_AT91SAM9G20:
- case ARCH_ID_AT91SAM9260:
- return uarts_sam9260;
-
- case ARCH_ID_AT91SAM9261:
- return uarts_sam9261;
-
- case ARCH_ID_AT91SAM9263:
- return uarts_sam9263;
-
- case ARCH_ID_AT91SAM9G45:
- return uarts_sam9g45;
-
- case ARCH_ID_AT91SAM9RL64:
- return uarts_sam9rl;
-
- case ARCH_ID_AT91SAM9N12:
- case ARCH_ID_AT91SAM9X5:
- return uarts_sam9x5;
-
- case ARCH_ID_SAMA5:
- cidr = __raw_readl(dbgu_base + AT91_DBGU_EXID);
- if (cidr & ARCH_EXID_SAMA5D3)
- return uarts_sama5d3;
- else if (cidr & ARCH_EXID_SAMA5D4)
- return uarts_sama5d4;
-
- break;
- }
-
- /* at91sam9g10 */
- if ((cidr & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
- return uarts_sam9261;
- }
- /* at91sam9xe */
- else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
- return uarts_sam9260;
- }
-
- return NULL;
-}
-
-static inline void arch_decomp_setup(void)
-{
- int i = 0;
- const u32* usarts;
-
- usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU0);
- if (!usarts)
- usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU1);
- if (!usarts)
- usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU2);
- if (!usarts) {
- at91_uart = NULL;
- return;
- }
-
- do {
- /* physical address */
- at91_uart = (void __iomem *)usarts[i];
-
- if (__raw_readl(at91_uart + ATMEL_US_BRGR))
- return;
- i++;
- } while (usarts[i]);
-
- at91_uart = NULL;
-}
-
-/*
- * The following code assumes the serial port has already been
- * initialized by the bootloader. If you didn't setup a port in
- * your bootloader then nothing will appear (which might be desired).
- *
- * This does not append a newline
- */
-static void putc(int c)
-{
- if (!at91_uart)
- return;
-
- while (!(__raw_readl(at91_uart + ATMEL_US_CSR) & ATMEL_US_TXRDY))
- barrier();
- __raw_writel(c, at91_uart + ATMEL_US_THR);
-}
-
-static inline void flush(void)
-{
- if (!at91_uart)
- return;
-
- /* wait for transmission to complete */
- while (!(__raw_readl(at91_uart + ATMEL_US_CSR) & ATMEL_US_TXEMPTY))
- barrier();
-}
-
-#endif
--
2.1.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v3 4/7] ARM: at91: remove useless mach/cpu.h
2015-03-13 21:57 [PATCH v3 0/7] Switch mach-at91 to multiplatform Alexandre Belloni
` (2 preceding siblings ...)
2015-03-13 21:57 ` [PATCH v3 3/7] ARM: at91: remove unused headers Alexandre Belloni
@ 2015-03-13 21:57 ` Alexandre Belloni
2015-03-13 21:57 ` [PATCH v3 5/7] ARM: at91: remove SoC headers Alexandre Belloni
` (4 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Alexandre Belloni @ 2015-03-13 21:57 UTC (permalink / raw)
To: Nicolas Ferre
Cc: Boris Brezillon, Jean-Christophe Plagniol-Villard, Arnd Bergmann,
linux-kernel, linux-arm-kernel, Alexandre Belloni
mach/cpu.h is not used anymore, remove it.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/mach-at91/include/mach/at91sam9_smc.h | 2 -
arch/arm/mach-at91/include/mach/cpu.h | 216 -------------------------
arch/arm/mach-at91/pm.c | 1 -
3 files changed, 219 deletions(-)
delete mode 100644 arch/arm/mach-at91/include/mach/cpu.h
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_smc.h b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
index 175e1fdd9fe8..ff54a0ce90e3 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_smc.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
@@ -16,8 +16,6 @@
#ifndef AT91SAM9_SMC_H
#define AT91SAM9_SMC_H
-#include <mach/cpu.h>
-
#ifndef __ASSEMBLY__
struct sam9_smc_config {
/* Setup register */
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
deleted file mode 100644
index ce7c80a44983..000000000000
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ /dev/null
@@ -1,216 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/cpu.h
- *
- * Copyright (C) 2006 SAN People
- * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-
-#ifndef __MACH_CPU_H__
-#define __MACH_CPU_H__
-
-#define ARCH_ID_AT91RM9200 0x09290780
-#define ARCH_ID_AT91SAM9260 0x019803a0
-#define ARCH_ID_AT91SAM9261 0x019703a0
-#define ARCH_ID_AT91SAM9263 0x019607a0
-#define ARCH_ID_AT91SAM9G10 0x019903a0
-#define ARCH_ID_AT91SAM9G20 0x019905a0
-#define ARCH_ID_AT91SAM9RL64 0x019b03a0
-#define ARCH_ID_AT91SAM9G45 0x819b05a0
-#define ARCH_ID_AT91SAM9G45MRL 0x819b05a2 /* aka 9G45-ES2 & non ES lots */
-#define ARCH_ID_AT91SAM9G45ES 0x819b05a1 /* 9G45-ES (Engineering Sample) */
-#define ARCH_ID_AT91SAM9X5 0x819a05a0
-#define ARCH_ID_AT91SAM9N12 0x819a07a0
-
-#define ARCH_ID_AT91SAM9XE128 0x329973a0
-#define ARCH_ID_AT91SAM9XE256 0x329a93a0
-#define ARCH_ID_AT91SAM9XE512 0x329aa3a0
-
-#define ARCH_ID_AT91M40800 0x14080044
-#define ARCH_ID_AT91R40807 0x44080746
-#define ARCH_ID_AT91M40807 0x14080745
-#define ARCH_ID_AT91R40008 0x44000840
-
-#define ARCH_ID_SAMA5 0x8A5C07C0
-
-#define ARCH_EXID_AT91SAM9M11 0x00000001
-#define ARCH_EXID_AT91SAM9M10 0x00000002
-#define ARCH_EXID_AT91SAM9G46 0x00000003
-#define ARCH_EXID_AT91SAM9G45 0x00000004
-
-#define ARCH_EXID_AT91SAM9G15 0x00000000
-#define ARCH_EXID_AT91SAM9G35 0x00000001
-#define ARCH_EXID_AT91SAM9X35 0x00000002
-#define ARCH_EXID_AT91SAM9G25 0x00000003
-#define ARCH_EXID_AT91SAM9X25 0x00000004
-
-#define ARCH_EXID_SAMA5D3 0x00004300
-#define ARCH_EXID_SAMA5D31 0x00444300
-#define ARCH_EXID_SAMA5D33 0x00414300
-#define ARCH_EXID_SAMA5D34 0x00414301
-#define ARCH_EXID_SAMA5D35 0x00584300
-#define ARCH_EXID_SAMA5D36 0x00004301
-
-#define ARCH_EXID_SAMA5D4 0x00000007
-#define ARCH_EXID_SAMA5D41 0x00000001
-#define ARCH_EXID_SAMA5D42 0x00000002
-#define ARCH_EXID_SAMA5D43 0x00000003
-#define ARCH_EXID_SAMA5D44 0x00000004
-
-#define ARCH_FAMILY_AT91SAM9 0x01900000
-#define ARCH_FAMILY_AT91SAM9XE 0x02900000
-
-/* RM9200 type */
-#define ARCH_REVISON_9200_BGA (0 << 0)
-#define ARCH_REVISON_9200_PQFP (1 << 0)
-
-#ifndef __ASSEMBLY__
-enum at91_soc_type {
- /* 920T */
- AT91_SOC_RM9200,
-
- /* SAM92xx */
- AT91_SOC_SAM9260, AT91_SOC_SAM9261, AT91_SOC_SAM9263,
-
- /* SAM9Gxx */
- AT91_SOC_SAM9G10, AT91_SOC_SAM9G20, AT91_SOC_SAM9G45,
-
- /* SAM9RL */
- AT91_SOC_SAM9RL,
-
- /* SAM9X5 */
- AT91_SOC_SAM9X5,
-
- /* SAM9N12 */
- AT91_SOC_SAM9N12,
-
- /* SAMA5D3 */
- AT91_SOC_SAMA5D3,
-
- /* SAMA5D4 */
- AT91_SOC_SAMA5D4,
-
- /* Unknown type */
- AT91_SOC_UNKNOWN,
-};
-
-enum at91_soc_subtype {
- /* RM9200 */
- AT91_SOC_RM9200_BGA, AT91_SOC_RM9200_PQFP,
-
- /* SAM9260 */
- AT91_SOC_SAM9XE,
-
- /* SAM9G45 */
- AT91_SOC_SAM9G45ES, AT91_SOC_SAM9M10, AT91_SOC_SAM9G46, AT91_SOC_SAM9M11,
-
- /* SAM9X5 */
- AT91_SOC_SAM9G15, AT91_SOC_SAM9G35, AT91_SOC_SAM9X35,
- AT91_SOC_SAM9G25, AT91_SOC_SAM9X25,
-
- /* SAMA5D3 */
- AT91_SOC_SAMA5D31, AT91_SOC_SAMA5D33, AT91_SOC_SAMA5D34,
- AT91_SOC_SAMA5D35, AT91_SOC_SAMA5D36,
-
- /* SAMA5D4 */
- AT91_SOC_SAMA5D41, AT91_SOC_SAMA5D42, AT91_SOC_SAMA5D43,
- AT91_SOC_SAMA5D44,
-
- /* No subtype for this SoC */
- AT91_SOC_SUBTYPE_NONE,
-
- /* Unknown subtype */
- AT91_SOC_SUBTYPE_UNKNOWN,
-};
-
-struct at91_socinfo {
- unsigned int type, subtype;
- unsigned int cidr, exid;
-};
-
-extern struct at91_socinfo at91_soc_initdata;
-const char *at91_get_soc_type(struct at91_socinfo *c);
-const char *at91_get_soc_subtype(struct at91_socinfo *c);
-
-static inline int at91_soc_is_detected(void)
-{
- return at91_soc_initdata.type != AT91_SOC_UNKNOWN;
-}
-
-#ifdef CONFIG_SOC_AT91RM9200
-#define cpu_is_at91rm9200() (at91_soc_initdata.type == AT91_SOC_RM9200)
-#define cpu_is_at91rm9200_bga() (at91_soc_initdata.subtype == AT91_SOC_RM9200_BGA)
-#define cpu_is_at91rm9200_pqfp() (at91_soc_initdata.subtype == AT91_SOC_RM9200_PQFP)
-#else
-#define cpu_is_at91rm9200() (0)
-#define cpu_is_at91rm9200_bga() (0)
-#define cpu_is_at91rm9200_pqfp() (0)
-#endif
-
-#ifdef CONFIG_SOC_AT91SAM9
-#define cpu_is_at91sam9xe() (at91_soc_initdata.subtype == AT91_SOC_SAM9XE)
-#define cpu_is_at91sam9260() (at91_soc_initdata.type == AT91_SOC_SAM9260)
-#define cpu_is_at91sam9g20() (at91_soc_initdata.type == AT91_SOC_SAM9G20)
-#define cpu_is_at91sam9261() (at91_soc_initdata.type == AT91_SOC_SAM9261)
-#define cpu_is_at91sam9g10() (at91_soc_initdata.type == AT91_SOC_SAM9G10)
-#define cpu_is_at91sam9263() (at91_soc_initdata.type == AT91_SOC_SAM9263)
-#define cpu_is_at91sam9rl() (at91_soc_initdata.type == AT91_SOC_SAM9RL)
-#define cpu_is_at91sam9g45() (at91_soc_initdata.type == AT91_SOC_SAM9G45)
-#define cpu_is_at91sam9g45es() (at91_soc_initdata.subtype == AT91_SOC_SAM9G45ES)
-#define cpu_is_at91sam9m10() (at91_soc_initdata.subtype == AT91_SOC_SAM9M10)
-#define cpu_is_at91sam9g46() (at91_soc_initdata.subtype == AT91_SOC_SAM9G46)
-#define cpu_is_at91sam9m11() (at91_soc_initdata.subtype == AT91_SOC_SAM9M11)
-#define cpu_is_at91sam9x5() (at91_soc_initdata.type == AT91_SOC_SAM9X5)
-#define cpu_is_at91sam9g15() (at91_soc_initdata.subtype == AT91_SOC_SAM9G15)
-#define cpu_is_at91sam9g35() (at91_soc_initdata.subtype == AT91_SOC_SAM9G35)
-#define cpu_is_at91sam9x35() (at91_soc_initdata.subtype == AT91_SOC_SAM9X35)
-#define cpu_is_at91sam9g25() (at91_soc_initdata.subtype == AT91_SOC_SAM9G25)
-#define cpu_is_at91sam9x25() (at91_soc_initdata.subtype == AT91_SOC_SAM9X25)
-#define cpu_is_at91sam9n12() (at91_soc_initdata.type == AT91_SOC_SAM9N12)
-#else
-#define cpu_is_at91sam9xe() (0)
-#define cpu_is_at91sam9260() (0)
-#define cpu_is_at91sam9g20() (0)
-#define cpu_is_at91sam9261() (0)
-#define cpu_is_at91sam9g10() (0)
-#define cpu_is_at91sam9263() (0)
-#define cpu_is_at91sam9rl() (0)
-#define cpu_is_at91sam9g45() (0)
-#define cpu_is_at91sam9g45es() (0)
-#define cpu_is_at91sam9m10() (0)
-#define cpu_is_at91sam9g46() (0)
-#define cpu_is_at91sam9m11() (0)
-#define cpu_is_at91sam9x5() (0)
-#define cpu_is_at91sam9g15() (0)
-#define cpu_is_at91sam9g35() (0)
-#define cpu_is_at91sam9x35() (0)
-#define cpu_is_at91sam9g25() (0)
-#define cpu_is_at91sam9x25() (0)
-#define cpu_is_at91sam9n12() (0)
-#endif
-
-#ifdef CONFIG_SOC_SAMA5D3
-#define cpu_is_sama5d3() (at91_soc_initdata.type == AT91_SOC_SAMA5D3)
-#else
-#define cpu_is_sama5d3() (0)
-#endif
-
-#ifdef CONFIG_SOC_SAMA5D4
-#define cpu_is_sama5d4() (at91_soc_initdata.type == AT91_SOC_SAMA5D4)
-#else
-#define cpu_is_sama5d4() (0)
-#endif
-
-/*
- * Since this is ARM, we will never run on any AVR32 CPU. But these
- * definitions may reduce clutter in common drivers.
- */
-#define cpu_is_at32ap7000() (0)
-#endif /* __ASSEMBLY__ */
-
-#endif /* __MACH_CPU_H__ */
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index ac947cdd506c..2a12c01afc67 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -32,7 +32,6 @@
#include <asm/fncpy.h>
#include <asm/cacheflush.h>
-#include <mach/cpu.h>
#include <mach/hardware.h>
#include "generic.h"
--
2.1.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v3 5/7] ARM: at91: remove SoC headers
2015-03-13 21:57 [PATCH v3 0/7] Switch mach-at91 to multiplatform Alexandre Belloni
` (3 preceding siblings ...)
2015-03-13 21:57 ` [PATCH v3 4/7] ARM: at91: remove useless mach/cpu.h Alexandre Belloni
@ 2015-03-13 21:57 ` Alexandre Belloni
2015-03-13 21:57 ` [PATCH v3 6/7] ARM: at91: remove hardware.h Alexandre Belloni
` (3 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Alexandre Belloni @ 2015-03-13 21:57 UTC (permalink / raw)
To: Nicolas Ferre
Cc: Boris Brezillon, Jean-Christophe Plagniol-Villard, Arnd Bergmann,
linux-kernel, linux-arm-kernel, Alexandre Belloni
Remove the now useless SoC headers.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/mach-at91/include/mach/at91rm9200.h | 103 -------------------
arch/arm/mach-at91/include/mach/at91sam9260.h | 129 -----------------------
arch/arm/mach-at91/include/mach/at91sam9261.h | 99 ------------------
arch/arm/mach-at91/include/mach/at91sam9263.h | 117 ---------------------
arch/arm/mach-at91/include/mach/at91sam9g45.h | 143 --------------------------
arch/arm/mach-at91/include/mach/at91sam9n12.h | 65 ------------
arch/arm/mach-at91/include/mach/at91sam9rl.h | 105 -------------------
arch/arm/mach-at91/include/mach/at91sam9x5.h | 71 -------------
arch/arm/mach-at91/include/mach/hardware.h | 11 --
arch/arm/mach-at91/include/mach/sama5d3.h | 86 ----------------
arch/arm/mach-at91/include/mach/sama5d4.h | 33 ------
11 files changed, 962 deletions(-)
delete mode 100644 arch/arm/mach-at91/include/mach/at91rm9200.h
delete mode 100644 arch/arm/mach-at91/include/mach/at91sam9260.h
delete mode 100644 arch/arm/mach-at91/include/mach/at91sam9261.h
delete mode 100644 arch/arm/mach-at91/include/mach/at91sam9263.h
delete mode 100644 arch/arm/mach-at91/include/mach/at91sam9g45.h
delete mode 100644 arch/arm/mach-at91/include/mach/at91sam9n12.h
delete mode 100644 arch/arm/mach-at91/include/mach/at91sam9rl.h
delete mode 100644 arch/arm/mach-at91/include/mach/at91sam9x5.h
delete mode 100644 arch/arm/mach-at91/include/mach/sama5d3.h
delete mode 100644 arch/arm/mach-at91/include/mach/sama5d4.h
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h
deleted file mode 100644
index e67317c67761..000000000000
--- a/arch/arm/mach-at91/include/mach/at91rm9200.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91rm9200.h
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- *
- * Common definitions.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91RM9200_H
-#define AT91RM9200_H
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define AT91RM9200_ID_PIOA 2 /* Parallel IO Controller A */
-#define AT91RM9200_ID_PIOB 3 /* Parallel IO Controller B */
-#define AT91RM9200_ID_PIOC 4 /* Parallel IO Controller C */
-#define AT91RM9200_ID_PIOD 5 /* Parallel IO Controller D */
-#define AT91RM9200_ID_US0 6 /* USART 0 */
-#define AT91RM9200_ID_US1 7 /* USART 1 */
-#define AT91RM9200_ID_US2 8 /* USART 2 */
-#define AT91RM9200_ID_US3 9 /* USART 3 */
-#define AT91RM9200_ID_MCI 10 /* Multimedia Card Interface */
-#define AT91RM9200_ID_UDP 11 /* USB Device Port */
-#define AT91RM9200_ID_TWI 12 /* Two-Wire Interface */
-#define AT91RM9200_ID_SPI 13 /* Serial Peripheral Interface */
-#define AT91RM9200_ID_SSC0 14 /* Serial Synchronous Controller 0 */
-#define AT91RM9200_ID_SSC1 15 /* Serial Synchronous Controller 1 */
-#define AT91RM9200_ID_SSC2 16 /* Serial Synchronous Controller 2 */
-#define AT91RM9200_ID_TC0 17 /* Timer Counter 0 */
-#define AT91RM9200_ID_TC1 18 /* Timer Counter 1 */
-#define AT91RM9200_ID_TC2 19 /* Timer Counter 2 */
-#define AT91RM9200_ID_TC3 20 /* Timer Counter 3 */
-#define AT91RM9200_ID_TC4 21 /* Timer Counter 4 */
-#define AT91RM9200_ID_TC5 22 /* Timer Counter 5 */
-#define AT91RM9200_ID_UHP 23 /* USB Host port */
-#define AT91RM9200_ID_EMAC 24 /* Ethernet MAC */
-#define AT91RM9200_ID_IRQ0 25 /* Advanced Interrupt Controller (IRQ0) */
-#define AT91RM9200_ID_IRQ1 26 /* Advanced Interrupt Controller (IRQ1) */
-#define AT91RM9200_ID_IRQ2 27 /* Advanced Interrupt Controller (IRQ2) */
-#define AT91RM9200_ID_IRQ3 28 /* Advanced Interrupt Controller (IRQ3) */
-#define AT91RM9200_ID_IRQ4 29 /* Advanced Interrupt Controller (IRQ4) */
-#define AT91RM9200_ID_IRQ5 30 /* Advanced Interrupt Controller (IRQ5) */
-#define AT91RM9200_ID_IRQ6 31 /* Advanced Interrupt Controller (IRQ6) */
-
-
-/*
- * Peripheral physical base addresses.
- */
-#define AT91RM9200_BASE_TCB0 0xfffa0000
-#define AT91RM9200_BASE_TC0 0xfffa0000
-#define AT91RM9200_BASE_TC1 0xfffa0040
-#define AT91RM9200_BASE_TC2 0xfffa0080
-#define AT91RM9200_BASE_TCB1 0xfffa4000
-#define AT91RM9200_BASE_TC3 0xfffa4000
-#define AT91RM9200_BASE_TC4 0xfffa4040
-#define AT91RM9200_BASE_TC5 0xfffa4080
-#define AT91RM9200_BASE_UDP 0xfffb0000
-#define AT91RM9200_BASE_MCI 0xfffb4000
-#define AT91RM9200_BASE_TWI 0xfffb8000
-#define AT91RM9200_BASE_EMAC 0xfffbc000
-#define AT91RM9200_BASE_US0 0xfffc0000
-#define AT91RM9200_BASE_US1 0xfffc4000
-#define AT91RM9200_BASE_US2 0xfffc8000
-#define AT91RM9200_BASE_US3 0xfffcc000
-#define AT91RM9200_BASE_SSC0 0xfffd0000
-#define AT91RM9200_BASE_SSC1 0xfffd4000
-#define AT91RM9200_BASE_SSC2 0xfffd8000
-#define AT91RM9200_BASE_SPI 0xfffe0000
-
-
-/*
- * System Peripherals
- */
-#define AT91RM9200_BASE_DBGU AT91_BASE_DBGU0 /* Debug Unit */
-#define AT91RM9200_BASE_PIOA 0xfffff400 /* PIO Controller A */
-#define AT91RM9200_BASE_PIOB 0xfffff600 /* PIO Controller B */
-#define AT91RM9200_BASE_PIOC 0xfffff800 /* PIO Controller C */
-#define AT91RM9200_BASE_PIOD 0xfffffa00 /* PIO Controller D */
-#define AT91RM9200_BASE_ST 0xfffffd00 /* System Timer */
-#define AT91RM9200_BASE_RTC 0xfffffe00 /* Real-Time Clock */
-#define AT91RM9200_BASE_MC 0xffffff00 /* Memory Controllers */
-
-/*
- * Internal Memory.
- */
-#define AT91RM9200_ROM_BASE 0x00100000 /* Internal ROM base address */
-#define AT91RM9200_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */
-
-#define AT91RM9200_SRAM_BASE 0x00200000 /* Internal SRAM base address */
-#define AT91RM9200_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */
-
-#define AT91RM9200_UHP_BASE 0x00300000 /* USB Host controller */
-
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
deleted file mode 100644
index 416c7b6c56d3..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9260.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91sam9260.h
- *
- * (C) 2006 Andrew Victor
- *
- * Common definitions.
- * Based on AT91SAM9260 datasheet revision A (Preliminary).
- *
- * Includes also definitions for AT91SAM9XE and AT91SAM9G families
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91SAM9260_H
-#define AT91SAM9260_H
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define AT91SAM9260_ID_PIOA 2 /* Parallel IO Controller A */
-#define AT91SAM9260_ID_PIOB 3 /* Parallel IO Controller B */
-#define AT91SAM9260_ID_PIOC 4 /* Parallel IO Controller C */
-#define AT91SAM9260_ID_ADC 5 /* Analog-to-Digital Converter */
-#define AT91SAM9260_ID_US0 6 /* USART 0 */
-#define AT91SAM9260_ID_US1 7 /* USART 1 */
-#define AT91SAM9260_ID_US2 8 /* USART 2 */
-#define AT91SAM9260_ID_MCI 9 /* Multimedia Card Interface */
-#define AT91SAM9260_ID_UDP 10 /* USB Device Port */
-#define AT91SAM9260_ID_TWI 11 /* Two-Wire Interface */
-#define AT91SAM9260_ID_SPI0 12 /* Serial Peripheral Interface 0 */
-#define AT91SAM9260_ID_SPI1 13 /* Serial Peripheral Interface 1 */
-#define AT91SAM9260_ID_SSC 14 /* Serial Synchronous Controller */
-#define AT91SAM9260_ID_TC0 17 /* Timer Counter 0 */
-#define AT91SAM9260_ID_TC1 18 /* Timer Counter 1 */
-#define AT91SAM9260_ID_TC2 19 /* Timer Counter 2 */
-#define AT91SAM9260_ID_UHP 20 /* USB Host port */
-#define AT91SAM9260_ID_EMAC 21 /* Ethernet */
-#define AT91SAM9260_ID_ISI 22 /* Image Sensor Interface */
-#define AT91SAM9260_ID_US3 23 /* USART 3 */
-#define AT91SAM9260_ID_US4 24 /* USART 4 */
-#define AT91SAM9260_ID_US5 25 /* USART 5 */
-#define AT91SAM9260_ID_TC3 26 /* Timer Counter 3 */
-#define AT91SAM9260_ID_TC4 27 /* Timer Counter 4 */
-#define AT91SAM9260_ID_TC5 28 /* Timer Counter 5 */
-#define AT91SAM9260_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */
-#define AT91SAM9260_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */
-#define AT91SAM9260_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */
-
-
-/*
- * User Peripheral physical base addresses.
- */
-#define AT91SAM9260_BASE_TCB0 0xfffa0000
-#define AT91SAM9260_BASE_TC0 0xfffa0000
-#define AT91SAM9260_BASE_TC1 0xfffa0040
-#define AT91SAM9260_BASE_TC2 0xfffa0080
-#define AT91SAM9260_BASE_UDP 0xfffa4000
-#define AT91SAM9260_BASE_MCI 0xfffa8000
-#define AT91SAM9260_BASE_TWI 0xfffac000
-#define AT91SAM9260_BASE_US0 0xfffb0000
-#define AT91SAM9260_BASE_US1 0xfffb4000
-#define AT91SAM9260_BASE_US2 0xfffb8000
-#define AT91SAM9260_BASE_SSC 0xfffbc000
-#define AT91SAM9260_BASE_ISI 0xfffc0000
-#define AT91SAM9260_BASE_EMAC 0xfffc4000
-#define AT91SAM9260_BASE_SPI0 0xfffc8000
-#define AT91SAM9260_BASE_SPI1 0xfffcc000
-#define AT91SAM9260_BASE_US3 0xfffd0000
-#define AT91SAM9260_BASE_US4 0xfffd4000
-#define AT91SAM9260_BASE_US5 0xfffd8000
-#define AT91SAM9260_BASE_TCB1 0xfffdc000
-#define AT91SAM9260_BASE_TC3 0xfffdc000
-#define AT91SAM9260_BASE_TC4 0xfffdc040
-#define AT91SAM9260_BASE_TC5 0xfffdc080
-#define AT91SAM9260_BASE_ADC 0xfffe0000
-
-/*
- * System Peripherals
- */
-#define AT91SAM9260_BASE_ECC 0xffffe800
-#define AT91SAM9260_BASE_SDRAMC 0xffffea00
-#define AT91SAM9260_BASE_SMC 0xffffec00
-#define AT91SAM9260_BASE_MATRIX 0xffffee00
-#define AT91SAM9260_BASE_DBGU AT91_BASE_DBGU0
-#define AT91SAM9260_BASE_PIOA 0xfffff400
-#define AT91SAM9260_BASE_PIOB 0xfffff600
-#define AT91SAM9260_BASE_PIOC 0xfffff800
-#define AT91SAM9260_BASE_RSTC 0xfffffd00
-#define AT91SAM9260_BASE_SHDWC 0xfffffd10
-#define AT91SAM9260_BASE_RTT 0xfffffd20
-#define AT91SAM9260_BASE_PIT 0xfffffd30
-#define AT91SAM9260_BASE_WDT 0xfffffd40
-#define AT91SAM9260_BASE_GPBR 0xfffffd50
-
-
-/*
- * Internal Memory.
- */
-#define AT91SAM9260_ROM_BASE 0x00100000 /* Internal ROM base address */
-#define AT91SAM9260_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
-
-#define AT91SAM9260_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */
-#define AT91SAM9260_SRAM0_SIZE SZ_4K /* Internal SRAM 0 size (4Kb) */
-#define AT91SAM9260_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */
-#define AT91SAM9260_SRAM1_SIZE SZ_4K /* Internal SRAM 1 size (4Kb) */
-#define AT91SAM9260_SRAM_BASE 0x002FF000 /* Internal SRAM base address */
-#define AT91SAM9260_SRAM_SIZE SZ_8K /* Internal SRAM size (8Kb) */
-
-#define AT91SAM9260_UHP_BASE 0x00500000 /* USB Host controller */
-
-#define AT91SAM9XE_FLASH_BASE 0x00200000 /* Internal FLASH base address */
-#define AT91SAM9XE_SRAM_BASE 0x00300000 /* Internal SRAM base address */
-
-#define AT91SAM9G20_ROM_BASE 0x00100000 /* Internal ROM base address */
-#define AT91SAM9G20_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
-
-#define AT91SAM9G20_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */
-#define AT91SAM9G20_SRAM0_SIZE SZ_16K /* Internal SRAM 0 size (16Kb) */
-#define AT91SAM9G20_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */
-#define AT91SAM9G20_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */
-#define AT91SAM9G20_SRAM_BASE 0x002FC000 /* Internal SRAM base address */
-#define AT91SAM9G20_SRAM_SIZE SZ_32K /* Internal SRAM size (32Kb) */
-
-#define AT91SAM9G20_UHP_BASE 0x00500000 /* USB Host controller */
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
deleted file mode 100644
index a041406d06ee..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9261.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91sam9261.h
- *
- * Copyright (C) SAN People
- *
- * Common definitions.
- * Based on AT91SAM9261 datasheet revision E. (Preliminary)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91SAM9261_H
-#define AT91SAM9261_H
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define AT91SAM9261_ID_PIOA 2 /* Parallel IO Controller A */
-#define AT91SAM9261_ID_PIOB 3 /* Parallel IO Controller B */
-#define AT91SAM9261_ID_PIOC 4 /* Parallel IO Controller C */
-#define AT91SAM9261_ID_US0 6 /* USART 0 */
-#define AT91SAM9261_ID_US1 7 /* USART 1 */
-#define AT91SAM9261_ID_US2 8 /* USART 2 */
-#define AT91SAM9261_ID_MCI 9 /* Multimedia Card Interface */
-#define AT91SAM9261_ID_UDP 10 /* USB Device Port */
-#define AT91SAM9261_ID_TWI 11 /* Two-Wire Interface */
-#define AT91SAM9261_ID_SPI0 12 /* Serial Peripheral Interface 0 */
-#define AT91SAM9261_ID_SPI1 13 /* Serial Peripheral Interface 1 */
-#define AT91SAM9261_ID_SSC0 14 /* Serial Synchronous Controller 0 */
-#define AT91SAM9261_ID_SSC1 15 /* Serial Synchronous Controller 1 */
-#define AT91SAM9261_ID_SSC2 16 /* Serial Synchronous Controller 2 */
-#define AT91SAM9261_ID_TC0 17 /* Timer Counter 0 */
-#define AT91SAM9261_ID_TC1 18 /* Timer Counter 1 */
-#define AT91SAM9261_ID_TC2 19 /* Timer Counter 2 */
-#define AT91SAM9261_ID_UHP 20 /* USB Host port */
-#define AT91SAM9261_ID_LCDC 21 /* LDC Controller */
-#define AT91SAM9261_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */
-#define AT91SAM9261_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */
-#define AT91SAM9261_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */
-
-
-/*
- * User Peripheral physical base addresses.
- */
-#define AT91SAM9261_BASE_TCB0 0xfffa0000
-#define AT91SAM9261_BASE_TC0 0xfffa0000
-#define AT91SAM9261_BASE_TC1 0xfffa0040
-#define AT91SAM9261_BASE_TC2 0xfffa0080
-#define AT91SAM9261_BASE_UDP 0xfffa4000
-#define AT91SAM9261_BASE_MCI 0xfffa8000
-#define AT91SAM9261_BASE_TWI 0xfffac000
-#define AT91SAM9261_BASE_US0 0xfffb0000
-#define AT91SAM9261_BASE_US1 0xfffb4000
-#define AT91SAM9261_BASE_US2 0xfffb8000
-#define AT91SAM9261_BASE_SSC0 0xfffbc000
-#define AT91SAM9261_BASE_SSC1 0xfffc0000
-#define AT91SAM9261_BASE_SSC2 0xfffc4000
-#define AT91SAM9261_BASE_SPI0 0xfffc8000
-#define AT91SAM9261_BASE_SPI1 0xfffcc000
-
-
-/*
- * System Peripherals
- */
-#define AT91SAM9261_BASE_SMC 0xffffec00
-#define AT91SAM9261_BASE_MATRIX 0xffffee00
-#define AT91SAM9261_BASE_SDRAMC 0xffffea00
-#define AT91SAM9261_BASE_DBGU AT91_BASE_DBGU0
-#define AT91SAM9261_BASE_PIOA 0xfffff400
-#define AT91SAM9261_BASE_PIOB 0xfffff600
-#define AT91SAM9261_BASE_PIOC 0xfffff800
-#define AT91SAM9261_BASE_RSTC 0xfffffd00
-#define AT91SAM9261_BASE_SHDWC 0xfffffd10
-#define AT91SAM9261_BASE_RTT 0xfffffd20
-#define AT91SAM9261_BASE_PIT 0xfffffd30
-#define AT91SAM9261_BASE_WDT 0xfffffd40
-#define AT91SAM9261_BASE_GPBR 0xfffffd50
-
-
-/*
- * Internal Memory.
- */
-#define AT91SAM9261_SRAM_BASE 0x00300000 /* Internal SRAM base address */
-#define AT91SAM9261_SRAM_SIZE 0x00028000 /* Internal SRAM size (160Kb) */
-
-#define AT91SAM9G10_SRAM_BASE AT91SAM9261_SRAM_BASE /* Internal SRAM base address */
-#define AT91SAM9G10_SRAM_SIZE 0x00004000 /* Internal SRAM size (16Kb) */
-
-#define AT91SAM9261_ROM_BASE 0x00400000 /* Internal ROM base address */
-#define AT91SAM9261_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
-
-#define AT91SAM9261_UHP_BASE 0x00500000 /* USB Host controller */
-#define AT91SAM9261_LCDC_BASE 0x00600000 /* LDC controller */
-
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h
deleted file mode 100644
index d201029d60b3..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9263.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91sam9263.h
- *
- * (C) 2007 Atmel Corporation.
- *
- * Common definitions.
- * Based on AT91SAM9263 datasheet revision B (Preliminary).
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91SAM9263_H
-#define AT91SAM9263_H
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define AT91SAM9263_ID_PIOA 2 /* Parallel IO Controller A */
-#define AT91SAM9263_ID_PIOB 3 /* Parallel IO Controller B */
-#define AT91SAM9263_ID_PIOCDE 4 /* Parallel IO Controller C, D and E */
-#define AT91SAM9263_ID_US0 7 /* USART 0 */
-#define AT91SAM9263_ID_US1 8 /* USART 1 */
-#define AT91SAM9263_ID_US2 9 /* USART 2 */
-#define AT91SAM9263_ID_MCI0 10 /* Multimedia Card Interface 0 */
-#define AT91SAM9263_ID_MCI1 11 /* Multimedia Card Interface 1 */
-#define AT91SAM9263_ID_CAN 12 /* CAN */
-#define AT91SAM9263_ID_TWI 13 /* Two-Wire Interface */
-#define AT91SAM9263_ID_SPI0 14 /* Serial Peripheral Interface 0 */
-#define AT91SAM9263_ID_SPI1 15 /* Serial Peripheral Interface 1 */
-#define AT91SAM9263_ID_SSC0 16 /* Serial Synchronous Controller 0 */
-#define AT91SAM9263_ID_SSC1 17 /* Serial Synchronous Controller 1 */
-#define AT91SAM9263_ID_AC97C 18 /* AC97 Controller */
-#define AT91SAM9263_ID_TCB 19 /* Timer Counter 0, 1 and 2 */
-#define AT91SAM9263_ID_PWMC 20 /* Pulse Width Modulation Controller */
-#define AT91SAM9263_ID_EMAC 21 /* Ethernet */
-#define AT91SAM9263_ID_2DGE 23 /* 2D Graphic Engine */
-#define AT91SAM9263_ID_UDP 24 /* USB Device Port */
-#define AT91SAM9263_ID_ISI 25 /* Image Sensor Interface */
-#define AT91SAM9263_ID_LCDC 26 /* LCD Controller */
-#define AT91SAM9263_ID_DMA 27 /* DMA Controller */
-#define AT91SAM9263_ID_UHP 29 /* USB Host port */
-#define AT91SAM9263_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */
-#define AT91SAM9263_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */
-
-
-/*
- * User Peripheral physical base addresses.
- */
-#define AT91SAM9263_BASE_UDP 0xfff78000
-#define AT91SAM9263_BASE_TCB0 0xfff7c000
-#define AT91SAM9263_BASE_TC0 0xfff7c000
-#define AT91SAM9263_BASE_TC1 0xfff7c040
-#define AT91SAM9263_BASE_TC2 0xfff7c080
-#define AT91SAM9263_BASE_MCI0 0xfff80000
-#define AT91SAM9263_BASE_MCI1 0xfff84000
-#define AT91SAM9263_BASE_TWI 0xfff88000
-#define AT91SAM9263_BASE_US0 0xfff8c000
-#define AT91SAM9263_BASE_US1 0xfff90000
-#define AT91SAM9263_BASE_US2 0xfff94000
-#define AT91SAM9263_BASE_SSC0 0xfff98000
-#define AT91SAM9263_BASE_SSC1 0xfff9c000
-#define AT91SAM9263_BASE_AC97C 0xfffa0000
-#define AT91SAM9263_BASE_SPI0 0xfffa4000
-#define AT91SAM9263_BASE_SPI1 0xfffa8000
-#define AT91SAM9263_BASE_CAN 0xfffac000
-#define AT91SAM9263_BASE_PWMC 0xfffb8000
-#define AT91SAM9263_BASE_EMAC 0xfffbc000
-#define AT91SAM9263_BASE_ISI 0xfffc4000
-#define AT91SAM9263_BASE_2DGE 0xfffc8000
-
-/*
- * System Peripherals
- */
-#define AT91SAM9263_BASE_ECC0 0xffffe000
-#define AT91SAM9263_BASE_SDRAMC0 0xffffe200
-#define AT91SAM9263_BASE_SMC0 0xffffe400
-#define AT91SAM9263_BASE_ECC1 0xffffe600
-#define AT91SAM9263_BASE_SDRAMC1 0xffffe800
-#define AT91SAM9263_BASE_SMC1 0xffffea00
-#define AT91SAM9263_BASE_MATRIX 0xffffec00
-#define AT91SAM9263_BASE_DBGU AT91_BASE_DBGU1
-#define AT91SAM9263_BASE_PIOA 0xfffff200
-#define AT91SAM9263_BASE_PIOB 0xfffff400
-#define AT91SAM9263_BASE_PIOC 0xfffff600
-#define AT91SAM9263_BASE_PIOD 0xfffff800
-#define AT91SAM9263_BASE_PIOE 0xfffffa00
-#define AT91SAM9263_BASE_RSTC 0xfffffd00
-#define AT91SAM9263_BASE_SHDWC 0xfffffd10
-#define AT91SAM9263_BASE_RTT0 0xfffffd20
-#define AT91SAM9263_BASE_PIT 0xfffffd30
-#define AT91SAM9263_BASE_WDT 0xfffffd40
-#define AT91SAM9263_BASE_RTT1 0xfffffd50
-#define AT91SAM9263_BASE_GPBR 0xfffffd60
-
-#define AT91_SMC AT91_SMC0
-
-/*
- * Internal Memory.
- */
-#define AT91SAM9263_SRAM0_BASE 0x00300000 /* Internal SRAM 0 base address */
-#define AT91SAM9263_SRAM0_SIZE (80 * SZ_1K) /* Internal SRAM 0 size (80Kb) */
-
-#define AT91SAM9263_ROM_BASE 0x00400000 /* Internal ROM base address */
-#define AT91SAM9263_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */
-
-#define AT91SAM9263_SRAM1_BASE 0x00500000 /* Internal SRAM 1 base address */
-#define AT91SAM9263_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */
-
-#define AT91SAM9263_LCDC_BASE 0x00700000 /* LCD Controller */
-#define AT91SAM9263_DMAC_BASE 0x00800000 /* DMA Controller */
-#define AT91SAM9263_UHP_BASE 0x00a00000 /* USB Host controller */
-
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
deleted file mode 100644
index 8eba1021f533..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * Chip-specific header file for the AT91SAM9G45 family
- *
- * Copyright (C) 2008-2009 Atmel Corporation.
- *
- * Common definitions.
- * Based on AT91SAM9G45 preliminary datasheet.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91SAM9G45_H
-#define AT91SAM9G45_H
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define AT91SAM9G45_ID_PIOA 2 /* Parallel I/O Controller A */
-#define AT91SAM9G45_ID_PIOB 3 /* Parallel I/O Controller B */
-#define AT91SAM9G45_ID_PIOC 4 /* Parallel I/O Controller C */
-#define AT91SAM9G45_ID_PIODE 5 /* Parallel I/O Controller D and E */
-#define AT91SAM9G45_ID_TRNG 6 /* True Random Number Generator */
-#define AT91SAM9G45_ID_US0 7 /* USART 0 */
-#define AT91SAM9G45_ID_US1 8 /* USART 1 */
-#define AT91SAM9G45_ID_US2 9 /* USART 2 */
-#define AT91SAM9G45_ID_US3 10 /* USART 3 */
-#define AT91SAM9G45_ID_MCI0 11 /* High Speed Multimedia Card Interface 0 */
-#define AT91SAM9G45_ID_TWI0 12 /* Two-Wire Interface 0 */
-#define AT91SAM9G45_ID_TWI1 13 /* Two-Wire Interface 1 */
-#define AT91SAM9G45_ID_SPI0 14 /* Serial Peripheral Interface 0 */
-#define AT91SAM9G45_ID_SPI1 15 /* Serial Peripheral Interface 1 */
-#define AT91SAM9G45_ID_SSC0 16 /* Synchronous Serial Controller 0 */
-#define AT91SAM9G45_ID_SSC1 17 /* Synchronous Serial Controller 1 */
-#define AT91SAM9G45_ID_TCB 18 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
-#define AT91SAM9G45_ID_PWMC 19 /* Pulse Width Modulation Controller */
-#define AT91SAM9G45_ID_TSC 20 /* Touch Screen ADC Controller */
-#define AT91SAM9G45_ID_DMA 21 /* DMA Controller */
-#define AT91SAM9G45_ID_UHPHS 22 /* USB Host High Speed */
-#define AT91SAM9G45_ID_LCDC 23 /* LCD Controller */
-#define AT91SAM9G45_ID_AC97C 24 /* AC97 Controller */
-#define AT91SAM9G45_ID_EMAC 25 /* Ethernet MAC */
-#define AT91SAM9G45_ID_ISI 26 /* Image Sensor Interface */
-#define AT91SAM9G45_ID_UDPHS 27 /* USB Device High Speed */
-#define AT91SAM9G45_ID_AESTDESSHA 28 /* AES + T-DES + SHA */
-#define AT91SAM9G45_ID_MCI1 29 /* High Speed Multimedia Card Interface 1 */
-#define AT91SAM9G45_ID_VDEC 30 /* Video Decoder */
-#define AT91SAM9G45_ID_IRQ0 31 /* Advanced Interrupt Controller */
-
-/*
- * User Peripheral physical base addresses.
- */
-#define AT91SAM9G45_BASE_UDPHS 0xfff78000
-#define AT91SAM9G45_BASE_TCB0 0xfff7c000
-#define AT91SAM9G45_BASE_TC0 0xfff7c000
-#define AT91SAM9G45_BASE_TC1 0xfff7c040
-#define AT91SAM9G45_BASE_TC2 0xfff7c080
-#define AT91SAM9G45_BASE_MCI0 0xfff80000
-#define AT91SAM9G45_BASE_TWI0 0xfff84000
-#define AT91SAM9G45_BASE_TWI1 0xfff88000
-#define AT91SAM9G45_BASE_US0 0xfff8c000
-#define AT91SAM9G45_BASE_US1 0xfff90000
-#define AT91SAM9G45_BASE_US2 0xfff94000
-#define AT91SAM9G45_BASE_US3 0xfff98000
-#define AT91SAM9G45_BASE_SSC0 0xfff9c000
-#define AT91SAM9G45_BASE_SSC1 0xfffa0000
-#define AT91SAM9G45_BASE_SPI0 0xfffa4000
-#define AT91SAM9G45_BASE_SPI1 0xfffa8000
-#define AT91SAM9G45_BASE_AC97C 0xfffac000
-#define AT91SAM9G45_BASE_TSC 0xfffb0000
-#define AT91SAM9G45_BASE_ISI 0xfffb4000
-#define AT91SAM9G45_BASE_PWMC 0xfffb8000
-#define AT91SAM9G45_BASE_EMAC 0xfffbc000
-#define AT91SAM9G45_BASE_AES 0xfffc0000
-#define AT91SAM9G45_BASE_TDES 0xfffc4000
-#define AT91SAM9G45_BASE_SHA 0xfffc8000
-#define AT91SAM9G45_BASE_TRNG 0xfffcc000
-#define AT91SAM9G45_BASE_MCI1 0xfffd0000
-#define AT91SAM9G45_BASE_TCB1 0xfffd4000
-#define AT91SAM9G45_BASE_TC3 0xfffd4000
-#define AT91SAM9G45_BASE_TC4 0xfffd4040
-#define AT91SAM9G45_BASE_TC5 0xfffd4080
-
-/*
- * System Peripherals
- */
-#define AT91SAM9G45_BASE_ECC 0xffffe200
-#define AT91SAM9G45_BASE_DDRSDRC1 0xffffe400
-#define AT91SAM9G45_BASE_DDRSDRC0 0xffffe600
-#define AT91SAM9G45_BASE_DMA 0xffffec00
-#define AT91SAM9G45_BASE_SMC 0xffffe800
-#define AT91SAM9G45_BASE_MATRIX 0xffffea00
-#define AT91SAM9G45_BASE_DBGU AT91_BASE_DBGU1
-#define AT91SAM9G45_BASE_PIOA 0xfffff200
-#define AT91SAM9G45_BASE_PIOB 0xfffff400
-#define AT91SAM9G45_BASE_PIOC 0xfffff600
-#define AT91SAM9G45_BASE_PIOD 0xfffff800
-#define AT91SAM9G45_BASE_PIOE 0xfffffa00
-#define AT91SAM9G45_BASE_RSTC 0xfffffd00
-#define AT91SAM9G45_BASE_SHDWC 0xfffffd10
-#define AT91SAM9G45_BASE_RTT 0xfffffd20
-#define AT91SAM9G45_BASE_PIT 0xfffffd30
-#define AT91SAM9G45_BASE_WDT 0xfffffd40
-#define AT91SAM9G45_BASE_RTC 0xfffffdb0
-#define AT91SAM9G45_BASE_GPBR 0xfffffd60
-
-/*
- * Internal Memory.
- */
-#define AT91SAM9G45_SRAM_BASE 0x00300000 /* Internal SRAM base address */
-#define AT91SAM9G45_SRAM_SIZE SZ_64K /* Internal SRAM size (64Kb) */
-
-#define AT91SAM9G45_ROM_BASE 0x00400000 /* Internal ROM base address */
-#define AT91SAM9G45_ROM_SIZE SZ_64K /* Internal ROM size (64Kb) */
-
-#define AT91SAM9G45_LCDC_BASE 0x00500000 /* LCD Controller */
-#define AT91SAM9G45_UDPHS_FIFO 0x00600000 /* USB Device HS controller */
-#define AT91SAM9G45_OHCI_BASE 0x00700000 /* USB Host controller (OHCI) */
-#define AT91SAM9G45_EHCI_BASE 0x00800000 /* USB Host controller (EHCI) */
-#define AT91SAM9G45_VDEC_BASE 0x00900000 /* Video Decoder Controller */
-
-/*
- * DMA peripheral identifiers
- * for hardware handshaking interface
- */
-#define AT_DMA_ID_MCI0 0
-#define AT_DMA_ID_SPI0_TX 1
-#define AT_DMA_ID_SPI0_RX 2
-#define AT_DMA_ID_SPI1_TX 3
-#define AT_DMA_ID_SPI1_RX 4
-#define AT_DMA_ID_SSC0_TX 5
-#define AT_DMA_ID_SSC0_RX 6
-#define AT_DMA_ID_SSC1_TX 7
-#define AT_DMA_ID_SSC1_RX 8
-#define AT_DMA_ID_AC97_TX 9
-#define AT_DMA_ID_AC97_RX 10
-#define AT_DMA_ID_AES_TX 11
-#define AT_DMA_ID_AES_RX 12
-#define AT_DMA_ID_MCI1 13
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12.h b/arch/arm/mach-at91/include/mach/at91sam9n12.h
deleted file mode 100644
index 0151bcf6163c..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9n12.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * SoC specific header file for the AT91SAM9N12
- *
- * Copyright (C) 2012 Atmel Corporation
- *
- * Common definitions, based on AT91SAM9N12 SoC datasheet
- *
- * Licensed under GPLv2 or later
- */
-
-#ifndef _AT91SAM9N12_H_
-#define _AT91SAM9N12_H_
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define AT91SAM9N12_ID_PIOAB 2 /* Parallel I/O Controller A and B */
-#define AT91SAM9N12_ID_PIOCD 3 /* Parallel I/O Controller C and D */
-#define AT91SAM9N12_ID_FUSE 4 /* FUSE Controller */
-#define AT91SAM9N12_ID_USART0 5 /* USART 0 */
-#define AT91SAM9N12_ID_USART1 6 /* USART 1 */
-#define AT91SAM9N12_ID_USART2 7 /* USART 2 */
-#define AT91SAM9N12_ID_USART3 8 /* USART 3 */
-#define AT91SAM9N12_ID_TWI0 9 /* Two-Wire Interface 0 */
-#define AT91SAM9N12_ID_TWI1 10 /* Two-Wire Interface 1 */
-#define AT91SAM9N12_ID_MCI 12 /* High Speed Multimedia Card Interface */
-#define AT91SAM9N12_ID_SPI0 13 /* Serial Peripheral Interface 0 */
-#define AT91SAM9N12_ID_SPI1 14 /* Serial Peripheral Interface 1 */
-#define AT91SAM9N12_ID_UART0 15 /* UART 0 */
-#define AT91SAM9N12_ID_UART1 16 /* UART 1 */
-#define AT91SAM9N12_ID_TCB 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
-#define AT91SAM9N12_ID_PWM 18 /* Pulse Width Modulation Controller */
-#define AT91SAM9N12_ID_ADC 19 /* ADC Controller */
-#define AT91SAM9N12_ID_DMA 20 /* DMA Controller */
-#define AT91SAM9N12_ID_UHP 22 /* USB Host High Speed */
-#define AT91SAM9N12_ID_UDP 23 /* USB Device High Speed */
-#define AT91SAM9N12_ID_LCDC 25 /* LCD Controller */
-#define AT91SAM9N12_ID_ISI 25 /* Image Sensor Interface */
-#define AT91SAM9N12_ID_SSC 28 /* Synchronous Serial Controller */
-#define AT91SAM9N12_ID_TRNG 30 /* TRNG */
-#define AT91SAM9N12_ID_IRQ0 31 /* Advanced Interrupt Controller */
-
-/*
- * User Peripheral physical base addresses.
- */
-#define AT91SAM9N12_BASE_USART0 0xf801c000
-#define AT91SAM9N12_BASE_USART1 0xf8020000
-#define AT91SAM9N12_BASE_USART2 0xf8024000
-#define AT91SAM9N12_BASE_USART3 0xf8028000
-
-/*
- * System Peripherals
- */
-#define AT91SAM9N12_BASE_RTC 0xfffffeb0
-
-/*
- * Internal Memory.
- */
-#define AT91SAM9N12_SRAM_BASE 0x00300000 /* Internal SRAM base address */
-#define AT91SAM9N12_SRAM_SIZE SZ_32K /* Internal SRAM size (32Kb) */
-
-#define AT91SAM9N12_ROM_BASE 0x00100000 /* Internal ROM base address */
-#define AT91SAM9N12_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h
deleted file mode 100644
index a15db56d33fa..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9rl.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91sam9260.h
- *
- * Copyright (C) 2007 Atmel Corporation
- *
- * Common definitions.
- * Based on AT91SAM9RL datasheet revision A. (Preliminary)
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file COPYING in the main directory of this archive for
- * more details.
- */
-
-#ifndef AT91SAM9RL_H
-#define AT91SAM9RL_H
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define AT91SAM9RL_ID_PIOA 2 /* Parallel IO Controller A */
-#define AT91SAM9RL_ID_PIOB 3 /* Parallel IO Controller B */
-#define AT91SAM9RL_ID_PIOC 4 /* Parallel IO Controller C */
-#define AT91SAM9RL_ID_PIOD 5 /* Parallel IO Controller D */
-#define AT91SAM9RL_ID_US0 6 /* USART 0 */
-#define AT91SAM9RL_ID_US1 7 /* USART 1 */
-#define AT91SAM9RL_ID_US2 8 /* USART 2 */
-#define AT91SAM9RL_ID_US3 9 /* USART 3 */
-#define AT91SAM9RL_ID_MCI 10 /* Multimedia Card Interface */
-#define AT91SAM9RL_ID_TWI0 11 /* TWI 0 */
-#define AT91SAM9RL_ID_TWI1 12 /* TWI 1 */
-#define AT91SAM9RL_ID_SPI 13 /* Serial Peripheral Interface */
-#define AT91SAM9RL_ID_SSC0 14 /* Serial Synchronous Controller 0 */
-#define AT91SAM9RL_ID_SSC1 15 /* Serial Synchronous Controller 1 */
-#define AT91SAM9RL_ID_TC0 16 /* Timer Counter 0 */
-#define AT91SAM9RL_ID_TC1 17 /* Timer Counter 1 */
-#define AT91SAM9RL_ID_TC2 18 /* Timer Counter 2 */
-#define AT91SAM9RL_ID_PWMC 19 /* Pulse Width Modulation Controller */
-#define AT91SAM9RL_ID_TSC 20 /* Touch Screen Controller */
-#define AT91SAM9RL_ID_DMA 21 /* DMA Controller */
-#define AT91SAM9RL_ID_UDPHS 22 /* USB Device HS */
-#define AT91SAM9RL_ID_LCDC 23 /* LCD Controller */
-#define AT91SAM9RL_ID_AC97C 24 /* AC97 Controller */
-#define AT91SAM9RL_ID_IRQ0 31 /* Advanced Interrupt Controller (IRQ0) */
-
-
-/*
- * User Peripheral physical base addresses.
- */
-#define AT91SAM9RL_BASE_TCB0 0xfffa0000
-#define AT91SAM9RL_BASE_TC0 0xfffa0000
-#define AT91SAM9RL_BASE_TC1 0xfffa0040
-#define AT91SAM9RL_BASE_TC2 0xfffa0080
-#define AT91SAM9RL_BASE_MCI 0xfffa4000
-#define AT91SAM9RL_BASE_TWI0 0xfffa8000
-#define AT91SAM9RL_BASE_TWI1 0xfffac000
-#define AT91SAM9RL_BASE_US0 0xfffb0000
-#define AT91SAM9RL_BASE_US1 0xfffb4000
-#define AT91SAM9RL_BASE_US2 0xfffb8000
-#define AT91SAM9RL_BASE_US3 0xfffbc000
-#define AT91SAM9RL_BASE_SSC0 0xfffc0000
-#define AT91SAM9RL_BASE_SSC1 0xfffc4000
-#define AT91SAM9RL_BASE_PWMC 0xfffc8000
-#define AT91SAM9RL_BASE_SPI 0xfffcc000
-#define AT91SAM9RL_BASE_TSC 0xfffd0000
-#define AT91SAM9RL_BASE_UDPHS 0xfffd4000
-#define AT91SAM9RL_BASE_AC97C 0xfffd8000
-
-
-/*
- * System Peripherals (offset from AT91_BASE_SYS)
- */
-#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS)
-
-#define AT91SAM9RL_BASE_DMA 0xffffe600
-#define AT91SAM9RL_BASE_ECC 0xffffe800
-#define AT91SAM9RL_BASE_SDRAMC 0xffffea00
-#define AT91SAM9RL_BASE_SMC 0xffffec00
-#define AT91SAM9RL_BASE_MATRIX 0xffffee00
-#define AT91SAM9RL_BASE_DBGU AT91_BASE_DBGU0
-#define AT91SAM9RL_BASE_PIOA 0xfffff400
-#define AT91SAM9RL_BASE_PIOB 0xfffff600
-#define AT91SAM9RL_BASE_PIOC 0xfffff800
-#define AT91SAM9RL_BASE_PIOD 0xfffffa00
-#define AT91SAM9RL_BASE_RSTC 0xfffffd00
-#define AT91SAM9RL_BASE_SHDWC 0xfffffd10
-#define AT91SAM9RL_BASE_RTT 0xfffffd20
-#define AT91SAM9RL_BASE_PIT 0xfffffd30
-#define AT91SAM9RL_BASE_WDT 0xfffffd40
-#define AT91SAM9RL_BASE_GPBR 0xfffffd60
-#define AT91SAM9RL_BASE_RTC 0xfffffe00
-
-
-/*
- * Internal Memory.
- */
-#define AT91SAM9RL_SRAM_BASE 0x00300000 /* Internal SRAM base address */
-#define AT91SAM9RL_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */
-
-#define AT91SAM9RL_ROM_BASE 0x00400000 /* Internal ROM base address */
-#define AT91SAM9RL_ROM_SIZE (2 * SZ_16K) /* Internal ROM size (32Kb) */
-
-#define AT91SAM9RL_LCDC_BASE 0x00500000 /* LCD Controller */
-#define AT91SAM9RL_UDPHS_FIFO 0x00600000 /* USB Device HS controller */
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
deleted file mode 100644
index 2fc76c49e97c..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Chip-specific header file for the AT91SAM9x5 family
- *
- * Copyright (C) 2009-2012 Atmel Corporation.
- *
- * Common definitions.
- * Based on AT91SAM9x5 datasheet.
- *
- * Licensed under GPLv2 or later.
- */
-
-#ifndef AT91SAM9X5_H
-#define AT91SAM9X5_H
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define AT91SAM9X5_ID_PIOAB 2 /* Parallel I/O Controller A and B */
-#define AT91SAM9X5_ID_PIOCD 3 /* Parallel I/O Controller C and D */
-#define AT91SAM9X5_ID_SMD 4 /* SMD Soft Modem (SMD) */
-#define AT91SAM9X5_ID_USART0 5 /* USART 0 */
-#define AT91SAM9X5_ID_USART1 6 /* USART 1 */
-#define AT91SAM9X5_ID_USART2 7 /* USART 2 */
-#define AT91SAM9X5_ID_USART3 8 /* USART 3 */
-#define AT91SAM9X5_ID_TWI0 9 /* Two-Wire Interface 0 */
-#define AT91SAM9X5_ID_TWI1 10 /* Two-Wire Interface 1 */
-#define AT91SAM9X5_ID_TWI2 11 /* Two-Wire Interface 2 */
-#define AT91SAM9X5_ID_MCI0 12 /* High Speed Multimedia Card Interface 0 */
-#define AT91SAM9X5_ID_SPI0 13 /* Serial Peripheral Interface 0 */
-#define AT91SAM9X5_ID_SPI1 14 /* Serial Peripheral Interface 1 */
-#define AT91SAM9X5_ID_UART0 15 /* UART 0 */
-#define AT91SAM9X5_ID_UART1 16 /* UART 1 */
-#define AT91SAM9X5_ID_TCB 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
-#define AT91SAM9X5_ID_PWM 18 /* Pulse Width Modulation Controller */
-#define AT91SAM9X5_ID_ADC 19 /* ADC Controller */
-#define AT91SAM9X5_ID_DMA0 20 /* DMA Controller 0 */
-#define AT91SAM9X5_ID_DMA1 21 /* DMA Controller 1 */
-#define AT91SAM9X5_ID_UHPHS 22 /* USB Host High Speed */
-#define AT91SAM9X5_ID_UDPHS 23 /* USB Device High Speed */
-#define AT91SAM9X5_ID_EMAC0 24 /* Ethernet MAC0 */
-#define AT91SAM9X5_ID_LCDC 25 /* LCD Controller */
-#define AT91SAM9X5_ID_ISI 25 /* Image Sensor Interface */
-#define AT91SAM9X5_ID_MCI1 26 /* High Speed Multimedia Card Interface 1 */
-#define AT91SAM9X5_ID_EMAC1 27 /* Ethernet MAC1 */
-#define AT91SAM9X5_ID_SSC 28 /* Synchronous Serial Controller */
-#define AT91SAM9X5_ID_CAN0 29 /* CAN Controller 0 */
-#define AT91SAM9X5_ID_CAN1 30 /* CAN Controller 1 */
-#define AT91SAM9X5_ID_IRQ0 31 /* Advanced Interrupt Controller */
-
-/*
- * User Peripheral physical base addresses.
- */
-#define AT91SAM9X5_BASE_USART0 0xf801c000
-#define AT91SAM9X5_BASE_USART1 0xf8020000
-#define AT91SAM9X5_BASE_USART2 0xf8024000
-
-/*
- * System Peripherals
- */
-#define AT91SAM9X5_BASE_RTC 0xfffffeb0
-
-/*
- * Internal Memory.
- */
-#define AT91SAM9X5_SRAM_BASE 0x00300000 /* Internal SRAM base address */
-#define AT91SAM9X5_SRAM_SIZE SZ_32K /* Internal SRAM size (32Kb) */
-
-#define AT91SAM9X5_ROM_BASE 0x00400000 /* Internal ROM base address */
-#define AT91SAM9X5_ROM_SIZE SZ_64K /* Internal ROM size (64Kb) */
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index cacbaa52418f..2f8ce2d69fdb 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -24,17 +24,6 @@
/* sama5d4 */
#define AT91_BASE_DBGU2 0xfc069000
-#include <mach/at91rm9200.h>
-#include <mach/at91sam9260.h>
-#include <mach/at91sam9261.h>
-#include <mach/at91sam9263.h>
-#include <mach/at91sam9rl.h>
-#include <mach/at91sam9g45.h>
-#include <mach/at91sam9x5.h>
-#include <mach/at91sam9n12.h>
-#include <mach/sama5d3.h>
-#include <mach/sama5d4.h>
-
/*
* On all at91 except rm9200 and x40 have the System Controller starts
* at address 0xffffc000 and has a size of 16KiB.
diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h
deleted file mode 100644
index 25613d8c6dcd..000000000000
--- a/arch/arm/mach-at91/include/mach/sama5d3.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * Chip-specific header file for the SAMA5D3 family
- *
- * Copyright (C) 2013 Atmel,
- * 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
- *
- * Common definitions.
- * Based on SAMA5D3 datasheet.
- *
- * Licensed under GPLv2 or later.
- */
-
-#ifndef SAMA5D3_H
-#define SAMA5D3_H
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS 1 /* System Peripherals */
-#define SAMA5D3_ID_DBGU 2 /* debug Unit (usually no special interrupt line) */
-#define AT91_ID_PIT 3 /* PIT */
-#define SAMA5D3_ID_WDT 4 /* Watchdog Timer Interrupt */
-#define SAMA5D3_ID_HSMC 5 /* Static Memory Controller */
-#define SAMA5D3_ID_PIOA 6 /* PIOA */
-#define SAMA5D3_ID_PIOB 7 /* PIOB */
-#define SAMA5D3_ID_PIOC 8 /* PIOC */
-#define SAMA5D3_ID_PIOD 9 /* PIOD */
-#define SAMA5D3_ID_PIOE 10 /* PIOE */
-#define SAMA5D3_ID_SMD 11 /* SMD Soft Modem */
-#define SAMA5D3_ID_USART0 12 /* USART0 */
-#define SAMA5D3_ID_USART1 13 /* USART1 */
-#define SAMA5D3_ID_USART2 14 /* USART2 */
-#define SAMA5D3_ID_USART3 15 /* USART3 */
-#define SAMA5D3_ID_UART0 16 /* UART 0 */
-#define SAMA5D3_ID_UART1 17 /* UART 1 */
-#define SAMA5D3_ID_TWI0 18 /* Two-Wire Interface 0 */
-#define SAMA5D3_ID_TWI1 19 /* Two-Wire Interface 1 */
-#define SAMA5D3_ID_TWI2 20 /* Two-Wire Interface 2 */
-#define SAMA5D3_ID_HSMCI0 21 /* MCI */
-#define SAMA5D3_ID_HSMCI1 22 /* MCI */
-#define SAMA5D3_ID_HSMCI2 23 /* MCI */
-#define SAMA5D3_ID_SPI0 24 /* Serial Peripheral Interface 0 */
-#define SAMA5D3_ID_SPI1 25 /* Serial Peripheral Interface 1 */
-#define SAMA5D3_ID_TC0 26 /* Timer Counter 0 */
-#define SAMA5D3_ID_TC1 27 /* Timer Counter 2 */
-#define SAMA5D3_ID_PWM 28 /* Pulse Width Modulation Controller */
-#define SAMA5D3_ID_ADC 29 /* Touch Screen ADC Controller */
-#define SAMA5D3_ID_DMA0 30 /* DMA Controller 0 */
-#define SAMA5D3_ID_DMA1 31 /* DMA Controller 1 */
-#define SAMA5D3_ID_UHPHS 32 /* USB Host High Speed */
-#define SAMA5D3_ID_UDPHS 33 /* USB Device High Speed */
-#define SAMA5D3_ID_GMAC 34 /* Gigabit Ethernet MAC */
-#define SAMA5D3_ID_EMAC 35 /* Ethernet MAC */
-#define SAMA5D3_ID_LCDC 36 /* LCD Controller */
-#define SAMA5D3_ID_ISI 37 /* Image Sensor Interface */
-#define SAMA5D3_ID_SSC0 38 /* Synchronous Serial Controller 0 */
-#define SAMA5D3_ID_SSC1 39 /* Synchronous Serial Controller 1 */
-#define SAMA5D3_ID_CAN0 40 /* CAN Controller 0 */
-#define SAMA5D3_ID_CAN1 41 /* CAN Controller 1 */
-#define SAMA5D3_ID_SHA 42 /* Secure Hash Algorithm */
-#define SAMA5D3_ID_AES 43 /* Advanced Encryption Standard */
-#define SAMA5D3_ID_TDES 44 /* Triple Data Encryption Standard */
-#define SAMA5D3_ID_TRNG 45 /* True Random Generator Number */
-#define SAMA5D3_ID_IRQ0 47 /* Advanced Interrupt Controller (IRQ0) */
-
-/*
- * User Peripheral physical base addresses.
- */
-#define SAMA5D3_BASE_USART0 0xf001c000
-#define SAMA5D3_BASE_USART1 0xf0020000
-#define SAMA5D3_BASE_USART2 0xf8020000
-#define SAMA5D3_BASE_USART3 0xf8024000
-
-/*
- * System Peripherals
- */
-#define SAMA5D3_BASE_RTC 0xfffffeb0
-
-/*
- * Internal Memory
- */
-#define SAMA5D3_SRAM_BASE 0x00300000 /* Internal SRAM base address */
-#define SAMA5D3_SRAM_SIZE (128 * SZ_1K) /* Internal SRAM size (128Kb) */
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/sama5d4.h b/arch/arm/mach-at91/include/mach/sama5d4.h
deleted file mode 100644
index f256a45d9854..000000000000
--- a/arch/arm/mach-at91/include/mach/sama5d4.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Chip-specific header file for the SAMA5D4 family
- *
- * Copyright (C) 2013 Atmel Corporation,
- * Nicolas Ferre <nicolas.ferre@atmel.com>
- *
- * Common definitions.
- * Based on SAMA5D4 datasheet.
- *
- * Licensed under GPLv2 or later.
- */
-
-#ifndef SAMA5D4_H
-#define SAMA5D4_H
-
-/*
- * User Peripheral physical base addresses.
- */
-#define SAMA5D4_BASE_USART3 0xfc00c000 /* (USART3 non-secure) Base Address */
-#define SAMA5D4_BASE_PMC 0xf0018000 /* (PMC) Base Address */
-#define SAMA5D4_BASE_MPDDRC 0xf0010000 /* (MPDDRC) Base Address */
-#define SAMA5D4_BASE_PIOD 0xfc068000 /* (PIOD) Base Address */
-
-/* Some other peripherals */
-#define SAMA5D4_BASE_SYS2 SAMA5D4_BASE_PIOD
-
-/*
- * Internal Memory.
- */
-#define SAMA5D4_NS_SRAM_BASE 0x00210000 /* Internal SRAM base address Non-Secure */
-#define SAMA5D4_NS_SRAM_SIZE (64 * SZ_1K) /* Internal SRAM size Non-Secure part (64Kb) */
-
-#endif
--
2.1.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v3 6/7] ARM: at91: remove hardware.h
2015-03-13 21:57 [PATCH v3 0/7] Switch mach-at91 to multiplatform Alexandre Belloni
` (4 preceding siblings ...)
2015-03-13 21:57 ` [PATCH v3 5/7] ARM: at91: remove SoC headers Alexandre Belloni
@ 2015-03-13 21:57 ` Alexandre Belloni
2015-03-13 21:57 ` [PATCH v3 7/7] ARM: at91: drop AT91_TIMER_HZ Alexandre Belloni
` (2 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Alexandre Belloni @ 2015-03-13 21:57 UTC (permalink / raw)
To: Nicolas Ferre
Cc: Boris Brezillon, Jean-Christophe Plagniol-Villard, Arnd Bergmann,
linux-kernel, linux-arm-kernel, Alexandre Belloni
hardware.h is now mostyl unused, move the remaining declarations to pm.c and
remove it.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/mach-at91/include/mach/hardware.h | 123 -----------------------------
arch/arm/mach-at91/pm.c | 11 ++-
arch/arm/mach-at91/pm_suspend.S | 1 -
arch/arm/mach-at91/sama5.c | 2 -
4 files changed, 9 insertions(+), 128 deletions(-)
delete mode 100644 arch/arm/mach-at91/include/mach/hardware.h
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
deleted file mode 100644
index 2f8ce2d69fdb..000000000000
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/hardware.h
- *
- * Copyright (C) 2003 SAN People
- * Copyright (C) 2003 ATMEL
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include <asm/sizes.h>
-
-/* DBGU base */
-/* rm9200, 9260/9g20, 9261/9g10, 9rl */
-#define AT91_BASE_DBGU0 0xfffff200
-/* 9263, 9g45, sama5d3 */
-#define AT91_BASE_DBGU1 0xffffee00
-/* sama5d4 */
-#define AT91_BASE_DBGU2 0xfc069000
-
-/*
- * On all at91 except rm9200 and x40 have the System Controller starts
- * at address 0xffffc000 and has a size of 16KiB.
- *
- * On rm9200 it's start at 0xfffe4000 of 111KiB with non reserved data starting
- * at 0xfffff000
- *
- * Removes the individual definitions of AT91_BASE_SYS and
- * replaces them with a common version at base 0xfffffc000 and size 16KiB
- * and map the same memory space
- */
-#define AT91_BASE_SYS 0xffffc000
-
-/*
- * On sama5d4 there is no system controller, we map some needed peripherals
- */
-#define AT91_ALT_BASE_SYS 0xfc069000
-
-/*
- * On all at91 have the Advanced Interrupt Controller starts at address
- * 0xfffff000 and the Power Management Controller starts at 0xfffffc00
- */
-#define AT91_AIC 0xfffff000
-#define AT91_PMC 0xfffffc00
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS 1 /* System Peripherals */
-
-#ifdef CONFIG_MMU
-/*
- * Remap the peripherals from address 0xFFF78000 .. 0xFFFFFFFF
- * to 0xFEF78000 .. 0xFF000000. (544Kb)
- */
-#define AT91_IO_PHYS_BASE 0xFFF78000
-#define AT91_IO_VIRT_BASE IOMEM(0xFF000000 - AT91_IO_SIZE)
-
-/*
- * On sama5d4, remap the peripherals from address 0xFC069000 .. 0xFC06F000
- * to 0xFB069000 .. 0xFB06F000. (24Kb)
- */
-#define AT91_ALT_IO_PHYS_BASE AT91_ALT_BASE_SYS
-#define AT91_ALT_IO_VIRT_BASE IOMEM(0xFB069000)
-#else
-/*
- * Identity mapping for the non MMU case.
- */
-#define AT91_IO_PHYS_BASE AT91_BASE_SYS
-#define AT91_IO_VIRT_BASE IOMEM(AT91_IO_PHYS_BASE)
-
-#define AT91_ALT_IO_PHYS_BASE AT91_ALT_BASE_SYS
-#define AT91_ALT_IO_VIRT_BASE IOMEM(AT91_ALT_BASE_SYS)
-#endif
-
-#define AT91_IO_SIZE (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1)
-
- /* Convert a physical IO address to virtual IO address */
-#define AT91_IO_P2V(x) ((x) - AT91_IO_PHYS_BASE + AT91_IO_VIRT_BASE)
-#define AT91_ALT_IO_P2V(x) ((x) - AT91_ALT_IO_PHYS_BASE + AT91_ALT_IO_VIRT_BASE)
-
-/*
- * Virtual to Physical Address mapping for IO devices.
- */
-#define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS)
-#define AT91_ALT_VA_BASE_SYS AT91_ALT_IO_P2V(AT91_ALT_BASE_SYS)
-
- /* Internal SRAM is mapped below the IO devices */
-#define AT91_SRAM_MAX SZ_1M
-#define AT91_VIRT_BASE (AT91_IO_VIRT_BASE - AT91_SRAM_MAX)
-
-/* External Memory Map */
-#define AT91_CHIPSELECT_0 0x10000000
-#define AT91_CHIPSELECT_1 0x20000000
-#define AT91_CHIPSELECT_2 0x30000000
-#define AT91_CHIPSELECT_3 0x40000000
-#define AT91_CHIPSELECT_4 0x50000000
-#define AT91_CHIPSELECT_5 0x60000000
-#define AT91_CHIPSELECT_6 0x70000000
-#define AT91_CHIPSELECT_7 0x80000000
-
-/* Clocks */
-#define AT91_SLOW_CLOCK 32768 /* slow clock */
-
-/*
- * FIXME: this is needed to communicate between the pinctrl driver and
- * the PM implementation in the machine. Possibly part of the PM
- * implementation should be moved down into the pinctrl driver and get
- * called as part of the generic suspend/resume path.
- */
-#ifndef __ASSEMBLY__
-extern void at91_pinctrl_gpio_suspend(void);
-extern void at91_pinctrl_gpio_resume(void);
-#endif
-
-#endif
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 2a12c01afc67..f93a735ba327 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -32,11 +32,18 @@
#include <asm/fncpy.h>
#include <asm/cacheflush.h>
-#include <mach/hardware.h>
-
#include "generic.h"
#include "pm.h"
+/*
+ * FIXME: this is needed to communicate between the pinctrl driver and
+ * the PM implementation in the machine. Possibly part of the PM
+ * implementation should be moved down into the pinctrl driver and get
+ * called as part of the generic suspend/resume path.
+ */
+extern void at91_pinctrl_gpio_suspend(void);
+extern void at91_pinctrl_gpio_resume(void);
+
static struct {
unsigned long uhp_udp_mask;
int memctrl;
diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S
index 7c444c259740..bd22b2c8a051 100644
--- a/arch/arm/mach-at91/pm_suspend.S
+++ b/arch/arm/mach-at91/pm_suspend.S
@@ -13,7 +13,6 @@
*/
#include <linux/linkage.h>
#include <linux/clk/at91_pmc.h>
-#include <mach/hardware.h>
#include <mach/at91_ramc.h>
#include "pm.h"
diff --git a/arch/arm/mach-at91/sama5.c b/arch/arm/mach-at91/sama5.c
index ef5d2073774b..41d829d8e7d5 100644
--- a/arch/arm/mach-at91/sama5.c
+++ b/arch/arm/mach-at91/sama5.c
@@ -14,8 +14,6 @@
#include <asm/mach/map.h>
#include <asm/system_misc.h>
-#include <mach/hardware.h>
-
#include "generic.h"
#include "soc.h"
--
2.1.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v3 7/7] ARM: at91: drop AT91_TIMER_HZ
2015-03-13 21:57 [PATCH v3 0/7] Switch mach-at91 to multiplatform Alexandre Belloni
` (5 preceding siblings ...)
2015-03-13 21:57 ` [PATCH v3 6/7] ARM: at91: remove hardware.h Alexandre Belloni
@ 2015-03-13 21:57 ` Alexandre Belloni
2015-03-13 22:04 ` [PATCH v3 0/7] Switch mach-at91 to multiplatform Alexandre Belloni
2015-03-14 10:23 ` Arnd Bergmann
8 siblings, 0 replies; 11+ messages in thread
From: Alexandre Belloni @ 2015-03-13 21:57 UTC (permalink / raw)
To: Nicolas Ferre
Cc: Boris Brezillon, Jean-Christophe Plagniol-Villard, Arnd Bergmann,
linux-kernel, linux-arm-kernel, Alexandre Belloni
Drop AT91_TIMER_HZ as this can be handled using HZ_FIXED. Initial help message
was:
On AT91rm9200 chips where you're using a system clock derived
from the 32768 Hz hardware clock, this tick rate should divide
it exactly: use a power-of-two value, such as 128 or 256, to
reduce timing errors caused by rounding.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/Kconfig | 2 +-
arch/arm/mach-at91/Kconfig | 18 ------------------
2 files changed, 1 insertion(+), 19 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a1d153098001..8d5c4f9c15f9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1502,7 +1502,7 @@ config HZ_FIXED
int
default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
ARCH_S5PV210 || ARCH_EXYNOS4
- default AT91_TIMER_HZ if ARCH_AT91
+ default 128 if SOC_AT91RM9200
default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
default 0
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 4662eae06753..da977699c037 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -100,22 +100,4 @@ config SOC_SAMA5
select SOC_SAM_V7
select SRAM if PM
-comment "Atmel SoCs Feature Selections"
-
-config AT91_TIMER_HZ
- int "Kernel HZ (jiffies per second)"
- range 32 1024
- depends on ARCH_AT91
- default "128" if SOC_AT91RM9200
- default "100"
- help
- On AT91rm9200 chips where you're using a system clock derived
- from the 32768 Hz hardware clock, this tick rate should divide
- it exactly: use a power-of-two value, such as 128 or 256, to
- reduce timing errors caused by rounding.
-
- On AT91sam926x chips, or otherwise when using a higher precision
- system clock (of at least several MHz), rounding is less of a
- problem so it can be safer to use a decimal values like 100.
-
endif
--
2.1.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v3 0/7] Switch mach-at91 to multiplatform
2015-03-13 21:57 [PATCH v3 0/7] Switch mach-at91 to multiplatform Alexandre Belloni
` (6 preceding siblings ...)
2015-03-13 21:57 ` [PATCH v3 7/7] ARM: at91: drop AT91_TIMER_HZ Alexandre Belloni
@ 2015-03-13 22:04 ` Alexandre Belloni
2015-03-14 10:23 ` Arnd Bergmann
8 siblings, 0 replies; 11+ messages in thread
From: Alexandre Belloni @ 2015-03-13 22:04 UTC (permalink / raw)
To: Nicolas Ferre
Cc: Boris Brezillon, Jean-Christophe Plagniol-Villard, Arnd Bergmann,
linux-kernel, linux-arm-kernel
Nicolas,
On 13/03/2015 at 22:57:17 +0100, Alexandre Belloni wrote :
> AT91 is now ready to switch to multiplatform. Do it and clean the remaining mach
> includes.
>
> Changes in v3:
> - use a menu structure as asked by Arnd
> - remove useless selects as pointed by Rob
> - drop a patch that has already been applied
> - add a patch to remove AT91_TIMER_HZ
I forgot to add that I rebased it on your at91-4.1-cleanup branch as the
merge conflict in arch/arm/mach-at91/Kconfig was not easy to solve.
--
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v3 0/7] Switch mach-at91 to multiplatform
2015-03-13 21:57 [PATCH v3 0/7] Switch mach-at91 to multiplatform Alexandre Belloni
` (7 preceding siblings ...)
2015-03-13 22:04 ` [PATCH v3 0/7] Switch mach-at91 to multiplatform Alexandre Belloni
@ 2015-03-14 10:23 ` Arnd Bergmann
2015-03-14 13:58 ` Alexandre Belloni
8 siblings, 1 reply; 11+ messages in thread
From: Arnd Bergmann @ 2015-03-14 10:23 UTC (permalink / raw)
To: Alexandre Belloni
Cc: Nicolas Ferre, Boris Brezillon, Jean-Christophe Plagniol-Villard,
linux-kernel, linux-arm-kernel
On Friday 13 March 2015 22:57:17 Alexandre Belloni wrote:
> AT91 is now ready to switch to multiplatform. Do it and clean the remaining mach
> includes.
>
> Changes in v3:
> - use a menu structure as asked by Arnd
> - remove useless selects as pointed by Rob
> - drop a patch that has already been applied
> - add a patch to remove AT91_TIMER_HZ
>
>
Looks all good to me. Are there any headers left in include/mach that
can be moved to mach-at91, or does this cover all of them?
Arnd
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v3 0/7] Switch mach-at91 to multiplatform
2015-03-14 10:23 ` Arnd Bergmann
@ 2015-03-14 13:58 ` Alexandre Belloni
0 siblings, 0 replies; 11+ messages in thread
From: Alexandre Belloni @ 2015-03-14 13:58 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Nicolas Ferre, Boris Brezillon, Jean-Christophe Plagniol-Villard,
linux-kernel, linux-arm-kernel
On 14/03/2015 at 11:23:18 +0100, Arnd Bergmann wrote :
> On Friday 13 March 2015 22:57:17 Alexandre Belloni wrote:
> > AT91 is now ready to switch to multiplatform. Do it and clean the remaining mach
> > includes.
> >
> > Changes in v3:
> > - use a menu structure as asked by Arnd
> > - remove useless selects as pointed by Rob
> > - drop a patch that has already been applied
> > - add a patch to remove AT91_TIMER_HZ
> >
> >
>
> Looks all good to me. Are there any headers left in include/mach that
> can be moved to mach-at91, or does this cover all of them?
>
There are existing series removing the need for them. However, depending
on the time we take to remove them, I'm not sure it is worth moving
those headers now.
--
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 11+ messages in thread