* [PATCH 0/6] Introduce Allwinner A33 support
@ 2015-05-10 6:46 Vishnu Patekar
2015-05-10 6:46 ` [PATCH 1/6] ARM: sunxi: Add Machine support for A33 Vishnu Patekar
` (6 more replies)
0 siblings, 7 replies; 30+ messages in thread
From: Vishnu Patekar @ 2015-05-10 6:46 UTC (permalink / raw)
To: maxime.ripard, emilio, linus.walleij, robh+dt
Cc: hdegoede, wens, jenskuske, arnd, linux-arm-kernel, linux-kernel,
linux-sunxi, devicetree, Vishnu Patekar
Hello everyone,
This patch series introduces basic kernel support for Allwinner's A33 SoC,
A33 is very similar to A23.
mainly adds common sun8i dtsi, a33 pinctrl. It also adds interrupts, timers,
watchdog, RTC, and UARTs, which are mostly compatible to
those in earlier SoCs like A23 and A31, and can simply be reused.
These patches are based on
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
Patch 1 adds machine support for the A33.
Patch 2 adds the pin sets for the A33 main PIO.
Patch 3 adds support to reuse A23 clocks. A33 specific clocks not yet implemented.
Patch 4 adds common sun8i.dtsi, modified sun8i-a23.dtsi and a23 based dts, I've referred the h3 dtsi
by Jens Kuske.
removed the checkpatch warning related to Linux Foundation address in dtsi,dts.
Patch 5 adds the DTSI for the A33, based on common sun8i.dtsi.
Patch 6 adds a DT for the ET_Q8_A33 tablet, which these patches
were developed and tested with.
Vishnu Patekar (6):
ARM: sunxi: Add Machine support for A33
pinctrl: sunxi: add allwinner A33 PIO controller support
clk: sunxi: Add A33 clock for compilation
ARM: dts: sunxi: add common sun8i dtsi
ARM: dts: sunxi: Add Allwinner A33 DTSI
ARM: dts: sun8i: Add ET-Q8 A33 support
Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 2 +
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts | 6 +-
arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts | 6 +-
arch/arm/boot/dts/sun8i-a23.dtsi | 432 +----------------
arch/arm/boot/dts/sun8i-a33-et-q8.dts | 108 +++++
arch/arm/boot/dts/sun8i-a33.dtsi | 217 +++++++++
arch/arm/boot/dts/sun8i.dtsi | 481 +++++++++++++++++++
arch/arm/mach-sunxi/Kconfig | 2 +-
arch/arm/mach-sunxi/platsmp.c | 2 +-
arch/arm/mach-sunxi/sunxi.c | 4 +-
drivers/clk/sunxi/clk-sunxi.c | 1 +
drivers/pinctrl/sunxi/Kconfig | 5 +
drivers/pinctrl/sunxi/Makefile | 1 +
drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c | 513 +++++++++++++++++++++
16 files changed, 1340 insertions(+), 444 deletions(-)
create mode 100644 arch/arm/boot/dts/sun8i-a33-et-q8.dts
create mode 100644 arch/arm/boot/dts/sun8i-a33.dtsi
create mode 100644 arch/arm/boot/dts/sun8i.dtsi
create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
--
1.9.1
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 1/6] ARM: sunxi: Add Machine support for A33
2015-05-10 6:46 [PATCH 0/6] Introduce Allwinner A33 support Vishnu Patekar
@ 2015-05-10 6:46 ` Vishnu Patekar
2015-05-10 8:49 ` Hans de Goede
2015-05-10 10:33 ` Maxime Ripard
2015-05-10 6:46 ` [PATCH 2/6] pinctrl: sunxi: add allwinner A33 PIO controller support Vishnu Patekar
` (5 subsequent siblings)
6 siblings, 2 replies; 30+ messages in thread
From: Vishnu Patekar @ 2015-05-10 6:46 UTC (permalink / raw)
To: maxime.ripard, emilio, linus.walleij, robh+dt
Cc: hdegoede, wens, jenskuske, arnd, linux-arm-kernel, linux-kernel,
linux-sunxi, devicetree, Vishnu Patekar
Allwinnner A33 quad core cortex-a7 based SOC.
It is similar to A23.
Renamed cpu method to "allwinner,sun8i" for common sun8i smp.
smp code is generic for A23, A33 and hopefully H3.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
---
Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
arch/arm/mach-sunxi/Kconfig | 2 +-
arch/arm/mach-sunxi/platsmp.c | 2 +-
arch/arm/mach-sunxi/sunxi.c | 4 ++--
4 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
index 42941fd..e32f082 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.txt
+++ b/Documentation/devicetree/bindings/arm/sunxi.txt
@@ -9,4 +9,5 @@ using one of the following compatible strings:
allwinner,sun6i-a31
allwinner,sun7i-a20
allwinner,sun8i-a23
+ allwinner,sun8i-a33
allwinner,sun9i-a80
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 81502b9..38bedd8 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -35,7 +35,7 @@ config MACH_SUN7I
select SUN5I_HSTIMER
config MACH_SUN8I
- bool "Allwinner A23 (sun8i) SoCs support"
+ bool "Allwinner (sun8i) SoCs support"
default ARCH_SUNXI
select ARM_GIC
select MFD_SUN6I_PRCM
diff --git a/arch/arm/mach-sunxi/platsmp.c b/arch/arm/mach-sunxi/platsmp.c
index e8483ec..c56b501 100644
--- a/arch/arm/mach-sunxi/platsmp.c
+++ b/arch/arm/mach-sunxi/platsmp.c
@@ -189,4 +189,4 @@ struct smp_operations sun8i_smp_ops __initdata = {
.smp_prepare_cpus = sun8i_smp_prepare_cpus,
.smp_boot_secondary = sun8i_smp_boot_secondary,
};
-CPU_METHOD_OF_DECLARE(sun8i_a23_smp, "allwinner,sun8i-a23", &sun8i_smp_ops);
+CPU_METHOD_OF_DECLARE(sun8i_smp, "allwinner,sun8i", &sun8i_smp_ops);
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 1bc811a..8937d0d 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -66,11 +66,11 @@ DT_MACHINE_START(SUN7I_DT, "Allwinner sun7i (A20) Family")
MACHINE_END
static const char * const sun8i_board_dt_compat[] = {
- "allwinner,sun8i-a23",
+ "allwinner,sun8i",
NULL,
};
-DT_MACHINE_START(SUN8I_DT, "Allwinner sun8i (A23) Family")
+DT_MACHINE_START(SUN8I_DT, "Allwinner sun8i Family")
.dt_compat = sun8i_board_dt_compat,
.init_late = sunxi_dt_cpufreq_init,
MACHINE_END
--
1.9.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 2/6] pinctrl: sunxi: add allwinner A33 PIO controller support
2015-05-10 6:46 [PATCH 0/6] Introduce Allwinner A33 support Vishnu Patekar
2015-05-10 6:46 ` [PATCH 1/6] ARM: sunxi: Add Machine support for A33 Vishnu Patekar
@ 2015-05-10 6:46 ` Vishnu Patekar
2015-05-10 8:50 ` Hans de Goede
` (2 more replies)
2015-05-10 6:46 ` [PATCH 3/6] clk: sunxi: Add A33 clock for compilation Vishnu Patekar
` (4 subsequent siblings)
6 siblings, 3 replies; 30+ messages in thread
From: Vishnu Patekar @ 2015-05-10 6:46 UTC (permalink / raw)
To: maxime.ripard, emilio, linus.walleij, robh+dt
Cc: hdegoede, wens, jenskuske, arnd, linux-arm-kernel, linux-kernel,
linux-sunxi, devicetree, Vishnu Patekar
A33 PIO has 7 ports which starts from PB and has two interrupt ports.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
---
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 2 +
drivers/pinctrl/sunxi/Kconfig | 5 +
drivers/pinctrl/sunxi/Makefile | 1 +
drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c | 513 +++++++++++++++++++++
4 files changed, 521 insertions(+)
create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index fdd8046..9462ab7 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -16,6 +16,8 @@ Required properties:
"allwinner,sun7i-a20-pinctrl"
"allwinner,sun8i-a23-pinctrl"
"allwinner,sun8i-a23-r-pinctrl"
+ "allwinner,sun8i-a33-pinctrl"
+
- reg: Should contain the register physical address and length for the
pin controller.
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index 2eb893e..dd83aab 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -38,6 +38,11 @@ config PINCTRL_SUN8I_A23
def_bool MACH_SUN8I
select PINCTRL_SUNXI_COMMON
+
+config PINCTRL_SUN8I_A33
+ def_bool MACH_SUN8I
+ select PINCTRL_SUNXI_COMMON
+
config PINCTRL_SUN8I_A23_R
def_bool MACH_SUN8I
depends on RESET_CONTROLLER
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index b796d57..227a121 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -11,4 +11,5 @@ obj-$(CONFIG_PINCTRL_SUN6I_A31_R) += pinctrl-sun6i-a31-r.o
obj-$(CONFIG_PINCTRL_SUN7I_A20) += pinctrl-sun7i-a20.o
obj-$(CONFIG_PINCTRL_SUN8I_A23) += pinctrl-sun8i-a23.o
obj-$(CONFIG_PINCTRL_SUN8I_A23_R) += pinctrl-sun8i-a23-r.o
+obj-$(CONFIG_PINCTRL_SUN8I_A33) += pinctrl-sun8i-a33.o
obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
new file mode 100644
index 0000000..00265f0
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
@@ -0,0 +1,513 @@
+/*
+ * Allwinner a33 SoCs pinctrl driver.
+ *
+ * Copyright (C) 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
+ *
+ * Based on pinctrl-sun8i-a23.c, which is:
+ * Copyright (C) 2014 Chen-Yu Tsai <wens@csie.org>
+ * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin sun8i_a33_pins[] = {
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart2"), /* TX */
+ SUNXI_FUNCTION(0x3, "uart0"), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 0)), /* PB_EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart2"), /* RX */
+ SUNXI_FUNCTION(0x3, "uart0"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 1)), /* PB_EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 2)), /* PB_EINT2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 3)), /* PB_EINT3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s0"), /* SYNC */
+ SUNXI_FUNCTION(0x3, "aif2"), /* SYNC */
+ SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 4)), /* PB_EINT4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */
+ SUNXI_FUNCTION(0x3, "aif2"), /* BCLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 5)), /* PB_EINT5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s0"), /* DOUT */
+ SUNXI_FUNCTION(0x3, "aif2"), /* DOUT */
+ SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 6)), /* PB_EINT6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s0"), /* DIN */
+ SUNXI_FUNCTION(0x3, "aif2"), /* DIN */
+ SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 7)), /* PB_EINT7 */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* WE */
+ SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
+ SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
+ SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */
+ SUNXI_FUNCTION(0x3, "spi0")), /* CS */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* RE */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand"), /* DQ6 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand"), /* DQ7 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand"), /* DQS */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* RST */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
+ SUNXI_FUNCTION(0x3, "mmc1")), /* CLK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
+ SUNXI_FUNCTION(0x3, "mmc1")), /* CMD */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
+ SUNXI_FUNCTION(0x3, "mmc1")), /* D0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
+ SUNXI_FUNCTION(0x3, "mmc1")), /* D1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
+ SUNXI_FUNCTION(0x3, "mmc1")), /* D2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
+ SUNXI_FUNCTION(0x3, "mmc1")), /* D3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
+ SUNXI_FUNCTION(0x3, "uart1")), /* TX */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
+ SUNXI_FUNCTION(0x3, "uart1")), /* RX */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
+ SUNXI_FUNCTION(0x3, "uart1")), /* RTS */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
+ SUNXI_FUNCTION(0x3, "uart1")), /* CTS */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
+ SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
+ SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
+ SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
+ SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
+ SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
+ SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
+ SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
+ SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
+ SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
+ SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi")), /* PCLK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi")), /* MCLK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi")), /* HSYNC */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi")), /* VSYNC */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi")), /* D0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi")), /* D1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi")), /* D2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi")), /* D3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi")), /* D4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi")), /* D5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi")), /* D6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi")), /* D7 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* SCK */
+ SUNXI_FUNCTION(0x3, "i2c2")), /* SCK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "csi"), /* SDA */
+ SUNXI_FUNCTION(0x3, "i2c2")), /* SDA */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out")),
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
+ SUNXI_FUNCTION(0x3, "jtag")), /* MS1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
+ SUNXI_FUNCTION(0x3, "jtag")), /* DI1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
+ SUNXI_FUNCTION(0x3, "uart0")), /* TX */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
+ SUNXI_FUNCTION(0x3, "jtag")), /* DO1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
+ SUNXI_FUNCTION(0x3, "uart0")), /* RX */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
+ SUNXI_FUNCTION(0x3, "jtag")), /* CK1 */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 0)), /* PG_EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
+ SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 1)), /* PG_EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
+ SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 2)), /* PG_EINT2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
+ SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 3)), /* PG_EINT3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
+ SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 4)), /* PG_EINT4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
+ SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 5)), /* PG_EINT5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart1"), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 6)), /* PG_EINT6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart1"), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 7)), /* PG_EINT7 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 8)), /* PG_EINT8 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 9)), /* PG_EINT9 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s1"), /* SYNC */
+ SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 10)), /* PG_EINT10 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s1"), /* CLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 11)), /* PG_EINT11 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s1"), /* DOUT */
+ SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 12)), /* PG_EINT12 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s1"), /* DIN */
+ SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 13)), /* PG_EINT13 */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "pwm0")),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "pwm1")),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi0"), /* CS */
+ SUNXI_FUNCTION(0x3, "uart3")), /* TX */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
+ SUNXI_FUNCTION(0x3, "uart3")), /* RX */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi0"), /* DOUT */
+ SUNXI_FUNCTION(0x3, "uart3")), /* RTS */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi0"), /* DIN */
+ SUNXI_FUNCTION(0x3, "uart3")), /* CTS */
+};
+
+static const struct sunxi_pinctrl_desc sun8i_a33_pinctrl_data = {
+ .pins = sun8i_a33_pins,
+ .npins = ARRAY_SIZE(sun8i_a33_pins),
+ .irq_banks = 2,
+};
+
+static int sun8i_a33_pinctrl_probe(struct platform_device *pdev)
+{
+ return sunxi_pinctrl_init(pdev,
+ &sun8i_a33_pinctrl_data);
+}
+
+static const struct of_device_id sun8i_a33_pinctrl_match[] = {
+ { .compatible = "allwinner,sun8i-a33-pinctrl", },
+ {}
+};
+MODULE_DEVICE_TABLE(of, sun8i_a33_pinctrl_match);
+
+static struct platform_driver sun8i_a33_pinctrl_driver = {
+ .probe = sun8i_a33_pinctrl_probe,
+ .driver = {
+ .name = "sun8i-a33-pinctrl",
+ .of_match_table = sun8i_a33_pinctrl_match,
+ },
+};
+module_platform_driver(sun8i_a33_pinctrl_driver);
+
+MODULE_AUTHOR("Vishnu Patekar <vishnupatekar0510@gmail.com>");
+MODULE_DESCRIPTION("Allwinner a33 pinctrl driver");
+MODULE_LICENSE("GPL");
--
1.9.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 3/6] clk: sunxi: Add A33 clock for compilation
2015-05-10 6:46 [PATCH 0/6] Introduce Allwinner A33 support Vishnu Patekar
2015-05-10 6:46 ` [PATCH 1/6] ARM: sunxi: Add Machine support for A33 Vishnu Patekar
2015-05-10 6:46 ` [PATCH 2/6] pinctrl: sunxi: add allwinner A33 PIO controller support Vishnu Patekar
@ 2015-05-10 6:46 ` Vishnu Patekar
2015-05-10 10:17 ` Maxime Ripard
2015-05-10 6:46 ` [PATCH 4/6] ARM: dts: sunxi: add common sun8i dtsi Vishnu Patekar
` (3 subsequent siblings)
6 siblings, 1 reply; 30+ messages in thread
From: Vishnu Patekar @ 2015-05-10 6:46 UTC (permalink / raw)
To: maxime.ripard, emilio, linus.walleij, robh+dt
Cc: hdegoede, wens, jenskuske, arnd, linux-arm-kernel, linux-kernel,
linux-sunxi, devicetree, Vishnu Patekar
A33 clock control unit is similar to A23.
A33 specific clocks are not yet implemented, added CLK_OF_DECLARE
to get it compiled for A33.
Signed-off-by: VishnuPatekar <vishnupatekar0510@gmail.com>
---
drivers/clk/sunxi/clk-sunxi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 7e1e2bd..6d25e4e 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -1389,6 +1389,7 @@ static void __init sun6i_init_clocks(struct device_node *node)
CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sun6i_init_clocks);
CLK_OF_DECLARE(sun6i_a31s_clk_init, "allwinner,sun6i-a31s", sun6i_init_clocks);
CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks);
+CLK_OF_DECLARE(sun8i_a33_clk_init, "allwinner,sun8i-a33", sun6i_init_clocks);
static void __init sun9i_init_clocks(struct device_node *node)
{
--
1.9.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 4/6] ARM: dts: sunxi: add common sun8i dtsi
2015-05-10 6:46 [PATCH 0/6] Introduce Allwinner A33 support Vishnu Patekar
` (2 preceding siblings ...)
2015-05-10 6:46 ` [PATCH 3/6] clk: sunxi: Add A33 clock for compilation Vishnu Patekar
@ 2015-05-10 6:46 ` Vishnu Patekar
2015-05-10 8:52 ` Hans de Goede
2015-05-10 10:41 ` Maxime Ripard
2015-05-10 6:46 ` [PATCH 5/6] ARM: dts: sunxi: Add Allwinner A33 DTSI Vishnu Patekar
` (2 subsequent siblings)
6 siblings, 2 replies; 30+ messages in thread
From: Vishnu Patekar @ 2015-05-10 6:46 UTC (permalink / raw)
To: maxime.ripard, emilio, linus.walleij, robh+dt
Cc: hdegoede, wens, jenskuske, arnd, linux-arm-kernel, linux-kernel,
linux-sunxi, devicetree, Vishnu Patekar
added the common sun8i.dtsi and "allwinner,sun8i" compatible for common
sun8i features, I've referred the h3 dtsi by Jens Kuske.
accordingly modified the sun8i-a23.dtsi and a23 dts.
I don't have a23 device, however, dts got compiled.
Signed-off-by: VishnuPatekar <vishnupatekar0510@gmail.com>
---
arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts | 6 +-
arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts | 6 +-
arch/arm/boot/dts/sun8i-a23.dtsi | 432 +----------------------
arch/arm/boot/dts/sun8i.dtsi | 481 ++++++++++++++++++++++++++
4 files changed, 486 insertions(+), 439 deletions(-)
create mode 100644 arch/arm/boot/dts/sun8i.dtsi
diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts
index dd31c53..b3f19e7 100644
--- a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts
+++ b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts
@@ -16,10 +16,6 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
- * You should have received a copy of the GNU General Public
- * License along with this file; if not, write to the Free
- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
*
* Or, alternatively,
*
@@ -55,5 +51,5 @@
/ {
model = "Ippo Q8H Dual Core Tablet (v1.2)";
- compatible = "ippo,q8h-v1.2", "allwinner,sun8i-a23";
+ compatible = "ippo,q8h-v1.2", "allwinner,sun8i", "allwinner,sun8i-a23";
};
diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
index f5658d1..5db4010 100644
--- a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
+++ b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
@@ -18,10 +18,6 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
- * You should have received a copy of the GNU General Public
- * License along with this file; if not, write to the Free
- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
*
* Or, alternatively,
*
@@ -57,7 +53,7 @@
/ {
model = "Ippo Q8H Dual Core Tablet (v5)";
- compatible = "ippo,q8h-v5", "allwinner,sun8i-a23";
+ compatible = "ippo,q8h-v5", "allwinner,sun8i", "allwinner,sun8i-a23";
aliases {
serial0 = &r_uart;
diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi
index 6d6eda3..c17be9e 100644
--- a/arch/arm/boot/dts/sun8i-a23.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23.dtsi
@@ -18,10 +18,6 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
- * You should have received a copy of the GNU General Public
- * License along with this file; if not, write to the Free
- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
*
* Or, alternatively,
*
@@ -47,41 +43,11 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
-#include "skeleton.dtsi"
-
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-
-#include <dt-bindings/pinctrl/sun4i-a10.h>
+#include "sun8i.dtsi"
/ {
- interrupt-parent = <&gic>;
-
- chosen {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- framebuffer@0 {
- compatible = "allwinner,simple-framebuffer",
- "simple-framebuffer";
- allwinner,pipeline = "de_be0-lcd0";
- clocks = <&pll6 0>;
- status = "disabled";
- };
- };
-
- timer {
- compatible = "arm,armv7-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
- clock-frequency = <24000000>;
- arm,cpu-registers-not-fw-configured;
- };
-
cpus {
- enable-method = "allwinner,sun8i-a23";
+ enable-method = "allwinner,sun8i";
#address-cells = <1>;
#size-cells = <0>;
@@ -103,32 +69,6 @@
};
clocks {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- osc24M: osc24M_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- clock-output-names = "osc24M";
- };
-
- osc32k: osc32k_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- clock-output-names = "osc32k";
- };
-
- pll1: clk@01c20000 {
- #clock-cells = <0>;
- compatible = "allwinner,sun8i-a23-pll1-clk";
- reg = <0x01c20000 0x4>;
- clocks = <&osc24M>;
- clock-output-names = "pll1";
- };
-
/* dummy clock until actually implemented */
pll5: pll5_clk {
#clock-cells = <0>;
@@ -137,29 +77,6 @@
clock-output-names = "pll5";
};
- pll6: clk@01c20028 {
- #clock-cells = <1>;
- compatible = "allwinner,sun6i-a31-pll6-clk";
- reg = <0x01c20028 0x4>;
- clocks = <&osc24M>;
- clock-output-names = "pll6", "pll6x2";
- };
-
- cpu: cpu_clk@01c20050 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-cpu-clk";
- reg = <0x01c20050 0x4>;
-
- /*
- * PLL1 is listed twice here.
- * While it looks suspicious, it's actually documented
- * that way both in the datasheet and in the code from
- * Allwinner.
- */
- clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
- clock-output-names = "cpu";
- };
-
axi: axi_clk@01c20050 {
#clock-cells = <0>;
compatible = "allwinner,sun8i-a23-axi-clk";
@@ -168,22 +85,6 @@
clock-output-names = "axi";
};
- ahb1: ahb1_clk@01c20054 {
- #clock-cells = <0>;
- compatible = "allwinner,sun6i-a31-ahb1-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
- clock-output-names = "ahb1";
- };
-
- apb1: apb1_clk@01c20054 {
- #clock-cells = <0>;
- compatible = "allwinner,sun4i-a10-apb0-clk";
- reg = <0x01c20054 0x4>;
- clocks = <&ahb1>;
- clock-output-names = "apb1";
- };
-
ahb1_gates: clk@01c20060 {
#clock-cells = <1>;
compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
@@ -228,36 +129,6 @@
"apb2_uart3", "apb2_uart4";
};
- mmc0_clk: clk@01c20088 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-mmc-clk";
- reg = <0x01c20088 0x4>;
- clocks = <&osc24M>, <&pll6 0>;
- clock-output-names = "mmc0",
- "mmc0_output",
- "mmc0_sample";
- };
-
- mmc1_clk: clk@01c2008c {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-mmc-clk";
- reg = <0x01c2008c 0x4>;
- clocks = <&osc24M>, <&pll6 0>;
- clock-output-names = "mmc1",
- "mmc1_output",
- "mmc1_sample";
- };
-
- mmc2_clk: clk@01c20090 {
- #clock-cells = <1>;
- compatible = "allwinner,sun4i-a10-mmc-clk";
- reg = <0x01c20090 0x4>;
- clocks = <&osc24M>, <&pll6 0>;
- clock-output-names = "mmc2",
- "mmc2_output",
- "mmc2_sample";
- };
-
mbus_clk: clk@01c2015c {
#clock-cells = <0>;
compatible = "allwinner,sun8i-a23-mbus-clk";
@@ -268,11 +139,6 @@
};
soc@01c00000 {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
dma: dma-controller@01c02000 {
compatible = "allwinner,sun8i-a23-dma";
reg = <0x01c02000 0x1000>;
@@ -282,75 +148,12 @@
#dma-cells = <1>;
};
- mmc0: mmc@01c0f000 {
- compatible = "allwinner,sun5i-a13-mmc";
- reg = <0x01c0f000 0x1000>;
- clocks = <&ahb1_gates 8>,
- <&mmc0_clk 0>,
- <&mmc0_clk 1>,
- <&mmc0_clk 2>;
- clock-names = "ahb",
- "mmc",
- "output",
- "sample";
- resets = <&ahb1_rst 8>;
- reset-names = "ahb";
- interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- mmc1: mmc@01c10000 {
- compatible = "allwinner,sun5i-a13-mmc";
- reg = <0x01c10000 0x1000>;
- clocks = <&ahb1_gates 9>,
- <&mmc1_clk 0>,
- <&mmc1_clk 1>,
- <&mmc1_clk 2>;
- clock-names = "ahb",
- "mmc",
- "output",
- "sample";
- resets = <&ahb1_rst 9>;
- reset-names = "ahb";
- interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- mmc2: mmc@01c11000 {
- compatible = "allwinner,sun5i-a13-mmc";
- reg = <0x01c11000 0x1000>;
- clocks = <&ahb1_gates 10>,
- <&mmc2_clk 0>,
- <&mmc2_clk 1>,
- <&mmc2_clk 2>;
- clock-names = "ahb",
- "mmc",
- "output",
- "sample";
- resets = <&ahb1_rst 10>;
- reset-names = "ahb";
- interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
pio: pinctrl@01c20800 {
compatible = "allwinner,sun8i-a23-pinctrl";
- reg = <0x01c20800 0x400>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb1_gates 5>;
- gpio-controller;
- interrupt-controller;
- #address-cells = <1>;
- #size-cells = <0>;
- #gpio-cells = <3>;
+
uart0_pins_a: uart0@0 {
allwinner,pins = "PF2", "PF4";
@@ -359,20 +162,6 @@
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
- mmc0_pins_a: mmc0@0 {
- allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
- allwinner,function = "mmc0";
- allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- mmc1_pins_a: mmc1@0 {
- allwinner,pins = "PG0","PG1","PG2","PG3","PG4","PG5";
- allwinner,function = "mmc1";
- allwinner,drive = <SUN4I_PINCTRL_30_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
i2c0_pins_a: i2c0@0 {
allwinner,pins = "PH2", "PH3";
allwinner,function = "i2c0";
@@ -395,38 +184,6 @@
};
};
- ahb1_rst: reset@01c202c0 {
- #reset-cells = <1>;
- compatible = "allwinner,sun6i-a31-clock-reset";
- reg = <0x01c202c0 0xc>;
- };
-
- apb1_rst: reset@01c202d0 {
- #reset-cells = <1>;
- compatible = "allwinner,sun6i-a31-clock-reset";
- reg = <0x01c202d0 0x4>;
- };
-
- apb2_rst: reset@01c202d8 {
- #reset-cells = <1>;
- compatible = "allwinner,sun6i-a31-clock-reset";
- reg = <0x01c202d8 0x4>;
- };
-
- timer@01c20c00 {
- compatible = "allwinner,sun4i-a10-timer";
- reg = <0x01c20c00 0xa0>;
- interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&osc24M>;
- };
-
- wdt0: watchdog@01c20ca0 {
- compatible = "allwinner,sun6i-a31-wdt";
- reg = <0x01c20ca0 0x20>;
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- };
-
lradc: lradc@01c22800 {
compatible = "allwinner,sun4i-a10-lradc-keys";
reg = <0x01c22800 0x100>;
@@ -434,58 +191,6 @@
status = "disabled";
};
- uart0: serial@01c28000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x01c28000 0x400>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&apb2_gates 16>;
- resets = <&apb2_rst 16>;
- dmas = <&dma 6>, <&dma 6>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- uart1: serial@01c28400 {
- compatible = "snps,dw-apb-uart";
- reg = <0x01c28400 0x400>;
- interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&apb2_gates 17>;
- resets = <&apb2_rst 17>;
- dmas = <&dma 7>, <&dma 7>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- uart2: serial@01c28800 {
- compatible = "snps,dw-apb-uart";
- reg = <0x01c28800 0x400>;
- interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&apb2_gates 18>;
- resets = <&apb2_rst 18>;
- dmas = <&dma 8>, <&dma 8>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- uart3: serial@01c28c00 {
- compatible = "snps,dw-apb-uart";
- reg = <0x01c28c00 0x400>;
- interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&apb2_gates 19>;
- resets = <&apb2_rst 19>;
- dmas = <&dma 9>, <&dma 9>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
uart4: serial@01c29000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c29000 0x400>;
@@ -498,136 +203,5 @@
dma-names = "rx", "tx";
status = "disabled";
};
-
- i2c0: i2c@01c2ac00 {
- compatible = "allwinner,sun6i-a31-i2c";
- reg = <0x01c2ac00 0x400>;
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb2_gates 0>;
- resets = <&apb2_rst 0>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- i2c1: i2c@01c2b000 {
- compatible = "allwinner,sun6i-a31-i2c";
- reg = <0x01c2b000 0x400>;
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb2_gates 1>;
- resets = <&apb2_rst 1>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- i2c2: i2c@01c2b400 {
- compatible = "allwinner,sun6i-a31-i2c";
- reg = <0x01c2b400 0x400>;
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb2_gates 2>;
- resets = <&apb2_rst 2>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- gic: interrupt-controller@01c81000 {
- compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
- reg = <0x01c81000 0x1000>,
- <0x01c82000 0x1000>,
- <0x01c84000 0x2000>,
- <0x01c86000 0x2000>;
- interrupt-controller;
- #interrupt-cells = <3>;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
- };
-
- rtc: rtc@01f00000 {
- compatible = "allwinner,sun6i-a31-rtc";
- reg = <0x01f00000 0x54>;
- interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- prcm@01f01400 {
- compatible = "allwinner,sun8i-a23-prcm";
- reg = <0x01f01400 0x200>;
-
- ar100: ar100_clk {
- compatible = "fixed-factor-clock";
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&osc24M>;
- clock-output-names = "ar100";
- };
-
- ahb0: ahb0_clk {
- compatible = "fixed-factor-clock";
- #clock-cells = <0>;
- clock-div = <1>;
- clock-mult = <1>;
- clocks = <&ar100>;
- clock-output-names = "ahb0";
- };
-
- apb0: apb0_clk {
- compatible = "allwinner,sun8i-a23-apb0-clk";
- #clock-cells = <0>;
- clocks = <&ahb0>;
- clock-output-names = "apb0";
- };
-
- apb0_gates: apb0_gates_clk {
- compatible = "allwinner,sun8i-a23-apb0-gates-clk";
- #clock-cells = <1>;
- clocks = <&apb0>;
- clock-output-names = "apb0_pio", "apb0_timer",
- "apb0_rsb", "apb0_uart",
- "apb0_i2c";
- };
-
- apb0_rst: apb0_rst {
- compatible = "allwinner,sun6i-a31-clock-reset";
- #reset-cells = <1>;
- };
- };
-
- cpucfg@01f01c00 {
- compatible = "allwinner,sun8i-a23-cpuconfig";
- reg = <0x01f01c00 0x300>;
- };
-
- r_uart: serial@01f02800 {
- compatible = "snps,dw-apb-uart";
- reg = <0x01f02800 0x400>;
- interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&apb0_gates 4>;
- resets = <&apb0_rst 4>;
- status = "disabled";
- };
-
- r_pio: pinctrl@01f02c00 {
- compatible = "allwinner,sun8i-a23-r-pinctrl";
- reg = <0x01f02c00 0x400>;
- interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb0_gates 0>;
- resets = <&apb0_rst 0>;
- gpio-controller;
- interrupt-controller;
- #address-cells = <1>;
- #size-cells = <0>;
- #gpio-cells = <3>;
-
- r_uart_pins_a: r_uart@0 {
- allwinner,pins = "PL2", "PL3";
- allwinner,function = "s_uart";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
- };
};
};
diff --git a/arch/arm/boot/dts/sun8i.dtsi b/arch/arm/boot/dts/sun8i.dtsi
new file mode 100644
index 0000000..cf481e5
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i.dtsi
@@ -0,0 +1,481 @@
+/*
+ * Copyright 2014 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "skeleton.dtsi"
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ interrupt-parent = <&gic>;
+
+ chosen {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ framebuffer@0 {
+ compatible = "allwinner,simple-framebuffer",
+ "simple-framebuffer";
+ allwinner,pipeline = "de_be0-lcd0";
+ clocks = <&pll6 0>;
+ status = "disabled";
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ clock-frequency = <24000000>;
+ arm,cpu-registers-not-fw-configured;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ osc24M: osc24M_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "osc24M";
+ };
+
+ osc32k: osc32k_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "osc32k";
+ };
+
+ pll1: clk@01c20000 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun8i-a23-pll1-clk";
+ reg = <0x01c20000 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll1";
+ };
+
+ pll6: clk@01c20028 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun6i-a31-pll6-clk";
+ reg = <0x01c20028 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll6", "pll6x2";
+ };
+
+ cpu: cpu_clk@01c20050 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-cpu-clk";
+ reg = <0x01c20050 0x4>;
+
+ /*
+ * PLL1 is listed twice here.
+ * While it looks suspicious, it's actually documented
+ * that way both in the datasheet and in the code from
+ * Allwinner.
+ */
+ clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
+ clock-output-names = "cpu";
+ };
+
+
+ ahb1: ahb1_clk@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun6i-a31-ahb1-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
+ clock-output-names = "ahb1";
+ };
+
+ apb1: apb1_clk@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-apb0-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&ahb1>;
+ clock-output-names = "apb1";
+ };
+
+ mmc0_clk: clk@01c20088 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-mmc-clk";
+ reg = <0x01c20088 0x4>;
+ clocks = <&osc24M>, <&pll6 0>;
+ clock-output-names = "mmc0",
+ "mmc0_output",
+ "mmc0_sample";
+ };
+
+ mmc1_clk: clk@01c2008c {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-mmc-clk";
+ reg = <0x01c2008c 0x4>;
+ clocks = <&osc24M>, <&pll6 0>;
+ clock-output-names = "mmc1",
+ "mmc1_output",
+ "mmc1_sample";
+ };
+
+ mmc2_clk: clk@01c20090 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-mmc-clk";
+ reg = <0x01c20090 0x4>;
+ clocks = <&osc24M>, <&pll6 0>;
+ clock-output-names = "mmc2",
+ "mmc2_output",
+ "mmc2_sample";
+ };
+
+ };
+
+ soc@01c00000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+
+ mmc0: mmc@01c0f000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c0f000 0x1000>;
+ clocks = <&ahb1_gates 8>,
+ <&mmc0_clk 0>,
+ <&mmc0_clk 1>,
+ <&mmc0_clk 2>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ resets = <&ahb1_rst 8>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc1: mmc@01c10000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c10000 0x1000>;
+ clocks = <&ahb1_gates 9>,
+ <&mmc1_clk 0>,
+ <&mmc1_clk 1>,
+ <&mmc1_clk 2>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ resets = <&ahb1_rst 9>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc2: mmc@01c11000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c11000 0x1000>;
+ clocks = <&ahb1_gates 10>,
+ <&mmc2_clk 0>,
+ <&mmc2_clk 1>,
+ <&mmc2_clk 2>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ resets = <&ahb1_rst 10>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ pio: pinctrl@01c20800 {
+ reg = <0x01c20800 0x400>;
+ clocks = <&apb1_gates 5>;
+ gpio-controller;
+ interrupt-controller;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #gpio-cells = <3>;
+
+ mmc0_pins_a: mmc0@0 {
+ allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
+ allwinner,function = "mmc0";
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ mmc1_pins_a: mmc1@0 {
+ allwinner,pins = "PG0","PG1","PG2","PG3","PG4","PG5";
+ allwinner,function = "mmc1";
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+ };
+
+ ahb1_rst: reset@01c202c0 {
+ #reset-cells = <1>;
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ reg = <0x01c202c0 0xc>;
+ };
+
+ apb1_rst: reset@01c202d0 {
+ #reset-cells = <1>;
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ reg = <0x01c202d0 0x4>;
+ };
+
+ apb2_rst: reset@01c202d8 {
+ #reset-cells = <1>;
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ reg = <0x01c202d8 0x4>;
+ };
+
+ timer@01c20c00 {
+ compatible = "allwinner,sun4i-a10-timer";
+ reg = <0x01c20c00 0xa0>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc24M>;
+ };
+
+ wdt0: watchdog@01c20ca0 {
+ compatible = "allwinner,sun6i-a31-wdt";
+ reg = <0x01c20ca0 0x20>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ uart0: serial@01c28000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28000 0x400>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb2_gates 16>;
+ resets = <&apb2_rst 16>;
+ dmas = <&dma 6>, <&dma 6>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart1: serial@01c28400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28400 0x400>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb2_gates 17>;
+ resets = <&apb2_rst 17>;
+ dmas = <&dma 7>, <&dma 7>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart2: serial@01c28800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28800 0x400>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb2_gates 18>;
+ resets = <&apb2_rst 18>;
+ dmas = <&dma 8>, <&dma 8>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart3: serial@01c28c00 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28c00 0x400>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb2_gates 19>;
+ resets = <&apb2_rst 19>;
+ dmas = <&dma 9>, <&dma 9>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2c0: i2c@01c2ac00 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2ac00 0x400>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apb2_gates 0>;
+ resets = <&apb2_rst 0>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1: i2c@01c2b000 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2b000 0x400>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apb2_gates 1>;
+ resets = <&apb2_rst 1>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c2: i2c@01c2b400 {
+ compatible = "allwinner,sun6i-a31-i2c";
+ reg = <0x01c2b400 0x400>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apb2_gates 2>;
+ resets = <&apb2_rst 2>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ gic: interrupt-controller@01c81000 {
+ compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+ reg = <0x01c81000 0x1000>,
+ <0x01c82000 0x1000>,
+ <0x01c84000 0x2000>,
+ <0x01c86000 0x2000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ rtc: rtc@01f00000 {
+ compatible = "allwinner,sun6i-a31-rtc";
+ reg = <0x01f00000 0x54>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ prcm@01f01400 {
+ compatible = "allwinner,sun8i-a23-prcm";
+ reg = <0x01f01400 0x200>;
+
+ ar100: ar100_clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clocks = <&osc24M>;
+ clock-output-names = "ar100";
+ };
+
+ ahb0: ahb0_clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clocks = <&ar100>;
+ clock-output-names = "ahb0";
+ };
+
+ apb0: apb0_clk {
+ compatible = "allwinner,sun8i-a23-apb0-clk";
+ #clock-cells = <0>;
+ clocks = <&ahb0>;
+ clock-output-names = "apb0";
+ };
+
+ apb0_gates: apb0_gates_clk {
+ compatible = "allwinner,sun8i-a23-apb0-gates-clk";
+ #clock-cells = <1>;
+ clocks = <&apb0>;
+ clock-output-names = "apb0_pio", "apb0_timer",
+ "apb0_rsb", "apb0_uart",
+ "apb0_i2c";
+ };
+
+ apb0_rst: apb0_rst {
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ #reset-cells = <1>;
+ };
+ };
+
+ cpucfg@01f01c00 {
+ compatible = "allwinner,sun8i-a23-cpuconfig";
+ reg = <0x01f01c00 0x300>;
+ };
+
+ r_uart: serial@01f02800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01f02800 0x400>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb0_gates 4>;
+ resets = <&apb0_rst 4>;
+ status = "disabled";
+ };
+
+ r_pio: pinctrl@01f02c00 {
+ compatible = "allwinner,sun8i-a23-r-pinctrl";
+ reg = <0x01f02c00 0x400>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apb0_gates 0>;
+ resets = <&apb0_rst 0>;
+ gpio-controller;
+ interrupt-controller;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #gpio-cells = <3>;
+
+ r_uart_pins_a: r_uart@0 {
+ allwinner,pins = "PL2", "PL3";
+ allwinner,function = "s_uart";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+ };
+ };
+};
--
1.9.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 5/6] ARM: dts: sunxi: Add Allwinner A33 DTSI
2015-05-10 6:46 [PATCH 0/6] Introduce Allwinner A33 support Vishnu Patekar
` (3 preceding siblings ...)
2015-05-10 6:46 ` [PATCH 4/6] ARM: dts: sunxi: add common sun8i dtsi Vishnu Patekar
@ 2015-05-10 6:46 ` Vishnu Patekar
2015-05-10 8:53 ` Hans de Goede
2015-05-10 10:43 ` Maxime Ripard
2015-05-10 6:46 ` [PATCH 6/6] ARM: dts: sun8i: Add ET-Q8 A33 support Vishnu Patekar
2015-05-12 11:37 ` [PATCH 0/6] Introduce Allwinner " Linus Walleij
6 siblings, 2 replies; 30+ messages in thread
From: Vishnu Patekar @ 2015-05-10 6:46 UTC (permalink / raw)
To: maxime.ripard, emilio, linus.walleij, robh+dt
Cc: hdegoede, wens, jenskuske, arnd, linux-arm-kernel, linux-kernel,
linux-sunxi, devicetree, Vishnu Patekar
this is based on common sun8i.dtsi patch.
sun8i-a23.dtsi and sun8i-a33.dtsi are same, A33 specific features
e.g. clocks can be added in future.
Signed-off-by: VishnuPatekar <vishnupatekar0510@gmail.com>
---
arch/arm/boot/dts/sun8i-a33.dtsi | 217 +++++++++++++++++++++++++++++++++++++++
1 file changed, 217 insertions(+)
create mode 100644 arch/arm/boot/dts/sun8i-a33.dtsi
diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi
new file mode 100644
index 0000000..32489fc
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-a33.dtsi
@@ -0,0 +1,217 @@
+/*
+ * Copyright 2014 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "sun8i.dtsi"
+
+/ {
+ cpus {
+ enable-method = "allwinner,sun8i";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0>;
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <1>;
+ };
+
+ cpu@2 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <2>;
+ };
+
+ cpu@3 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <3>;
+ };
+ };
+
+ memory {
+ reg = <0x40000000 0x80000000>;
+ };
+
+ clocks {
+ /* dummy clock until actually implemented */
+ pll5: pll5_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ clock-output-names = "pll5";
+ };
+
+ axi: axi_clk@01c20050 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun8i-a23-axi-clk";
+ reg = <0x01c20050 0x4>;
+ clocks = <&cpu>;
+ clock-output-names = "axi";
+ };
+
+ ahb1_gates: clk@01c20060 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
+ reg = <0x01c20060 0x8>;
+ clocks = <&ahb1>;
+ clock-output-names = "ahb1_mipidsi", "ahb1_dma",
+ "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
+ "ahb1_nand", "ahb1_sdram",
+ "ahb1_hstimer", "ahb1_spi0",
+ "ahb1_spi1", "ahb1_otg", "ahb1_ehci",
+ "ahb1_ohci", "ahb1_ve", "ahb1_lcd",
+ "ahb1_csi", "ahb1_be", "ahb1_fe",
+ "ahb1_gpu", "ahb1_spinlock",
+ "ahb1_drc";
+ };
+
+ apb1_gates: clk@01c20068 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun8i-a23-apb1-gates-clk";
+ reg = <0x01c20068 0x4>;
+ clocks = <&apb1>;
+ clock-output-names = "apb1_codec", "apb1_pio",
+ "apb1_daudio0", "apb1_daudio1";
+ };
+
+ apb2: clk@01c20058 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-apb1-clk";
+ reg = <0x01c20058 0x4>;
+ clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
+ clock-output-names = "apb2";
+ };
+
+ apb2_gates: clk@01c2006c {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun8i-a23-apb2-gates-clk";
+ reg = <0x01c2006c 0x4>;
+ clocks = <&apb2>;
+ clock-output-names = "apb2_i2c0", "apb2_i2c1",
+ "apb2_i2c2", "apb2_uart0",
+ "apb2_uart1", "apb2_uart2",
+ "apb2_uart3", "apb2_uart4";
+ };
+
+ mbus_clk: clk@01c2015c {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun8i-a23-mbus-clk";
+ reg = <0x01c2015c 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5>;
+ clock-output-names = "mbus";
+ };
+ };
+
+ soc@01c00000 {
+ dma: dma-controller@01c02000 {
+ compatible = "allwinner,sun8i-a23-dma";
+ reg = <0x01c02000 0x1000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ahb1_gates 6>;
+ resets = <&ahb1_rst 6>;
+ #dma-cells = <1>;
+ };
+
+ pio: pinctrl@01c20800 {
+ compatible = "allwinner,sun8i-a33-pinctrl";
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+
+ uart0_pins_a: uart0@0 {
+ allwinner,pins = "PF2", "PF4";
+ allwinner,function = "uart0";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ i2c0_pins_a: i2c0@0 {
+ allwinner,pins = "PH2", "PH3";
+ allwinner,function = "i2c0";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ i2c1_pins_a: i2c1@0 {
+ allwinner,pins = "PH4", "PH5";
+ allwinner,function = "i2c1";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ i2c2_pins_a: i2c2@0 {
+ allwinner,pins = "PE12", "PE13";
+ allwinner,function = "i2c2";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+ };
+
+ lradc: lradc@01c22800 {
+ compatible = "allwinner,sun4i-a10-lradc-keys";
+ reg = <0x01c22800 0x100>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart4: serial@01c29000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c29000 0x400>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb2_gates 20>;
+ resets = <&apb2_rst 20>;
+ dmas = <&dma 10>, <&dma 10>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+ };
+};
--
1.9.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 6/6] ARM: dts: sun8i: Add ET-Q8 A33 support
2015-05-10 6:46 [PATCH 0/6] Introduce Allwinner A33 support Vishnu Patekar
` (4 preceding siblings ...)
2015-05-10 6:46 ` [PATCH 5/6] ARM: dts: sunxi: Add Allwinner A33 DTSI Vishnu Patekar
@ 2015-05-10 6:46 ` Vishnu Patekar
2015-05-10 8:54 ` Hans de Goede
2015-05-10 10:47 ` Maxime Ripard
2015-05-12 11:37 ` [PATCH 0/6] Introduce Allwinner " Linus Walleij
6 siblings, 2 replies; 30+ messages in thread
From: Vishnu Patekar @ 2015-05-10 6:46 UTC (permalink / raw)
To: maxime.ripard, emilio, linus.walleij, robh+dt
Cc: hdegoede, wens, jenskuske, arnd, linux-arm-kernel, linux-kernel,
linux-sunxi, devicetree, Vishnu Patekar
ET-Q8_A33 is A33 based cheap tablet in common Q8 format.
It has 512MB RAM, 4GB Nand, 7" Display, RDA5900P wifi, GSL1680 touch, etc.
Signed-off-by: VishnuPatekar <vishnupatekar0510@gmail.com>
---
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/sun8i-a33-et-q8.dts | 108 ++++++++++++++++++++++++++++++++++
2 files changed, 110 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/sun8i-a33-et-q8.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 82f4b9b..d44b1d6 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -570,7 +570,8 @@ dtb-$(CONFIG_MACH_SUN7I) += \
sun7i-a20-wexler-tab7200.dtb
dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-a23-ippo-q8h-v5.dtb \
- sun8i-a23-ippo-q8h-v1.2.dtb
+ sun8i-a23-ippo-q8h-v1.2.dtb \
+ sun8i-a33-et-q8.dtb
dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
sun9i-a80-cubieboard4.dtb
diff --git a/arch/arm/boot/dts/sun8i-a33-et-q8.dts b/arch/arm/boot/dts/sun8i-a33-et-q8.dts
new file mode 100644
index 0000000..260d5a3
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-a33-et-q8.dts
@@ -0,0 +1,108 @@
+/*
+ * Copyright 2015 Vishnu Patekar
+ * Vishnu Patekar <vishnupatekar0510@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a33.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "ET Q8 A33 ";
+ compatible = "et-q8-q33", "allwinner,sun8i", "allwinner,sun8i-a33";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ bootargs = "earlyprintk console=ttyS0,115200";
+ };
+};
+
+&lradc {
+ vref-supply = <®_vcc3v0>;
+ status = "okay";
+
+ button@200 {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ channel = <0>;
+ voltage = <200000>;
+ };
+
+ button@400 {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ channel = <0>;
+ voltage = <400000>;
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ /* pull-ups and devices require PMIC regulator */
+ status = "failed";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
--
1.9.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* Re: [PATCH 1/6] ARM: sunxi: Add Machine support for A33
2015-05-10 6:46 ` [PATCH 1/6] ARM: sunxi: Add Machine support for A33 Vishnu Patekar
@ 2015-05-10 8:49 ` Hans de Goede
2015-05-10 10:33 ` Maxime Ripard
1 sibling, 0 replies; 30+ messages in thread
From: Hans de Goede @ 2015-05-10 8:49 UTC (permalink / raw)
To: Vishnu Patekar, maxime.ripard, emilio, linus.walleij, robh+dt
Cc: wens, jenskuske, arnd, linux-arm-kernel, linux-kernel,
linux-sunxi, devicetree
Hi,
On 10-05-15 08:46, Vishnu Patekar wrote:
> Allwinnner A33 quad core cortex-a7 based SOC.
> It is similar to A23.
>
> Renamed cpu method to "allwinner,sun8i" for common sun8i smp.
> smp code is generic for A23, A33 and hopefully H3.
>
> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
> ---
> Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
> arch/arm/mach-sunxi/Kconfig | 2 +-
> arch/arm/mach-sunxi/platsmp.c | 2 +-
> arch/arm/mach-sunxi/sunxi.c | 4 ++--
> 4 files changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
> index 42941fd..e32f082 100644
> --- a/Documentation/devicetree/bindings/arm/sunxi.txt
> +++ b/Documentation/devicetree/bindings/arm/sunxi.txt
> @@ -9,4 +9,5 @@ using one of the following compatible strings:
> allwinner,sun6i-a31
> allwinner,sun7i-a20
> allwinner,sun8i-a23
> + allwinner,sun8i-a33
> allwinner,sun9i-a80
> diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
> index 81502b9..38bedd8 100644
> --- a/arch/arm/mach-sunxi/Kconfig
> +++ b/arch/arm/mach-sunxi/Kconfig
> @@ -35,7 +35,7 @@ config MACH_SUN7I
> select SUN5I_HSTIMER
>
> config MACH_SUN8I
> - bool "Allwinner A23 (sun8i) SoCs support"
> + bool "Allwinner (sun8i) SoCs support"
> default ARCH_SUNXI
> select ARM_GIC
> select MFD_SUN6I_PRCM
> diff --git a/arch/arm/mach-sunxi/platsmp.c b/arch/arm/mach-sunxi/platsmp.c
> index e8483ec..c56b501 100644
> --- a/arch/arm/mach-sunxi/platsmp.c
> +++ b/arch/arm/mach-sunxi/platsmp.c
> @@ -189,4 +189,4 @@ struct smp_operations sun8i_smp_ops __initdata = {
> .smp_prepare_cpus = sun8i_smp_prepare_cpus,
> .smp_boot_secondary = sun8i_smp_boot_secondary,
> };
> -CPU_METHOD_OF_DECLARE(sun8i_a23_smp, "allwinner,sun8i-a23", &sun8i_smp_ops);
> +CPU_METHOD_OF_DECLARE(sun8i_smp, "allwinner,sun8i", &sun8i_smp_ops);
> diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
> index 1bc811a..8937d0d 100644
> --- a/arch/arm/mach-sunxi/sunxi.c
> +++ b/arch/arm/mach-sunxi/sunxi.c
> @@ -66,11 +66,11 @@ DT_MACHINE_START(SUN7I_DT, "Allwinner sun7i (A20) Family")
> MACHINE_END
>
> static const char * const sun8i_board_dt_compat[] = {
> - "allwinner,sun8i-a23",
> + "allwinner,sun8i",
> NULL,
> };
This is wrong it should be:
static const char * const sun8i_board_dt_compat[] = {
"allwinner,sun8i-a23",
"allwinner,sun8i-a33",
NULL,
};
To match what you've said it will be in Documentation/devicetree/bindings/arm/sunxi.txt
(which is correct).
Otherwise this patch looks good, thanks for your work on this.
Regards,
Hans
>
> -DT_MACHINE_START(SUN8I_DT, "Allwinner sun8i (A23) Family")
> +DT_MACHINE_START(SUN8I_DT, "Allwinner sun8i Family")
> .dt_compat = sun8i_board_dt_compat,
> .init_late = sunxi_dt_cpufreq_init,
> MACHINE_END
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 2/6] pinctrl: sunxi: add allwinner A33 PIO controller support
2015-05-10 6:46 ` [PATCH 2/6] pinctrl: sunxi: add allwinner A33 PIO controller support Vishnu Patekar
@ 2015-05-10 8:50 ` Hans de Goede
2015-05-10 9:00 ` Chen-Yu Tsai
2015-05-10 10:34 ` Maxime Ripard
2015-05-11 7:22 ` Paul Bolle
2 siblings, 1 reply; 30+ messages in thread
From: Hans de Goede @ 2015-05-10 8:50 UTC (permalink / raw)
To: Vishnu Patekar, maxime.ripard, emilio, linus.walleij, robh+dt
Cc: wens, jenskuske, arnd, linux-arm-kernel, linux-kernel,
linux-sunxi, devicetree
Hi,
On 10-05-15 08:46, Vishnu Patekar wrote:
> A33 PIO has 7 ports which starts from PB and has two interrupt ports.
>
> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Is this patch really necessary at all? The A33 is a pin compatible drop in
for the A23, I would expect things to work just fine using the A23 pinmux code
for the A33. and also the a23 pinctrl compatibles.
Regards,
Hans
> ---
> .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 2 +
> drivers/pinctrl/sunxi/Kconfig | 5 +
> drivers/pinctrl/sunxi/Makefile | 1 +
> drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c | 513 +++++++++++++++++++++
> 4 files changed, 521 insertions(+)
> create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> index fdd8046..9462ab7 100644
> --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> @@ -16,6 +16,8 @@ Required properties:
> "allwinner,sun7i-a20-pinctrl"
> "allwinner,sun8i-a23-pinctrl"
> "allwinner,sun8i-a23-r-pinctrl"
> + "allwinner,sun8i-a33-pinctrl"
> +
> - reg: Should contain the register physical address and length for the
> pin controller.
>
> diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
> index 2eb893e..dd83aab 100644
> --- a/drivers/pinctrl/sunxi/Kconfig
> +++ b/drivers/pinctrl/sunxi/Kconfig
> @@ -38,6 +38,11 @@ config PINCTRL_SUN8I_A23
> def_bool MACH_SUN8I
> select PINCTRL_SUNXI_COMMON
>
> +
> +config PINCTRL_SUN8I_A33
> + def_bool MACH_SUN8I
> + select PINCTRL_SUNXI_COMMON
> +
> config PINCTRL_SUN8I_A23_R
> def_bool MACH_SUN8I
> depends on RESET_CONTROLLER
> diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
> index b796d57..227a121 100644
> --- a/drivers/pinctrl/sunxi/Makefile
> +++ b/drivers/pinctrl/sunxi/Makefile
> @@ -11,4 +11,5 @@ obj-$(CONFIG_PINCTRL_SUN6I_A31_R) += pinctrl-sun6i-a31-r.o
> obj-$(CONFIG_PINCTRL_SUN7I_A20) += pinctrl-sun7i-a20.o
> obj-$(CONFIG_PINCTRL_SUN8I_A23) += pinctrl-sun8i-a23.o
> obj-$(CONFIG_PINCTRL_SUN8I_A23_R) += pinctrl-sun8i-a23-r.o
> +obj-$(CONFIG_PINCTRL_SUN8I_A33) += pinctrl-sun8i-a33.o
> obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
> new file mode 100644
> index 0000000..00265f0
> --- /dev/null
> +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
> @@ -0,0 +1,513 @@
> +/*
> + * Allwinner a33 SoCs pinctrl driver.
> + *
> + * Copyright (C) 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
> + *
> + * Based on pinctrl-sun8i-a23.c, which is:
> + * Copyright (C) 2014 Chen-Yu Tsai <wens@csie.org>
> + * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/pinctrl/pinctrl.h>
> +
> +#include "pinctrl-sunxi.h"
> +
> +static const struct sunxi_desc_pin sun8i_a33_pins[] = {
> + /* Hole */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "uart2"), /* TX */
> + SUNXI_FUNCTION(0x3, "uart0"), /* TX */
> + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 0)), /* PB_EINT0 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "uart2"), /* RX */
> + SUNXI_FUNCTION(0x3, "uart0"), /* RX */
> + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 1)), /* PB_EINT1 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
> + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 2)), /* PB_EINT2 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
> + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 3)), /* PB_EINT3 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2s0"), /* SYNC */
> + SUNXI_FUNCTION(0x3, "aif2"), /* SYNC */
> + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 4)), /* PB_EINT4 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */
> + SUNXI_FUNCTION(0x3, "aif2"), /* BCLK */
> + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 5)), /* PB_EINT5 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2s0"), /* DOUT */
> + SUNXI_FUNCTION(0x3, "aif2"), /* DOUT */
> + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 6)), /* PB_EINT6 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2s0"), /* DIN */
> + SUNXI_FUNCTION(0x3, "aif2"), /* DIN */
> + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 7)), /* PB_EINT7 */
> + /* Hole */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* WE */
> + SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
> + SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
> + SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */
> + SUNXI_FUNCTION(0x3, "spi0")), /* CS */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* RE */
> + SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
> + SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
> + SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
> + SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
> + SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
> + SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
> + SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
> + SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand"), /* DQ6 */
> + SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand"), /* DQ7 */
> + SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand"), /* DQS */
> + SUNXI_FUNCTION(0x3, "mmc2")), /* RST */
> + /* Hole */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
> + SUNXI_FUNCTION(0x3, "mmc1")), /* CLK */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
> + SUNXI_FUNCTION(0x3, "mmc1")), /* CMD */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
> + SUNXI_FUNCTION(0x3, "mmc1")), /* D0 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
> + SUNXI_FUNCTION(0x3, "mmc1")), /* D1 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
> + SUNXI_FUNCTION(0x3, "mmc1")), /* D2 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
> + SUNXI_FUNCTION(0x3, "mmc1")), /* D3 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
> + SUNXI_FUNCTION(0x3, "uart1")), /* TX */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
> + SUNXI_FUNCTION(0x3, "uart1")), /* RX */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
> + SUNXI_FUNCTION(0x3, "uart1")), /* RTS */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
> + SUNXI_FUNCTION(0x3, "uart1")), /* CTS */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
> + SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
> + SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
> + SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
> + SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
> + SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
> + SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
> + SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
> + SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
> + SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
> + SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */
> + /* Hole */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "csi")), /* PCLK */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "csi")), /* MCLK */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "csi")), /* HSYNC */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "csi")), /* VSYNC */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "csi")), /* D0 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "csi")), /* D1 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "csi")), /* D2 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "csi")), /* D3 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "csi")), /* D4 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "csi")), /* D5 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "csi")), /* D6 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "csi")), /* D7 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "csi"), /* SCK */
> + SUNXI_FUNCTION(0x3, "i2c2")), /* SCK */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "csi"), /* SDA */
> + SUNXI_FUNCTION(0x3, "i2c2")), /* SDA */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out")),
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out")),
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out")),
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out")),
> + /* Hole */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
> + SUNXI_FUNCTION(0x3, "jtag")), /* MS1 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
> + SUNXI_FUNCTION(0x3, "jtag")), /* DI1 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
> + SUNXI_FUNCTION(0x3, "uart0")), /* TX */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
> + SUNXI_FUNCTION(0x3, "jtag")), /* DO1 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
> + SUNXI_FUNCTION(0x3, "uart0")), /* RX */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
> + SUNXI_FUNCTION(0x3, "jtag")), /* CK1 */
> + /* Hole */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
> + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 0)), /* PG_EINT0 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
> + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 1)), /* PG_EINT1 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
> + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 2)), /* PG_EINT2 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
> + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 3)), /* PG_EINT3 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
> + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 4)), /* PG_EINT4 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
> + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 5)), /* PG_EINT5 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "uart1"), /* TX */
> + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 6)), /* PG_EINT6 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "uart1"), /* RX */
> + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 7)), /* PG_EINT7 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
> + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 8)), /* PG_EINT8 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
> + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 9)), /* PG_EINT9 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2s1"), /* SYNC */
> + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 10)), /* PG_EINT10 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2s1"), /* CLK */
> + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 11)), /* PG_EINT11 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2s1"), /* DOUT */
> + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 12)), /* PG_EINT12 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2s1"), /* DIN */
> + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 13)), /* PG_EINT13 */
> + /* Hole */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "pwm0")),
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "pwm1")),
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "spi0"), /* CS */
> + SUNXI_FUNCTION(0x3, "uart3")), /* TX */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
> + SUNXI_FUNCTION(0x3, "uart3")), /* RX */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "spi0"), /* DOUT */
> + SUNXI_FUNCTION(0x3, "uart3")), /* RTS */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "spi0"), /* DIN */
> + SUNXI_FUNCTION(0x3, "uart3")), /* CTS */
> +};
> +
> +static const struct sunxi_pinctrl_desc sun8i_a33_pinctrl_data = {
> + .pins = sun8i_a33_pins,
> + .npins = ARRAY_SIZE(sun8i_a33_pins),
> + .irq_banks = 2,
> +};
> +
> +static int sun8i_a33_pinctrl_probe(struct platform_device *pdev)
> +{
> + return sunxi_pinctrl_init(pdev,
> + &sun8i_a33_pinctrl_data);
> +}
> +
> +static const struct of_device_id sun8i_a33_pinctrl_match[] = {
> + { .compatible = "allwinner,sun8i-a33-pinctrl", },
> + {}
> +};
> +MODULE_DEVICE_TABLE(of, sun8i_a33_pinctrl_match);
> +
> +static struct platform_driver sun8i_a33_pinctrl_driver = {
> + .probe = sun8i_a33_pinctrl_probe,
> + .driver = {
> + .name = "sun8i-a33-pinctrl",
> + .of_match_table = sun8i_a33_pinctrl_match,
> + },
> +};
> +module_platform_driver(sun8i_a33_pinctrl_driver);
> +
> +MODULE_AUTHOR("Vishnu Patekar <vishnupatekar0510@gmail.com>");
> +MODULE_DESCRIPTION("Allwinner a33 pinctrl driver");
> +MODULE_LICENSE("GPL");
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 4/6] ARM: dts: sunxi: add common sun8i dtsi
2015-05-10 6:46 ` [PATCH 4/6] ARM: dts: sunxi: add common sun8i dtsi Vishnu Patekar
@ 2015-05-10 8:52 ` Hans de Goede
2015-05-10 10:41 ` Maxime Ripard
1 sibling, 0 replies; 30+ messages in thread
From: Hans de Goede @ 2015-05-10 8:52 UTC (permalink / raw)
To: Vishnu Patekar, maxime.ripard, emilio, linus.walleij, robh+dt
Cc: wens, jenskuske, arnd, linux-arm-kernel, linux-kernel,
linux-sunxi, devicetree
Hi,
On 10-05-15 08:46, Vishnu Patekar wrote:
> added the common sun8i.dtsi and "allwinner,sun8i" compatible for common
> sun8i features, I've referred the h3 dtsi by Jens Kuske.
> accordingly modified the sun8i-a23.dtsi and a23 dts.
>
> I don't have a23 device, however, dts got compiled.
>
> Signed-off-by: VishnuPatekar <vishnupatekar0510@gmail.com>
Please edit ~/.gitconfig and add:
[diff]
renames = copies
And then resend this patch to make it easier to review what is
actually changing.
Thanks,
Hans
> ---
> arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts | 6 +-
> arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts | 6 +-
> arch/arm/boot/dts/sun8i-a23.dtsi | 432 +----------------------
> arch/arm/boot/dts/sun8i.dtsi | 481 ++++++++++++++++++++++++++
> 4 files changed, 486 insertions(+), 439 deletions(-)
> create mode 100644 arch/arm/boot/dts/sun8i.dtsi
>
> diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts
> index dd31c53..b3f19e7 100644
> --- a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts
> +++ b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts
> @@ -16,10 +16,6 @@
> * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> * GNU General Public License for more details.
> *
> - * You should have received a copy of the GNU General Public
> - * License along with this file; if not, write to the Free
> - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
> - * MA 02110-1301 USA
> *
> * Or, alternatively,
> *
> @@ -55,5 +51,5 @@
>
> / {
> model = "Ippo Q8H Dual Core Tablet (v1.2)";
> - compatible = "ippo,q8h-v1.2", "allwinner,sun8i-a23";
> + compatible = "ippo,q8h-v1.2", "allwinner,sun8i", "allwinner,sun8i-a23";
> };
> diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
> index f5658d1..5db4010 100644
> --- a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
> +++ b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
> @@ -18,10 +18,6 @@
> * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> * GNU General Public License for more details.
> *
> - * You should have received a copy of the GNU General Public
> - * License along with this file; if not, write to the Free
> - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
> - * MA 02110-1301 USA
> *
> * Or, alternatively,
> *
> @@ -57,7 +53,7 @@
>
> / {
> model = "Ippo Q8H Dual Core Tablet (v5)";
> - compatible = "ippo,q8h-v5", "allwinner,sun8i-a23";
> + compatible = "ippo,q8h-v5", "allwinner,sun8i", "allwinner,sun8i-a23";
>
> aliases {
> serial0 = &r_uart;
> diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi
> index 6d6eda3..c17be9e 100644
> --- a/arch/arm/boot/dts/sun8i-a23.dtsi
> +++ b/arch/arm/boot/dts/sun8i-a23.dtsi
> @@ -18,10 +18,6 @@
> * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> * GNU General Public License for more details.
> *
> - * You should have received a copy of the GNU General Public
> - * License along with this file; if not, write to the Free
> - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
> - * MA 02110-1301 USA
> *
> * Or, alternatively,
> *
> @@ -47,41 +43,11 @@
> * OTHER DEALINGS IN THE SOFTWARE.
> */
>
> -#include "skeleton.dtsi"
> -
> -#include <dt-bindings/interrupt-controller/arm-gic.h>
> -
> -#include <dt-bindings/pinctrl/sun4i-a10.h>
> +#include "sun8i.dtsi"
>
> / {
> - interrupt-parent = <&gic>;
> -
> - chosen {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - ranges;
> -
> - framebuffer@0 {
> - compatible = "allwinner,simple-framebuffer",
> - "simple-framebuffer";
> - allwinner,pipeline = "de_be0-lcd0";
> - clocks = <&pll6 0>;
> - status = "disabled";
> - };
> - };
> -
> - timer {
> - compatible = "arm,armv7-timer";
> - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> - clock-frequency = <24000000>;
> - arm,cpu-registers-not-fw-configured;
> - };
> -
> cpus {
> - enable-method = "allwinner,sun8i-a23";
> + enable-method = "allwinner,sun8i";
> #address-cells = <1>;
> #size-cells = <0>;
>
> @@ -103,32 +69,6 @@
> };
>
> clocks {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - ranges;
> -
> - osc24M: osc24M_clk {
> - #clock-cells = <0>;
> - compatible = "fixed-clock";
> - clock-frequency = <24000000>;
> - clock-output-names = "osc24M";
> - };
> -
> - osc32k: osc32k_clk {
> - #clock-cells = <0>;
> - compatible = "fixed-clock";
> - clock-frequency = <32768>;
> - clock-output-names = "osc32k";
> - };
> -
> - pll1: clk@01c20000 {
> - #clock-cells = <0>;
> - compatible = "allwinner,sun8i-a23-pll1-clk";
> - reg = <0x01c20000 0x4>;
> - clocks = <&osc24M>;
> - clock-output-names = "pll1";
> - };
> -
> /* dummy clock until actually implemented */
> pll5: pll5_clk {
> #clock-cells = <0>;
> @@ -137,29 +77,6 @@
> clock-output-names = "pll5";
> };
>
> - pll6: clk@01c20028 {
> - #clock-cells = <1>;
> - compatible = "allwinner,sun6i-a31-pll6-clk";
> - reg = <0x01c20028 0x4>;
> - clocks = <&osc24M>;
> - clock-output-names = "pll6", "pll6x2";
> - };
> -
> - cpu: cpu_clk@01c20050 {
> - #clock-cells = <0>;
> - compatible = "allwinner,sun4i-a10-cpu-clk";
> - reg = <0x01c20050 0x4>;
> -
> - /*
> - * PLL1 is listed twice here.
> - * While it looks suspicious, it's actually documented
> - * that way both in the datasheet and in the code from
> - * Allwinner.
> - */
> - clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
> - clock-output-names = "cpu";
> - };
> -
> axi: axi_clk@01c20050 {
> #clock-cells = <0>;
> compatible = "allwinner,sun8i-a23-axi-clk";
> @@ -168,22 +85,6 @@
> clock-output-names = "axi";
> };
>
> - ahb1: ahb1_clk@01c20054 {
> - #clock-cells = <0>;
> - compatible = "allwinner,sun6i-a31-ahb1-clk";
> - reg = <0x01c20054 0x4>;
> - clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
> - clock-output-names = "ahb1";
> - };
> -
> - apb1: apb1_clk@01c20054 {
> - #clock-cells = <0>;
> - compatible = "allwinner,sun4i-a10-apb0-clk";
> - reg = <0x01c20054 0x4>;
> - clocks = <&ahb1>;
> - clock-output-names = "apb1";
> - };
> -
> ahb1_gates: clk@01c20060 {
> #clock-cells = <1>;
> compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
> @@ -228,36 +129,6 @@
> "apb2_uart3", "apb2_uart4";
> };
>
> - mmc0_clk: clk@01c20088 {
> - #clock-cells = <1>;
> - compatible = "allwinner,sun4i-a10-mmc-clk";
> - reg = <0x01c20088 0x4>;
> - clocks = <&osc24M>, <&pll6 0>;
> - clock-output-names = "mmc0",
> - "mmc0_output",
> - "mmc0_sample";
> - };
> -
> - mmc1_clk: clk@01c2008c {
> - #clock-cells = <1>;
> - compatible = "allwinner,sun4i-a10-mmc-clk";
> - reg = <0x01c2008c 0x4>;
> - clocks = <&osc24M>, <&pll6 0>;
> - clock-output-names = "mmc1",
> - "mmc1_output",
> - "mmc1_sample";
> - };
> -
> - mmc2_clk: clk@01c20090 {
> - #clock-cells = <1>;
> - compatible = "allwinner,sun4i-a10-mmc-clk";
> - reg = <0x01c20090 0x4>;
> - clocks = <&osc24M>, <&pll6 0>;
> - clock-output-names = "mmc2",
> - "mmc2_output",
> - "mmc2_sample";
> - };
> -
> mbus_clk: clk@01c2015c {
> #clock-cells = <0>;
> compatible = "allwinner,sun8i-a23-mbus-clk";
> @@ -268,11 +139,6 @@
> };
>
> soc@01c00000 {
> - compatible = "simple-bus";
> - #address-cells = <1>;
> - #size-cells = <1>;
> - ranges;
> -
> dma: dma-controller@01c02000 {
> compatible = "allwinner,sun8i-a23-dma";
> reg = <0x01c02000 0x1000>;
> @@ -282,75 +148,12 @@
> #dma-cells = <1>;
> };
>
> - mmc0: mmc@01c0f000 {
> - compatible = "allwinner,sun5i-a13-mmc";
> - reg = <0x01c0f000 0x1000>;
> - clocks = <&ahb1_gates 8>,
> - <&mmc0_clk 0>,
> - <&mmc0_clk 1>,
> - <&mmc0_clk 2>;
> - clock-names = "ahb",
> - "mmc",
> - "output",
> - "sample";
> - resets = <&ahb1_rst 8>;
> - reset-names = "ahb";
> - interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
> - status = "disabled";
> - #address-cells = <1>;
> - #size-cells = <0>;
> - };
> -
> - mmc1: mmc@01c10000 {
> - compatible = "allwinner,sun5i-a13-mmc";
> - reg = <0x01c10000 0x1000>;
> - clocks = <&ahb1_gates 9>,
> - <&mmc1_clk 0>,
> - <&mmc1_clk 1>,
> - <&mmc1_clk 2>;
> - clock-names = "ahb",
> - "mmc",
> - "output",
> - "sample";
> - resets = <&ahb1_rst 9>;
> - reset-names = "ahb";
> - interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
> - status = "disabled";
> - #address-cells = <1>;
> - #size-cells = <0>;
> - };
> -
> - mmc2: mmc@01c11000 {
> - compatible = "allwinner,sun5i-a13-mmc";
> - reg = <0x01c11000 0x1000>;
> - clocks = <&ahb1_gates 10>,
> - <&mmc2_clk 0>,
> - <&mmc2_clk 1>,
> - <&mmc2_clk 2>;
> - clock-names = "ahb",
> - "mmc",
> - "output",
> - "sample";
> - resets = <&ahb1_rst 10>;
> - reset-names = "ahb";
> - interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
> - status = "disabled";
> - #address-cells = <1>;
> - #size-cells = <0>;
> - };
> -
> pio: pinctrl@01c20800 {
> compatible = "allwinner,sun8i-a23-pinctrl";
> - reg = <0x01c20800 0x400>;
> interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&apb1_gates 5>;
> - gpio-controller;
> - interrupt-controller;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - #gpio-cells = <3>;
> +
>
> uart0_pins_a: uart0@0 {
> allwinner,pins = "PF2", "PF4";
> @@ -359,20 +162,6 @@
> allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> };
>
> - mmc0_pins_a: mmc0@0 {
> - allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
> - allwinner,function = "mmc0";
> - allwinner,drive = <SUN4I_PINCTRL_30_MA>;
> - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> - };
> -
> - mmc1_pins_a: mmc1@0 {
> - allwinner,pins = "PG0","PG1","PG2","PG3","PG4","PG5";
> - allwinner,function = "mmc1";
> - allwinner,drive = <SUN4I_PINCTRL_30_MA>;
> - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> - };
> -
> i2c0_pins_a: i2c0@0 {
> allwinner,pins = "PH2", "PH3";
> allwinner,function = "i2c0";
> @@ -395,38 +184,6 @@
> };
> };
>
> - ahb1_rst: reset@01c202c0 {
> - #reset-cells = <1>;
> - compatible = "allwinner,sun6i-a31-clock-reset";
> - reg = <0x01c202c0 0xc>;
> - };
> -
> - apb1_rst: reset@01c202d0 {
> - #reset-cells = <1>;
> - compatible = "allwinner,sun6i-a31-clock-reset";
> - reg = <0x01c202d0 0x4>;
> - };
> -
> - apb2_rst: reset@01c202d8 {
> - #reset-cells = <1>;
> - compatible = "allwinner,sun6i-a31-clock-reset";
> - reg = <0x01c202d8 0x4>;
> - };
> -
> - timer@01c20c00 {
> - compatible = "allwinner,sun4i-a10-timer";
> - reg = <0x01c20c00 0xa0>;
> - interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&osc24M>;
> - };
> -
> - wdt0: watchdog@01c20ca0 {
> - compatible = "allwinner,sun6i-a31-wdt";
> - reg = <0x01c20ca0 0x20>;
> - interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
> - };
> -
> lradc: lradc@01c22800 {
> compatible = "allwinner,sun4i-a10-lradc-keys";
> reg = <0x01c22800 0x100>;
> @@ -434,58 +191,6 @@
> status = "disabled";
> };
>
> - uart0: serial@01c28000 {
> - compatible = "snps,dw-apb-uart";
> - reg = <0x01c28000 0x400>;
> - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> - reg-shift = <2>;
> - reg-io-width = <4>;
> - clocks = <&apb2_gates 16>;
> - resets = <&apb2_rst 16>;
> - dmas = <&dma 6>, <&dma 6>;
> - dma-names = "rx", "tx";
> - status = "disabled";
> - };
> -
> - uart1: serial@01c28400 {
> - compatible = "snps,dw-apb-uart";
> - reg = <0x01c28400 0x400>;
> - interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
> - reg-shift = <2>;
> - reg-io-width = <4>;
> - clocks = <&apb2_gates 17>;
> - resets = <&apb2_rst 17>;
> - dmas = <&dma 7>, <&dma 7>;
> - dma-names = "rx", "tx";
> - status = "disabled";
> - };
> -
> - uart2: serial@01c28800 {
> - compatible = "snps,dw-apb-uart";
> - reg = <0x01c28800 0x400>;
> - interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
> - reg-shift = <2>;
> - reg-io-width = <4>;
> - clocks = <&apb2_gates 18>;
> - resets = <&apb2_rst 18>;
> - dmas = <&dma 8>, <&dma 8>;
> - dma-names = "rx", "tx";
> - status = "disabled";
> - };
> -
> - uart3: serial@01c28c00 {
> - compatible = "snps,dw-apb-uart";
> - reg = <0x01c28c00 0x400>;
> - interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> - reg-shift = <2>;
> - reg-io-width = <4>;
> - clocks = <&apb2_gates 19>;
> - resets = <&apb2_rst 19>;
> - dmas = <&dma 9>, <&dma 9>;
> - dma-names = "rx", "tx";
> - status = "disabled";
> - };
> -
> uart4: serial@01c29000 {
> compatible = "snps,dw-apb-uart";
> reg = <0x01c29000 0x400>;
> @@ -498,136 +203,5 @@
> dma-names = "rx", "tx";
> status = "disabled";
> };
> -
> - i2c0: i2c@01c2ac00 {
> - compatible = "allwinner,sun6i-a31-i2c";
> - reg = <0x01c2ac00 0x400>;
> - interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&apb2_gates 0>;
> - resets = <&apb2_rst 0>;
> - status = "disabled";
> - #address-cells = <1>;
> - #size-cells = <0>;
> - };
> -
> - i2c1: i2c@01c2b000 {
> - compatible = "allwinner,sun6i-a31-i2c";
> - reg = <0x01c2b000 0x400>;
> - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&apb2_gates 1>;
> - resets = <&apb2_rst 1>;
> - status = "disabled";
> - #address-cells = <1>;
> - #size-cells = <0>;
> - };
> -
> - i2c2: i2c@01c2b400 {
> - compatible = "allwinner,sun6i-a31-i2c";
> - reg = <0x01c2b400 0x400>;
> - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&apb2_gates 2>;
> - resets = <&apb2_rst 2>;
> - status = "disabled";
> - #address-cells = <1>;
> - #size-cells = <0>;
> - };
> -
> - gic: interrupt-controller@01c81000 {
> - compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
> - reg = <0x01c81000 0x1000>,
> - <0x01c82000 0x1000>,
> - <0x01c84000 0x2000>,
> - <0x01c86000 0x2000>;
> - interrupt-controller;
> - #interrupt-cells = <3>;
> - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> - };
> -
> - rtc: rtc@01f00000 {
> - compatible = "allwinner,sun6i-a31-rtc";
> - reg = <0x01f00000 0x54>;
> - interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> - };
> -
> - prcm@01f01400 {
> - compatible = "allwinner,sun8i-a23-prcm";
> - reg = <0x01f01400 0x200>;
> -
> - ar100: ar100_clk {
> - compatible = "fixed-factor-clock";
> - #clock-cells = <0>;
> - clock-div = <1>;
> - clock-mult = <1>;
> - clocks = <&osc24M>;
> - clock-output-names = "ar100";
> - };
> -
> - ahb0: ahb0_clk {
> - compatible = "fixed-factor-clock";
> - #clock-cells = <0>;
> - clock-div = <1>;
> - clock-mult = <1>;
> - clocks = <&ar100>;
> - clock-output-names = "ahb0";
> - };
> -
> - apb0: apb0_clk {
> - compatible = "allwinner,sun8i-a23-apb0-clk";
> - #clock-cells = <0>;
> - clocks = <&ahb0>;
> - clock-output-names = "apb0";
> - };
> -
> - apb0_gates: apb0_gates_clk {
> - compatible = "allwinner,sun8i-a23-apb0-gates-clk";
> - #clock-cells = <1>;
> - clocks = <&apb0>;
> - clock-output-names = "apb0_pio", "apb0_timer",
> - "apb0_rsb", "apb0_uart",
> - "apb0_i2c";
> - };
> -
> - apb0_rst: apb0_rst {
> - compatible = "allwinner,sun6i-a31-clock-reset";
> - #reset-cells = <1>;
> - };
> - };
> -
> - cpucfg@01f01c00 {
> - compatible = "allwinner,sun8i-a23-cpuconfig";
> - reg = <0x01f01c00 0x300>;
> - };
> -
> - r_uart: serial@01f02800 {
> - compatible = "snps,dw-apb-uart";
> - reg = <0x01f02800 0x400>;
> - interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
> - reg-shift = <2>;
> - reg-io-width = <4>;
> - clocks = <&apb0_gates 4>;
> - resets = <&apb0_rst 4>;
> - status = "disabled";
> - };
> -
> - r_pio: pinctrl@01f02c00 {
> - compatible = "allwinner,sun8i-a23-r-pinctrl";
> - reg = <0x01f02c00 0x400>;
> - interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&apb0_gates 0>;
> - resets = <&apb0_rst 0>;
> - gpio-controller;
> - interrupt-controller;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - #gpio-cells = <3>;
> -
> - r_uart_pins_a: r_uart@0 {
> - allwinner,pins = "PL2", "PL3";
> - allwinner,function = "s_uart";
> - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> - };
> - };
> };
> };
> diff --git a/arch/arm/boot/dts/sun8i.dtsi b/arch/arm/boot/dts/sun8i.dtsi
> new file mode 100644
> index 0000000..cf481e5
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun8i.dtsi
> @@ -0,0 +1,481 @@
> +/*
> + * Copyright 2014 Chen-Yu Tsai
> + *
> + * Chen-Yu Tsai <wens@csie.org>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + *
> + * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +#include "skeleton.dtsi"
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +#include <dt-bindings/pinctrl/sun4i-a10.h>
> +
> +/ {
> + interrupt-parent = <&gic>;
> +
> + chosen {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + framebuffer@0 {
> + compatible = "allwinner,simple-framebuffer",
> + "simple-framebuffer";
> + allwinner,pipeline = "de_be0-lcd0";
> + clocks = <&pll6 0>;
> + status = "disabled";
> + };
> + };
> +
> + timer {
> + compatible = "arm,armv7-timer";
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> + clock-frequency = <24000000>;
> + arm,cpu-registers-not-fw-configured;
> + };
> +
> + clocks {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + osc24M: osc24M_clk {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <24000000>;
> + clock-output-names = "osc24M";
> + };
> +
> + osc32k: osc32k_clk {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <32768>;
> + clock-output-names = "osc32k";
> + };
> +
> + pll1: clk@01c20000 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun8i-a23-pll1-clk";
> + reg = <0x01c20000 0x4>;
> + clocks = <&osc24M>;
> + clock-output-names = "pll1";
> + };
> +
> + pll6: clk@01c20028 {
> + #clock-cells = <1>;
> + compatible = "allwinner,sun6i-a31-pll6-clk";
> + reg = <0x01c20028 0x4>;
> + clocks = <&osc24M>;
> + clock-output-names = "pll6", "pll6x2";
> + };
> +
> + cpu: cpu_clk@01c20050 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-cpu-clk";
> + reg = <0x01c20050 0x4>;
> +
> + /*
> + * PLL1 is listed twice here.
> + * While it looks suspicious, it's actually documented
> + * that way both in the datasheet and in the code from
> + * Allwinner.
> + */
> + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
> + clock-output-names = "cpu";
> + };
> +
> +
> + ahb1: ahb1_clk@01c20054 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun6i-a31-ahb1-clk";
> + reg = <0x01c20054 0x4>;
> + clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
> + clock-output-names = "ahb1";
> + };
> +
> + apb1: apb1_clk@01c20054 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-apb0-clk";
> + reg = <0x01c20054 0x4>;
> + clocks = <&ahb1>;
> + clock-output-names = "apb1";
> + };
> +
> + mmc0_clk: clk@01c20088 {
> + #clock-cells = <1>;
> + compatible = "allwinner,sun4i-a10-mmc-clk";
> + reg = <0x01c20088 0x4>;
> + clocks = <&osc24M>, <&pll6 0>;
> + clock-output-names = "mmc0",
> + "mmc0_output",
> + "mmc0_sample";
> + };
> +
> + mmc1_clk: clk@01c2008c {
> + #clock-cells = <1>;
> + compatible = "allwinner,sun4i-a10-mmc-clk";
> + reg = <0x01c2008c 0x4>;
> + clocks = <&osc24M>, <&pll6 0>;
> + clock-output-names = "mmc1",
> + "mmc1_output",
> + "mmc1_sample";
> + };
> +
> + mmc2_clk: clk@01c20090 {
> + #clock-cells = <1>;
> + compatible = "allwinner,sun4i-a10-mmc-clk";
> + reg = <0x01c20090 0x4>;
> + clocks = <&osc24M>, <&pll6 0>;
> + clock-output-names = "mmc2",
> + "mmc2_output",
> + "mmc2_sample";
> + };
> +
> + };
> +
> + soc@01c00000 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> +
> + mmc0: mmc@01c0f000 {
> + compatible = "allwinner,sun5i-a13-mmc";
> + reg = <0x01c0f000 0x1000>;
> + clocks = <&ahb1_gates 8>,
> + <&mmc0_clk 0>,
> + <&mmc0_clk 1>,
> + <&mmc0_clk 2>;
> + clock-names = "ahb",
> + "mmc",
> + "output",
> + "sample";
> + resets = <&ahb1_rst 8>;
> + reset-names = "ahb";
> + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + mmc1: mmc@01c10000 {
> + compatible = "allwinner,sun5i-a13-mmc";
> + reg = <0x01c10000 0x1000>;
> + clocks = <&ahb1_gates 9>,
> + <&mmc1_clk 0>,
> + <&mmc1_clk 1>,
> + <&mmc1_clk 2>;
> + clock-names = "ahb",
> + "mmc",
> + "output",
> + "sample";
> + resets = <&ahb1_rst 9>;
> + reset-names = "ahb";
> + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + mmc2: mmc@01c11000 {
> + compatible = "allwinner,sun5i-a13-mmc";
> + reg = <0x01c11000 0x1000>;
> + clocks = <&ahb1_gates 10>,
> + <&mmc2_clk 0>,
> + <&mmc2_clk 1>,
> + <&mmc2_clk 2>;
> + clock-names = "ahb",
> + "mmc",
> + "output",
> + "sample";
> + resets = <&ahb1_rst 10>;
> + reset-names = "ahb";
> + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + pio: pinctrl@01c20800 {
> + reg = <0x01c20800 0x400>;
> + clocks = <&apb1_gates 5>;
> + gpio-controller;
> + interrupt-controller;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #gpio-cells = <3>;
> +
> + mmc0_pins_a: mmc0@0 {
> + allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
> + allwinner,function = "mmc0";
> + allwinner,drive = <SUN4I_PINCTRL_30_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> + mmc1_pins_a: mmc1@0 {
> + allwinner,pins = "PG0","PG1","PG2","PG3","PG4","PG5";
> + allwinner,function = "mmc1";
> + allwinner,drive = <SUN4I_PINCTRL_30_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> + };
> +
> + ahb1_rst: reset@01c202c0 {
> + #reset-cells = <1>;
> + compatible = "allwinner,sun6i-a31-clock-reset";
> + reg = <0x01c202c0 0xc>;
> + };
> +
> + apb1_rst: reset@01c202d0 {
> + #reset-cells = <1>;
> + compatible = "allwinner,sun6i-a31-clock-reset";
> + reg = <0x01c202d0 0x4>;
> + };
> +
> + apb2_rst: reset@01c202d8 {
> + #reset-cells = <1>;
> + compatible = "allwinner,sun6i-a31-clock-reset";
> + reg = <0x01c202d8 0x4>;
> + };
> +
> + timer@01c20c00 {
> + compatible = "allwinner,sun4i-a10-timer";
> + reg = <0x01c20c00 0xa0>;
> + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&osc24M>;
> + };
> +
> + wdt0: watchdog@01c20ca0 {
> + compatible = "allwinner,sun6i-a31-wdt";
> + reg = <0x01c20ca0 0x20>;
> + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + uart0: serial@01c28000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c28000 0x400>;
> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&apb2_gates 16>;
> + resets = <&apb2_rst 16>;
> + dmas = <&dma 6>, <&dma 6>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + uart1: serial@01c28400 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c28400 0x400>;
> + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&apb2_gates 17>;
> + resets = <&apb2_rst 17>;
> + dmas = <&dma 7>, <&dma 7>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + uart2: serial@01c28800 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c28800 0x400>;
> + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&apb2_gates 18>;
> + resets = <&apb2_rst 18>;
> + dmas = <&dma 8>, <&dma 8>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + uart3: serial@01c28c00 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c28c00 0x400>;
> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&apb2_gates 19>;
> + resets = <&apb2_rst 19>;
> + dmas = <&dma 9>, <&dma 9>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + i2c0: i2c@01c2ac00 {
> + compatible = "allwinner,sun6i-a31-i2c";
> + reg = <0x01c2ac00 0x400>;
> + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&apb2_gates 0>;
> + resets = <&apb2_rst 0>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c1: i2c@01c2b000 {
> + compatible = "allwinner,sun6i-a31-i2c";
> + reg = <0x01c2b000 0x400>;
> + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&apb2_gates 1>;
> + resets = <&apb2_rst 1>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c2: i2c@01c2b400 {
> + compatible = "allwinner,sun6i-a31-i2c";
> + reg = <0x01c2b400 0x400>;
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&apb2_gates 2>;
> + resets = <&apb2_rst 2>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + gic: interrupt-controller@01c81000 {
> + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
> + reg = <0x01c81000 0x1000>,
> + <0x01c82000 0x1000>,
> + <0x01c84000 0x2000>,
> + <0x01c86000 0x2000>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> + };
> +
> + rtc: rtc@01f00000 {
> + compatible = "allwinner,sun6i-a31-rtc";
> + reg = <0x01f00000 0x54>;
> + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + prcm@01f01400 {
> + compatible = "allwinner,sun8i-a23-prcm";
> + reg = <0x01f01400 0x200>;
> +
> + ar100: ar100_clk {
> + compatible = "fixed-factor-clock";
> + #clock-cells = <0>;
> + clock-div = <1>;
> + clock-mult = <1>;
> + clocks = <&osc24M>;
> + clock-output-names = "ar100";
> + };
> +
> + ahb0: ahb0_clk {
> + compatible = "fixed-factor-clock";
> + #clock-cells = <0>;
> + clock-div = <1>;
> + clock-mult = <1>;
> + clocks = <&ar100>;
> + clock-output-names = "ahb0";
> + };
> +
> + apb0: apb0_clk {
> + compatible = "allwinner,sun8i-a23-apb0-clk";
> + #clock-cells = <0>;
> + clocks = <&ahb0>;
> + clock-output-names = "apb0";
> + };
> +
> + apb0_gates: apb0_gates_clk {
> + compatible = "allwinner,sun8i-a23-apb0-gates-clk";
> + #clock-cells = <1>;
> + clocks = <&apb0>;
> + clock-output-names = "apb0_pio", "apb0_timer",
> + "apb0_rsb", "apb0_uart",
> + "apb0_i2c";
> + };
> +
> + apb0_rst: apb0_rst {
> + compatible = "allwinner,sun6i-a31-clock-reset";
> + #reset-cells = <1>;
> + };
> + };
> +
> + cpucfg@01f01c00 {
> + compatible = "allwinner,sun8i-a23-cpuconfig";
> + reg = <0x01f01c00 0x300>;
> + };
> +
> + r_uart: serial@01f02800 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01f02800 0x400>;
> + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&apb0_gates 4>;
> + resets = <&apb0_rst 4>;
> + status = "disabled";
> + };
> +
> + r_pio: pinctrl@01f02c00 {
> + compatible = "allwinner,sun8i-a23-r-pinctrl";
> + reg = <0x01f02c00 0x400>;
> + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&apb0_gates 0>;
> + resets = <&apb0_rst 0>;
> + gpio-controller;
> + interrupt-controller;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #gpio-cells = <3>;
> +
> + r_uart_pins_a: r_uart@0 {
> + allwinner,pins = "PL2", "PL3";
> + allwinner,function = "s_uart";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> + };
> + };
> +};
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner A33 DTSI
2015-05-10 6:46 ` [PATCH 5/6] ARM: dts: sunxi: Add Allwinner A33 DTSI Vishnu Patekar
@ 2015-05-10 8:53 ` Hans de Goede
2015-05-10 9:33 ` Vishnu Patekar
2015-05-10 10:43 ` Maxime Ripard
1 sibling, 1 reply; 30+ messages in thread
From: Hans de Goede @ 2015-05-10 8:53 UTC (permalink / raw)
To: Vishnu Patekar, maxime.ripard, emilio, linus.walleij, robh+dt
Cc: wens, jenskuske, arnd, linux-arm-kernel, linux-kernel,
linux-sunxi, devicetree
Hi,
On 10-05-15 08:46, Vishnu Patekar wrote:
> this is based on common sun8i.dtsi patch.
> sun8i-a23.dtsi and sun8i-a33.dtsi are same, A33 specific features
> e.g. clocks can be added in future.
>
> Signed-off-by: VishnuPatekar <vishnupatekar0510@gmail.com>
This seems to only contain stuff which can be shared with the a23 dts,
why is this not all in the common sun8i.dtsi ?
Regards,
Hans
> ---
> arch/arm/boot/dts/sun8i-a33.dtsi | 217 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 217 insertions(+)
> create mode 100644 arch/arm/boot/dts/sun8i-a33.dtsi
>
> diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi
> new file mode 100644
> index 0000000..32489fc
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun8i-a33.dtsi
> @@ -0,0 +1,217 @@
> +/*
> + * Copyright 2014 Chen-Yu Tsai
> + *
> + * Chen-Yu Tsai <wens@csie.org>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + *
> + * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +#include "sun8i.dtsi"
> +
> +/ {
> + cpus {
> + enable-method = "allwinner,sun8i";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + compatible = "arm,cortex-a7";
> + device_type = "cpu";
> + reg = <0>;
> + };
> +
> + cpu@1 {
> + compatible = "arm,cortex-a7";
> + device_type = "cpu";
> + reg = <1>;
> + };
> +
> + cpu@2 {
> + compatible = "arm,cortex-a7";
> + device_type = "cpu";
> + reg = <2>;
> + };
> +
> + cpu@3 {
> + compatible = "arm,cortex-a7";
> + device_type = "cpu";
> + reg = <3>;
> + };
> + };
> +
> + memory {
> + reg = <0x40000000 0x80000000>;
> + };
> +
> + clocks {
> + /* dummy clock until actually implemented */
> + pll5: pll5_clk {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <0>;
> + clock-output-names = "pll5";
> + };
> +
> + axi: axi_clk@01c20050 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun8i-a23-axi-clk";
> + reg = <0x01c20050 0x4>;
> + clocks = <&cpu>;
> + clock-output-names = "axi";
> + };
> +
> + ahb1_gates: clk@01c20060 {
> + #clock-cells = <1>;
> + compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
> + reg = <0x01c20060 0x8>;
> + clocks = <&ahb1>;
> + clock-output-names = "ahb1_mipidsi", "ahb1_dma",
> + "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
> + "ahb1_nand", "ahb1_sdram",
> + "ahb1_hstimer", "ahb1_spi0",
> + "ahb1_spi1", "ahb1_otg", "ahb1_ehci",
> + "ahb1_ohci", "ahb1_ve", "ahb1_lcd",
> + "ahb1_csi", "ahb1_be", "ahb1_fe",
> + "ahb1_gpu", "ahb1_spinlock",
> + "ahb1_drc";
> + };
> +
> + apb1_gates: clk@01c20068 {
> + #clock-cells = <1>;
> + compatible = "allwinner,sun8i-a23-apb1-gates-clk";
> + reg = <0x01c20068 0x4>;
> + clocks = <&apb1>;
> + clock-output-names = "apb1_codec", "apb1_pio",
> + "apb1_daudio0", "apb1_daudio1";
> + };
> +
> + apb2: clk@01c20058 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-apb1-clk";
> + reg = <0x01c20058 0x4>;
> + clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
> + clock-output-names = "apb2";
> + };
> +
> + apb2_gates: clk@01c2006c {
> + #clock-cells = <1>;
> + compatible = "allwinner,sun8i-a23-apb2-gates-clk";
> + reg = <0x01c2006c 0x4>;
> + clocks = <&apb2>;
> + clock-output-names = "apb2_i2c0", "apb2_i2c1",
> + "apb2_i2c2", "apb2_uart0",
> + "apb2_uart1", "apb2_uart2",
> + "apb2_uart3", "apb2_uart4";
> + };
> +
> + mbus_clk: clk@01c2015c {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun8i-a23-mbus-clk";
> + reg = <0x01c2015c 0x4>;
> + clocks = <&osc24M>, <&pll6 1>, <&pll5>;
> + clock-output-names = "mbus";
> + };
> + };
> +
> + soc@01c00000 {
> + dma: dma-controller@01c02000 {
> + compatible = "allwinner,sun8i-a23-dma";
> + reg = <0x01c02000 0x1000>;
> + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ahb1_gates 6>;
> + resets = <&ahb1_rst 6>;
> + #dma-cells = <1>;
> + };
> +
> + pio: pinctrl@01c20800 {
> + compatible = "allwinner,sun8i-a33-pinctrl";
> + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
> +
> + uart0_pins_a: uart0@0 {
> + allwinner,pins = "PF2", "PF4";
> + allwinner,function = "uart0";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> + i2c0_pins_a: i2c0@0 {
> + allwinner,pins = "PH2", "PH3";
> + allwinner,function = "i2c0";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> + i2c1_pins_a: i2c1@0 {
> + allwinner,pins = "PH4", "PH5";
> + allwinner,function = "i2c1";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> + i2c2_pins_a: i2c2@0 {
> + allwinner,pins = "PE12", "PE13";
> + allwinner,function = "i2c2";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> + };
> +
> + lradc: lradc@01c22800 {
> + compatible = "allwinner,sun4i-a10-lradc-keys";
> + reg = <0x01c22800 0x100>;
> + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + uart4: serial@01c29000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c29000 0x400>;
> + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&apb2_gates 20>;
> + resets = <&apb2_rst 20>;
> + dmas = <&dma 10>, <&dma 10>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> + };
> +};
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 6/6] ARM: dts: sun8i: Add ET-Q8 A33 support
2015-05-10 6:46 ` [PATCH 6/6] ARM: dts: sun8i: Add ET-Q8 A33 support Vishnu Patekar
@ 2015-05-10 8:54 ` Hans de Goede
2015-05-10 10:47 ` Maxime Ripard
1 sibling, 0 replies; 30+ messages in thread
From: Hans de Goede @ 2015-05-10 8:54 UTC (permalink / raw)
To: Vishnu Patekar, maxime.ripard, emilio, linus.walleij, robh+dt
Cc: wens, jenskuske, arnd, linux-arm-kernel, linux-kernel,
linux-sunxi, devicetree
Hi,
On 10-05-15 08:46, Vishnu Patekar wrote:
> ET-Q8_A33 is A33 based cheap tablet in common Q8 format.
>
> It has 512MB RAM, 4GB Nand, 7" Display, RDA5900P wifi, GSL1680 touch, etc.
Where does the ET prefix come from ? The ippo boards have an ippo prefix as
that is written on the pcb ...
Regards,
Hans
>
> Signed-off-by: VishnuPatekar <vishnupatekar0510@gmail.com>
> ---
> arch/arm/boot/dts/Makefile | 3 +-
> arch/arm/boot/dts/sun8i-a33-et-q8.dts | 108 ++++++++++++++++++++++++++++++++++
> 2 files changed, 110 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/boot/dts/sun8i-a33-et-q8.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 82f4b9b..d44b1d6 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -570,7 +570,8 @@ dtb-$(CONFIG_MACH_SUN7I) += \
> sun7i-a20-wexler-tab7200.dtb
> dtb-$(CONFIG_MACH_SUN8I) += \
> sun8i-a23-ippo-q8h-v5.dtb \
> - sun8i-a23-ippo-q8h-v1.2.dtb
> + sun8i-a23-ippo-q8h-v1.2.dtb \
> + sun8i-a33-et-q8.dtb
> dtb-$(CONFIG_MACH_SUN9I) += \
> sun9i-a80-optimus.dtb \
> sun9i-a80-cubieboard4.dtb
> diff --git a/arch/arm/boot/dts/sun8i-a33-et-q8.dts b/arch/arm/boot/dts/sun8i-a33-et-q8.dts
> new file mode 100644
> index 0000000..260d5a3
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun8i-a33-et-q8.dts
> @@ -0,0 +1,108 @@
> +/*
> + * Copyright 2015 Vishnu Patekar
> + * Vishnu Patekar <vishnupatekar0510@gmail.com>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + *
> + * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/dts-v1/;
> +#include "sun8i-a33.dtsi"
> +#include "sunxi-common-regulators.dtsi"
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/pinctrl/sun4i-a10.h>
> +
> +/ {
> + model = "ET Q8 A33 ";
> + compatible = "et-q8-q33", "allwinner,sun8i", "allwinner,sun8i-a33";
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + bootargs = "earlyprintk console=ttyS0,115200";
> + };
> +};
> +
> +&lradc {
> + vref-supply = <®_vcc3v0>;
> + status = "okay";
> +
> + button@200 {
> + label = "Volume Up";
> + linux,code = <KEY_VOLUMEUP>;
> + channel = <0>;
> + voltage = <200000>;
> + };
> +
> + button@400 {
> + label = "Volume Down";
> + linux,code = <KEY_VOLUMEDOWN>;
> + channel = <0>;
> + voltage = <400000>;
> + };
> +};
> +
> +&i2c0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c0_pins_a>;
> + status = "okay";
> +};
> +
> +&i2c1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c1_pins_a>;
> + status = "okay";
> +};
> +
> +&i2c2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c2_pins_a>;
> + /* pull-ups and devices require PMIC regulator */
> + status = "failed";
> +};
> +
> +&uart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_pins_a>;
> + status = "okay";
> +};
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 2/6] pinctrl: sunxi: add allwinner A33 PIO controller support
2015-05-10 8:50 ` Hans de Goede
@ 2015-05-10 9:00 ` Chen-Yu Tsai
2015-05-10 9:10 ` Hans de Goede
0 siblings, 1 reply; 30+ messages in thread
From: Chen-Yu Tsai @ 2015-05-10 9:00 UTC (permalink / raw)
To: Hans de Goede
Cc: Vishnu Patekar, Maxime Ripard, Emilio Lopez, Linus Walleij,
Rob Herring, Chen-Yu Tsai, Jens Kuske, Arnd Bergmann,
linux-arm-kernel, linux-kernel, linux-sunxi, devicetree
Hi,
On Sun, May 10, 2015 at 4:50 PM, Hans de Goede <hdegoede@redhat.com> wrote:
> Hi,
>
> On 10-05-15 08:46, Vishnu Patekar wrote:
>>
>> A33 PIO has 7 ports which starts from PB and has two interrupt ports.
>>
>> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
>
>
> Is this patch really necessary at all? The A33 is a pin compatible drop in
> for the A23, I would expect things to work just fine using the A23 pinmux
> code
> for the A33. and also the a23 pinctrl compatibles.
A33 has UART0 available on PB[01], which is quite nice.
Also EINT seems to be missing a group.
So "pin compatible" is mostly true. :)
ChenYu
> Regards,
>
> Hans
>
>
>> ---
>> .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 2 +
>> drivers/pinctrl/sunxi/Kconfig | 5 +
>> drivers/pinctrl/sunxi/Makefile | 1 +
>> drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c | 513
>> +++++++++++++++++++++
>> 4 files changed, 521 insertions(+)
>> create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
>>
>> diff --git
>> a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
>> b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
>> index fdd8046..9462ab7 100644
>> ---
>> a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
>> +++
>> b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
>> @@ -16,6 +16,8 @@ Required properties:
>> "allwinner,sun7i-a20-pinctrl"
>> "allwinner,sun8i-a23-pinctrl"
>> "allwinner,sun8i-a23-r-pinctrl"
>> + "allwinner,sun8i-a33-pinctrl"
>> +
>> - reg: Should contain the register physical address and length for the
>> pin controller.
>>
>> diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
>> index 2eb893e..dd83aab 100644
>> --- a/drivers/pinctrl/sunxi/Kconfig
>> +++ b/drivers/pinctrl/sunxi/Kconfig
>> @@ -38,6 +38,11 @@ config PINCTRL_SUN8I_A23
>> def_bool MACH_SUN8I
>> select PINCTRL_SUNXI_COMMON
>>
>> +
>> +config PINCTRL_SUN8I_A33
>> + def_bool MACH_SUN8I
>> + select PINCTRL_SUNXI_COMMON
>> +
>> config PINCTRL_SUN8I_A23_R
>> def_bool MACH_SUN8I
>> depends on RESET_CONTROLLER
>> diff --git a/drivers/pinctrl/sunxi/Makefile
>> b/drivers/pinctrl/sunxi/Makefile
>> index b796d57..227a121 100644
>> --- a/drivers/pinctrl/sunxi/Makefile
>> +++ b/drivers/pinctrl/sunxi/Makefile
>> @@ -11,4 +11,5 @@ obj-$(CONFIG_PINCTRL_SUN6I_A31_R) +=
>> pinctrl-sun6i-a31-r.o
>> obj-$(CONFIG_PINCTRL_SUN7I_A20) += pinctrl-sun7i-a20.o
>> obj-$(CONFIG_PINCTRL_SUN8I_A23) += pinctrl-sun8i-a23.o
>> obj-$(CONFIG_PINCTRL_SUN8I_A23_R) += pinctrl-sun8i-a23-r.o
>> +obj-$(CONFIG_PINCTRL_SUN8I_A33) += pinctrl-sun8i-a33.o
>> obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o
>> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
>> b/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
>> new file mode 100644
>> index 0000000..00265f0
>> --- /dev/null
>> +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
>> @@ -0,0 +1,513 @@
>> +/*
>> + * Allwinner a33 SoCs pinctrl driver.
>> + *
>> + * Copyright (C) 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
>> + *
>> + * Based on pinctrl-sun8i-a23.c, which is:
>> + * Copyright (C) 2014 Chen-Yu Tsai <wens@csie.org>
>> + * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com>
>> + *
>> + * This file is licensed under the terms of the GNU General Public
>> + * License version 2. This program is licensed "as is" without any
>> + * warranty of any kind, whether express or implied.
>> + */
>> +
>> +#include <linux/module.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/of.h>
>> +#include <linux/of_device.h>
>> +#include <linux/pinctrl/pinctrl.h>
>> +
>> +#include "pinctrl-sunxi.h"
>> +
>> +static const struct sunxi_desc_pin sun8i_a33_pins[] = {
>> + /* Hole */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "uart2"), /* TX */
>> + SUNXI_FUNCTION(0x3, "uart0"), /* TX */
>> + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 0)), /* PB_EINT0 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "uart2"), /* RX */
>> + SUNXI_FUNCTION(0x3, "uart0"), /* RX */
>> + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 1)), /* PB_EINT1 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
>> + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 2)), /* PB_EINT2 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
>> + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 3)), /* PB_EINT3 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "i2s0"), /* SYNC */
>> + SUNXI_FUNCTION(0x3, "aif2"), /* SYNC */
>> + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 4)), /* PB_EINT4 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */
>> + SUNXI_FUNCTION(0x3, "aif2"), /* BCLK */
>> + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 5)), /* PB_EINT5 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "i2s0"), /* DOUT */
>> + SUNXI_FUNCTION(0x3, "aif2"), /* DOUT */
>> + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 6)), /* PB_EINT6 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "i2s0"), /* DIN */
>> + SUNXI_FUNCTION(0x3, "aif2"), /* DIN */
>> + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 7)), /* PB_EINT7 */
>> + /* Hole */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0"), /* WE */
>> + SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
>> + SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
>> + SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */
>> + SUNXI_FUNCTION(0x3, "spi0")), /* CS */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0"), /* RE */
>> + SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
>> + SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
>> + SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
>> + SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
>> + SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
>> + SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
>> + SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
>> + SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand"), /* DQ6 */
>> + SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand"), /* DQ7 */
>> + SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "nand"), /* DQS */
>> + SUNXI_FUNCTION(0x3, "mmc2")), /* RST */
>> + /* Hole */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
>> + SUNXI_FUNCTION(0x3, "mmc1")), /* CLK */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
>> + SUNXI_FUNCTION(0x3, "mmc1")), /* CMD */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
>> + SUNXI_FUNCTION(0x3, "mmc1")), /* D0 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
>> + SUNXI_FUNCTION(0x3, "mmc1")), /* D1 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
>> + SUNXI_FUNCTION(0x3, "mmc1")), /* D2 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
>> + SUNXI_FUNCTION(0x3, "mmc1")), /* D3 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
>> + SUNXI_FUNCTION(0x3, "uart1")), /* TX */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
>> + SUNXI_FUNCTION(0x3, "uart1")), /* RX */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
>> + SUNXI_FUNCTION(0x3, "uart1")), /* RTS */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
>> + SUNXI_FUNCTION(0x3, "uart1")), /* CTS */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
>> + SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
>> + SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
>> + SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
>> + SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
>> + SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
>> + SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
>> + SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
>> + SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
>> + SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
>> + SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */
>> + /* Hole */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "csi")), /* PCLK */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "csi")), /* MCLK */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "csi")), /* HSYNC */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "csi")), /* VSYNC */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "csi")), /* D0 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "csi")), /* D1 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "csi")), /* D2 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "csi")), /* D3 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "csi")), /* D4 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "csi")), /* D5 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "csi")), /* D6 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "csi")), /* D7 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "csi"), /* SCK */
>> + SUNXI_FUNCTION(0x3, "i2c2")), /* SCK */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "csi"), /* SDA */
>> + SUNXI_FUNCTION(0x3, "i2c2")), /* SDA */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out")),
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out")),
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out")),
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out")),
>> + /* Hole */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
>> + SUNXI_FUNCTION(0x3, "jtag")), /* MS1 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
>> + SUNXI_FUNCTION(0x3, "jtag")), /* DI1 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
>> + SUNXI_FUNCTION(0x3, "uart0")), /* TX */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
>> + SUNXI_FUNCTION(0x3, "jtag")), /* DO1 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
>> + SUNXI_FUNCTION(0x3, "uart0")), /* RX */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
>> + SUNXI_FUNCTION(0x3, "jtag")), /* CK1 */
>> + /* Hole */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
>> + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 0)), /* PG_EINT0 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
>> + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 1)), /* PG_EINT1 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
>> + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 2)), /* PG_EINT2 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
>> + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 3)), /* PG_EINT3 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
>> + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 4)), /* PG_EINT4 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
>> + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 5)), /* PG_EINT5 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "uart1"), /* TX */
>> + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 6)), /* PG_EINT6 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "uart1"), /* RX */
>> + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 7)), /* PG_EINT7 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
>> + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 8)), /* PG_EINT8 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
>> + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 9)), /* PG_EINT9 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "i2s1"), /* SYNC */
>> + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 10)), /* PG_EINT10 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "i2s1"), /* CLK */
>> + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 11)), /* PG_EINT11 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "i2s1"), /* DOUT */
>> + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 12)), /* PG_EINT12 */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "i2s1"), /* DIN */
>> + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 13)), /* PG_EINT13 */
>> + /* Hole */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "pwm0")),
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "pwm1")),
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "spi0"), /* CS */
>> + SUNXI_FUNCTION(0x3, "uart3")), /* TX */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
>> + SUNXI_FUNCTION(0x3, "uart3")), /* RX */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "spi0"), /* DOUT */
>> + SUNXI_FUNCTION(0x3, "uart3")), /* RTS */
>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>> + SUNXI_FUNCTION(0x2, "spi0"), /* DIN */
>> + SUNXI_FUNCTION(0x3, "uart3")), /* CTS */
>> +};
>> +
>> +static const struct sunxi_pinctrl_desc sun8i_a33_pinctrl_data = {
>> + .pins = sun8i_a33_pins,
>> + .npins = ARRAY_SIZE(sun8i_a33_pins),
>> + .irq_banks = 2,
>> +};
>> +
>> +static int sun8i_a33_pinctrl_probe(struct platform_device *pdev)
>> +{
>> + return sunxi_pinctrl_init(pdev,
>> + &sun8i_a33_pinctrl_data);
>> +}
>> +
>> +static const struct of_device_id sun8i_a33_pinctrl_match[] = {
>> + { .compatible = "allwinner,sun8i-a33-pinctrl", },
>> + {}
>> +};
>> +MODULE_DEVICE_TABLE(of, sun8i_a33_pinctrl_match);
>> +
>> +static struct platform_driver sun8i_a33_pinctrl_driver = {
>> + .probe = sun8i_a33_pinctrl_probe,
>> + .driver = {
>> + .name = "sun8i-a33-pinctrl",
>> + .of_match_table = sun8i_a33_pinctrl_match,
>> + },
>> +};
>> +module_platform_driver(sun8i_a33_pinctrl_driver);
>> +
>> +MODULE_AUTHOR("Vishnu Patekar <vishnupatekar0510@gmail.com>");
>> +MODULE_DESCRIPTION("Allwinner a33 pinctrl driver");
>> +MODULE_LICENSE("GPL");
>>
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 2/6] pinctrl: sunxi: add allwinner A33 PIO controller support
2015-05-10 9:00 ` Chen-Yu Tsai
@ 2015-05-10 9:10 ` Hans de Goede
0 siblings, 0 replies; 30+ messages in thread
From: Hans de Goede @ 2015-05-10 9:10 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: Vishnu Patekar, Maxime Ripard, Emilio Lopez, Linus Walleij,
Rob Herring, Jens Kuske, Arnd Bergmann, linux-arm-kernel,
linux-kernel, linux-sunxi, devicetree
Hi,
On 10-05-15 11:00, Chen-Yu Tsai wrote:
> Hi,
>
> On Sun, May 10, 2015 at 4:50 PM, Hans de Goede <hdegoede@redhat.com> wrote:
>> Hi,
>>
>> On 10-05-15 08:46, Vishnu Patekar wrote:
>>>
>>> A33 PIO has 7 ports which starts from PB and has two interrupt ports.
>>>
>>> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
>>
>>
>> Is this patch really necessary at all? The A33 is a pin compatible drop in
>> for the A23, I would expect things to work just fine using the A23 pinmux
>> code
>> for the A33. and also the a23 pinctrl compatibles.
>
> A33 has UART0 available on PB[01], which is quite nice.
> Also EINT seems to be missing a group.
>
> So "pin compatible" is mostly true. :)
Ok, lets go with this patch then:
Acked-by: Hans de Goede <hdegoede@redhat.com>
Regards,
Hans
>
> ChenYu
>
>> Regards,
>>
>> Hans
>>
>>
>>> ---
>>> .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 2 +
>>> drivers/pinctrl/sunxi/Kconfig | 5 +
>>> drivers/pinctrl/sunxi/Makefile | 1 +
>>> drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c | 513
>>> +++++++++++++++++++++
>>> 4 files changed, 521 insertions(+)
>>> create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
>>>
>>> diff --git
>>> a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
>>> b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
>>> index fdd8046..9462ab7 100644
>>> ---
>>> a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
>>> +++
>>> b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
>>> @@ -16,6 +16,8 @@ Required properties:
>>> "allwinner,sun7i-a20-pinctrl"
>>> "allwinner,sun8i-a23-pinctrl"
>>> "allwinner,sun8i-a23-r-pinctrl"
>>> + "allwinner,sun8i-a33-pinctrl"
>>> +
>>> - reg: Should contain the register physical address and length for the
>>> pin controller.
>>>
>>> diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
>>> index 2eb893e..dd83aab 100644
>>> --- a/drivers/pinctrl/sunxi/Kconfig
>>> +++ b/drivers/pinctrl/sunxi/Kconfig
>>> @@ -38,6 +38,11 @@ config PINCTRL_SUN8I_A23
>>> def_bool MACH_SUN8I
>>> select PINCTRL_SUNXI_COMMON
>>>
>>> +
>>> +config PINCTRL_SUN8I_A33
>>> + def_bool MACH_SUN8I
>>> + select PINCTRL_SUNXI_COMMON
>>> +
>>> config PINCTRL_SUN8I_A23_R
>>> def_bool MACH_SUN8I
>>> depends on RESET_CONTROLLER
>>> diff --git a/drivers/pinctrl/sunxi/Makefile
>>> b/drivers/pinctrl/sunxi/Makefile
>>> index b796d57..227a121 100644
>>> --- a/drivers/pinctrl/sunxi/Makefile
>>> +++ b/drivers/pinctrl/sunxi/Makefile
>>> @@ -11,4 +11,5 @@ obj-$(CONFIG_PINCTRL_SUN6I_A31_R) +=
>>> pinctrl-sun6i-a31-r.o
>>> obj-$(CONFIG_PINCTRL_SUN7I_A20) += pinctrl-sun7i-a20.o
>>> obj-$(CONFIG_PINCTRL_SUN8I_A23) += pinctrl-sun8i-a23.o
>>> obj-$(CONFIG_PINCTRL_SUN8I_A23_R) += pinctrl-sun8i-a23-r.o
>>> +obj-$(CONFIG_PINCTRL_SUN8I_A33) += pinctrl-sun8i-a33.o
>>> obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o
>>> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
>>> b/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
>>> new file mode 100644
>>> index 0000000..00265f0
>>> --- /dev/null
>>> +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
>>> @@ -0,0 +1,513 @@
>>> +/*
>>> + * Allwinner a33 SoCs pinctrl driver.
>>> + *
>>> + * Copyright (C) 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
>>> + *
>>> + * Based on pinctrl-sun8i-a23.c, which is:
>>> + * Copyright (C) 2014 Chen-Yu Tsai <wens@csie.org>
>>> + * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com>
>>> + *
>>> + * This file is licensed under the terms of the GNU General Public
>>> + * License version 2. This program is licensed "as is" without any
>>> + * warranty of any kind, whether express or implied.
>>> + */
>>> +
>>> +#include <linux/module.h>
>>> +#include <linux/platform_device.h>
>>> +#include <linux/of.h>
>>> +#include <linux/of_device.h>
>>> +#include <linux/pinctrl/pinctrl.h>
>>> +
>>> +#include "pinctrl-sunxi.h"
>>> +
>>> +static const struct sunxi_desc_pin sun8i_a33_pins[] = {
>>> + /* Hole */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "uart2"), /* TX */
>>> + SUNXI_FUNCTION(0x3, "uart0"), /* TX */
>>> + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 0)), /* PB_EINT0 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "uart2"), /* RX */
>>> + SUNXI_FUNCTION(0x3, "uart0"), /* RX */
>>> + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 1)), /* PB_EINT1 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
>>> + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 2)), /* PB_EINT2 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
>>> + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 3)), /* PB_EINT3 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "i2s0"), /* SYNC */
>>> + SUNXI_FUNCTION(0x3, "aif2"), /* SYNC */
>>> + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 4)), /* PB_EINT4 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */
>>> + SUNXI_FUNCTION(0x3, "aif2"), /* BCLK */
>>> + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 5)), /* PB_EINT5 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "i2s0"), /* DOUT */
>>> + SUNXI_FUNCTION(0x3, "aif2"), /* DOUT */
>>> + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 6)), /* PB_EINT6 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "i2s0"), /* DIN */
>>> + SUNXI_FUNCTION(0x3, "aif2"), /* DIN */
>>> + SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 7)), /* PB_EINT7 */
>>> + /* Hole */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "nand0"), /* WE */
>>> + SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
>>> + SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
>>> + SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */
>>> + SUNXI_FUNCTION(0x3, "spi0")), /* CS */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "nand0")), /* CE0 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "nand0"), /* RE */
>>> + SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
>>> + SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
>>> + SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
>>> + SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
>>> + SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
>>> + SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
>>> + SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
>>> + SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "nand"), /* DQ6 */
>>> + SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "nand"), /* DQ7 */
>>> + SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "nand"), /* DQS */
>>> + SUNXI_FUNCTION(0x3, "mmc2")), /* RST */
>>> + /* Hole */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
>>> + SUNXI_FUNCTION(0x3, "mmc1")), /* CLK */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
>>> + SUNXI_FUNCTION(0x3, "mmc1")), /* CMD */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
>>> + SUNXI_FUNCTION(0x3, "mmc1")), /* D0 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
>>> + SUNXI_FUNCTION(0x3, "mmc1")), /* D1 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
>>> + SUNXI_FUNCTION(0x3, "mmc1")), /* D2 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
>>> + SUNXI_FUNCTION(0x3, "mmc1")), /* D3 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
>>> + SUNXI_FUNCTION(0x3, "uart1")), /* TX */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
>>> + SUNXI_FUNCTION(0x3, "uart1")), /* RX */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
>>> + SUNXI_FUNCTION(0x3, "uart1")), /* RTS */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
>>> + SUNXI_FUNCTION(0x3, "uart1")), /* CTS */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
>>> + SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
>>> + SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
>>> + SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
>>> + SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
>>> + SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
>>> + SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
>>> + SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
>>> + SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
>>> + SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
>>> + SUNXI_FUNCTION(0x3, "lvds0")), /* VN3 */
>>> + /* Hole */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "csi")), /* PCLK */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "csi")), /* MCLK */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "csi")), /* HSYNC */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "csi")), /* VSYNC */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "csi")), /* D0 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "csi")), /* D1 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "csi")), /* D2 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "csi")), /* D3 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "csi")), /* D4 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "csi")), /* D5 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "csi")), /* D6 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "csi")), /* D7 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "csi"), /* SCK */
>>> + SUNXI_FUNCTION(0x3, "i2c2")), /* SCK */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "csi"), /* SDA */
>>> + SUNXI_FUNCTION(0x3, "i2c2")), /* SDA */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out")),
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out")),
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out")),
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out")),
>>> + /* Hole */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
>>> + SUNXI_FUNCTION(0x3, "jtag")), /* MS1 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
>>> + SUNXI_FUNCTION(0x3, "jtag")), /* DI1 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
>>> + SUNXI_FUNCTION(0x3, "uart0")), /* TX */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
>>> + SUNXI_FUNCTION(0x3, "jtag")), /* DO1 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
>>> + SUNXI_FUNCTION(0x3, "uart0")), /* RX */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
>>> + SUNXI_FUNCTION(0x3, "jtag")), /* CK1 */
>>> + /* Hole */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
>>> + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 0)), /* PG_EINT0 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
>>> + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 1)), /* PG_EINT1 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
>>> + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 2)), /* PG_EINT2 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
>>> + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 3)), /* PG_EINT3 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
>>> + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 4)), /* PG_EINT4 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
>>> + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 5)), /* PG_EINT5 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "uart1"), /* TX */
>>> + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 6)), /* PG_EINT6 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "uart1"), /* RX */
>>> + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 7)), /* PG_EINT7 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
>>> + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 8)), /* PG_EINT8 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
>>> + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 9)), /* PG_EINT9 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "i2s1"), /* SYNC */
>>> + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 10)), /* PG_EINT10 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "i2s1"), /* CLK */
>>> + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 11)), /* PG_EINT11 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "i2s1"), /* DOUT */
>>> + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 12)), /* PG_EINT12 */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "i2s1"), /* DIN */
>>> + SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 13)), /* PG_EINT13 */
>>> + /* Hole */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "pwm0")),
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "pwm1")),
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "spi0"), /* CS */
>>> + SUNXI_FUNCTION(0x3, "uart3")), /* TX */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
>>> + SUNXI_FUNCTION(0x3, "uart3")), /* RX */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "spi0"), /* DOUT */
>>> + SUNXI_FUNCTION(0x3, "uart3")), /* RTS */
>>> + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
>>> + SUNXI_FUNCTION(0x0, "gpio_in"),
>>> + SUNXI_FUNCTION(0x1, "gpio_out"),
>>> + SUNXI_FUNCTION(0x2, "spi0"), /* DIN */
>>> + SUNXI_FUNCTION(0x3, "uart3")), /* CTS */
>>> +};
>>> +
>>> +static const struct sunxi_pinctrl_desc sun8i_a33_pinctrl_data = {
>>> + .pins = sun8i_a33_pins,
>>> + .npins = ARRAY_SIZE(sun8i_a33_pins),
>>> + .irq_banks = 2,
>>> +};
>>> +
>>> +static int sun8i_a33_pinctrl_probe(struct platform_device *pdev)
>>> +{
>>> + return sunxi_pinctrl_init(pdev,
>>> + &sun8i_a33_pinctrl_data);
>>> +}
>>> +
>>> +static const struct of_device_id sun8i_a33_pinctrl_match[] = {
>>> + { .compatible = "allwinner,sun8i-a33-pinctrl", },
>>> + {}
>>> +};
>>> +MODULE_DEVICE_TABLE(of, sun8i_a33_pinctrl_match);
>>> +
>>> +static struct platform_driver sun8i_a33_pinctrl_driver = {
>>> + .probe = sun8i_a33_pinctrl_probe,
>>> + .driver = {
>>> + .name = "sun8i-a33-pinctrl",
>>> + .of_match_table = sun8i_a33_pinctrl_match,
>>> + },
>>> +};
>>> +module_platform_driver(sun8i_a33_pinctrl_driver);
>>> +
>>> +MODULE_AUTHOR("Vishnu Patekar <vishnupatekar0510@gmail.com>");
>>> +MODULE_DESCRIPTION("Allwinner a33 pinctrl driver");
>>> +MODULE_LICENSE("GPL");
>>>
>>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner A33 DTSI
2015-05-10 8:53 ` Hans de Goede
@ 2015-05-10 9:33 ` Vishnu Patekar
2015-05-10 9:54 ` Hans de Goede
0 siblings, 1 reply; 30+ messages in thread
From: Vishnu Patekar @ 2015-05-10 9:33 UTC (permalink / raw)
To: Hans de Goede
Cc: maxime.ripard, emilio, Linus Walleij, robh+dt, Chen-Yu Tsai,
Jens Kuske, Arnd Bergmann, linux-arm-kernel, linux-kernel,
linux-sunxi, devicetree
Hi,
On Sun, May 10, 2015 at 2:23 PM, Hans de Goede <hdegoede@redhat.com> wrote:
> Hi,
>
> On 10-05-15 08:46, Vishnu Patekar wrote:
>>
>> this is based on common sun8i.dtsi patch.
>> sun8i-a23.dtsi and sun8i-a33.dtsi are same, A33 specific features
>> e.g. clocks can be added in future.
>>
>> Signed-off-by: VishnuPatekar <vishnupatekar0510@gmail.com>
>
>
> This seems to only contain stuff which can be shared with the a23 dts,
> why is this not all in the common sun8i.dtsi ?
Allwinner H3 is also sun8i, I've referred the referred the H3 dtsi
patch sent by Jens Kuske.
I've added common parts bet a23 and h3 in sun8i.dtsi.
same note added in common sun8i PATCH 4, which I'm going to resend
after your comment.
>
> Regards,
>
> Hans
>
>
>> ---
>> arch/arm/boot/dts/sun8i-a33.dtsi | 217
>> +++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 217 insertions(+)
>> create mode 100644 arch/arm/boot/dts/sun8i-a33.dtsi
>>
>> diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi
>> b/arch/arm/boot/dts/sun8i-a33.dtsi
>> new file mode 100644
>> index 0000000..32489fc
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/sun8i-a33.dtsi
>> @@ -0,0 +1,217 @@
>> +/*
>> + * Copyright 2014 Chen-Yu Tsai
>> + *
>> + * Chen-Yu Tsai <wens@csie.org>
>> + *
>> + * This file is dual-licensed: you can use it either under the terms
>> + * of the GPL or the X11 license, at your option. Note that this dual
>> + * licensing only applies to this file, and not this project as a
>> + * whole.
>> + *
>> + * a) This file is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of the
>> + * License, or (at your option) any later version.
>> + *
>> + * This file is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + *
>> + * Or, alternatively,
>> + *
>> + * b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated documentation
>> + * files (the "Software"), to deal in the Software without
>> + * restriction, including without limitation the rights to use,
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following
>> + * conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be
>> + * included in all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> + */
>> +
>> +#include "sun8i.dtsi"
>> +
>> +/ {
>> + cpus {
>> + enable-method = "allwinner,sun8i";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + cpu@0 {
>> + compatible = "arm,cortex-a7";
>> + device_type = "cpu";
>> + reg = <0>;
>> + };
>> +
>> + cpu@1 {
>> + compatible = "arm,cortex-a7";
>> + device_type = "cpu";
>> + reg = <1>;
>> + };
>> +
>> + cpu@2 {
>> + compatible = "arm,cortex-a7";
>> + device_type = "cpu";
>> + reg = <2>;
>> + };
>> +
>> + cpu@3 {
>> + compatible = "arm,cortex-a7";
>> + device_type = "cpu";
>> + reg = <3>;
>> + };
>> + };
>> +
>> + memory {
>> + reg = <0x40000000 0x80000000>;
>> + };
>> +
>> + clocks {
>> + /* dummy clock until actually implemented */
>> + pll5: pll5_clk {
>> + #clock-cells = <0>;
>> + compatible = "fixed-clock";
>> + clock-frequency = <0>;
>> + clock-output-names = "pll5";
>> + };
>> +
>> + axi: axi_clk@01c20050 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun8i-a23-axi-clk";
>> + reg = <0x01c20050 0x4>;
>> + clocks = <&cpu>;
>> + clock-output-names = "axi";
>> + };
>> +
>> + ahb1_gates: clk@01c20060 {
>> + #clock-cells = <1>;
>> + compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
>> + reg = <0x01c20060 0x8>;
>> + clocks = <&ahb1>;
>> + clock-output-names = "ahb1_mipidsi", "ahb1_dma",
>> + "ahb1_mmc0", "ahb1_mmc1",
>> "ahb1_mmc2",
>> + "ahb1_nand", "ahb1_sdram",
>> + "ahb1_hstimer", "ahb1_spi0",
>> + "ahb1_spi1", "ahb1_otg",
>> "ahb1_ehci",
>> + "ahb1_ohci", "ahb1_ve",
>> "ahb1_lcd",
>> + "ahb1_csi", "ahb1_be", "ahb1_fe",
>> + "ahb1_gpu", "ahb1_spinlock",
>> + "ahb1_drc";
>> + };
>> +
>> + apb1_gates: clk@01c20068 {
>> + #clock-cells = <1>;
>> + compatible = "allwinner,sun8i-a23-apb1-gates-clk";
>> + reg = <0x01c20068 0x4>;
>> + clocks = <&apb1>;
>> + clock-output-names = "apb1_codec", "apb1_pio",
>> + "apb1_daudio0", "apb1_daudio1";
>> + };
>> +
>> + apb2: clk@01c20058 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-apb1-clk";
>> + reg = <0x01c20058 0x4>;
>> + clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6
>> 0>;
>> + clock-output-names = "apb2";
>> + };
>> +
>> + apb2_gates: clk@01c2006c {
>> + #clock-cells = <1>;
>> + compatible = "allwinner,sun8i-a23-apb2-gates-clk";
>> + reg = <0x01c2006c 0x4>;
>> + clocks = <&apb2>;
>> + clock-output-names = "apb2_i2c0", "apb2_i2c1",
>> + "apb2_i2c2", "apb2_uart0",
>> + "apb2_uart1", "apb2_uart2",
>> + "apb2_uart3", "apb2_uart4";
>> + };
>> +
>> + mbus_clk: clk@01c2015c {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun8i-a23-mbus-clk";
>> + reg = <0x01c2015c 0x4>;
>> + clocks = <&osc24M>, <&pll6 1>, <&pll5>;
>> + clock-output-names = "mbus";
>> + };
>> + };
>> +
>> + soc@01c00000 {
>> + dma: dma-controller@01c02000 {
>> + compatible = "allwinner,sun8i-a23-dma";
>> + reg = <0x01c02000 0x1000>;
>> + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ahb1_gates 6>;
>> + resets = <&ahb1_rst 6>;
>> + #dma-cells = <1>;
>> + };
>> +
>> + pio: pinctrl@01c20800 {
>> + compatible = "allwinner,sun8i-a33-pinctrl";
>> + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
>> +
>> + uart0_pins_a: uart0@0 {
>> + allwinner,pins = "PF2", "PF4";
>> + allwinner,function = "uart0";
>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> + };
>> +
>> + i2c0_pins_a: i2c0@0 {
>> + allwinner,pins = "PH2", "PH3";
>> + allwinner,function = "i2c0";
>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> + };
>> +
>> + i2c1_pins_a: i2c1@0 {
>> + allwinner,pins = "PH4", "PH5";
>> + allwinner,function = "i2c1";
>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> + };
>> +
>> + i2c2_pins_a: i2c2@0 {
>> + allwinner,pins = "PE12", "PE13";
>> + allwinner,function = "i2c2";
>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> + };
>> + };
>> +
>> + lradc: lradc@01c22800 {
>> + compatible = "allwinner,sun4i-a10-lradc-keys";
>> + reg = <0x01c22800 0x100>;
>> + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
>> + status = "disabled";
>> + };
>> +
>> + uart4: serial@01c29000 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x01c29000 0x400>;
>> + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + clocks = <&apb2_gates 20>;
>> + resets = <&apb2_rst 20>;
>> + dmas = <&dma 10>, <&dma 10>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + };
>> + };
>> +};
>>
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner A33 DTSI
2015-05-10 9:33 ` Vishnu Patekar
@ 2015-05-10 9:54 ` Hans de Goede
0 siblings, 0 replies; 30+ messages in thread
From: Hans de Goede @ 2015-05-10 9:54 UTC (permalink / raw)
To: Vishnu Patekar
Cc: maxime.ripard, emilio, Linus Walleij, robh+dt, Chen-Yu Tsai,
Jens Kuske, Arnd Bergmann, linux-arm-kernel, linux-kernel,
linux-sunxi, devicetree
Hi,
On 10-05-15 11:33, Vishnu Patekar wrote:
> Hi,
>
> On Sun, May 10, 2015 at 2:23 PM, Hans de Goede <hdegoede@redhat.com> wrote:
>> Hi,
>>
>> On 10-05-15 08:46, Vishnu Patekar wrote:
>>>
>>> this is based on common sun8i.dtsi patch.
>>> sun8i-a23.dtsi and sun8i-a33.dtsi are same, A33 specific features
>>> e.g. clocks can be added in future.
>>>
>>> Signed-off-by: VishnuPatekar <vishnupatekar0510@gmail.com>
>>
>>
>> This seems to only contain stuff which can be shared with the a23 dts,
>> why is this not all in the common sun8i.dtsi ?
> Allwinner H3 is also sun8i, I've referred the referred the H3 dtsi
> patch sent by Jens Kuske.
> I've added common parts bet a23 and h3 in sun8i.dtsi.
Ah, I see, ok that works for me.
Regards,
Hans
>
> same note added in common sun8i PATCH 4, which I'm going to resend
> after your comment.
>
>>
>> Regards,
>>
>> Hans
>>
>>
>>> ---
>>> arch/arm/boot/dts/sun8i-a33.dtsi | 217
>>> +++++++++++++++++++++++++++++++++++++++
>>> 1 file changed, 217 insertions(+)
>>> create mode 100644 arch/arm/boot/dts/sun8i-a33.dtsi
>>>
>>> diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi
>>> b/arch/arm/boot/dts/sun8i-a33.dtsi
>>> new file mode 100644
>>> index 0000000..32489fc
>>> --- /dev/null
>>> +++ b/arch/arm/boot/dts/sun8i-a33.dtsi
>>> @@ -0,0 +1,217 @@
>>> +/*
>>> + * Copyright 2014 Chen-Yu Tsai
>>> + *
>>> + * Chen-Yu Tsai <wens@csie.org>
>>> + *
>>> + * This file is dual-licensed: you can use it either under the terms
>>> + * of the GPL or the X11 license, at your option. Note that this dual
>>> + * licensing only applies to this file, and not this project as a
>>> + * whole.
>>> + *
>>> + * a) This file is free software; you can redistribute it and/or
>>> + * modify it under the terms of the GNU General Public License as
>>> + * published by the Free Software Foundation; either version 2 of the
>>> + * License, or (at your option) any later version.
>>> + *
>>> + * This file is distributed in the hope that it will be useful,
>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>>> + * GNU General Public License for more details.
>>> + *
>>> + *
>>> + * Or, alternatively,
>>> + *
>>> + * b) Permission is hereby granted, free of charge, to any person
>>> + * obtaining a copy of this software and associated documentation
>>> + * files (the "Software"), to deal in the Software without
>>> + * restriction, including without limitation the rights to use,
>>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>>> + * sell copies of the Software, and to permit persons to whom the
>>> + * Software is furnished to do so, subject to the following
>>> + * conditions:
>>> + *
>>> + * The above copyright notice and this permission notice shall be
>>> + * included in all copies or substantial portions of the Software.
>>> + *
>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>>> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>>> + * OTHER DEALINGS IN THE SOFTWARE.
>>> + */
>>> +
>>> +#include "sun8i.dtsi"
>>> +
>>> +/ {
>>> + cpus {
>>> + enable-method = "allwinner,sun8i";
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> +
>>> + cpu@0 {
>>> + compatible = "arm,cortex-a7";
>>> + device_type = "cpu";
>>> + reg = <0>;
>>> + };
>>> +
>>> + cpu@1 {
>>> + compatible = "arm,cortex-a7";
>>> + device_type = "cpu";
>>> + reg = <1>;
>>> + };
>>> +
>>> + cpu@2 {
>>> + compatible = "arm,cortex-a7";
>>> + device_type = "cpu";
>>> + reg = <2>;
>>> + };
>>> +
>>> + cpu@3 {
>>> + compatible = "arm,cortex-a7";
>>> + device_type = "cpu";
>>> + reg = <3>;
>>> + };
>>> + };
>>> +
>>> + memory {
>>> + reg = <0x40000000 0x80000000>;
>>> + };
>>> +
>>> + clocks {
>>> + /* dummy clock until actually implemented */
>>> + pll5: pll5_clk {
>>> + #clock-cells = <0>;
>>> + compatible = "fixed-clock";
>>> + clock-frequency = <0>;
>>> + clock-output-names = "pll5";
>>> + };
>>> +
>>> + axi: axi_clk@01c20050 {
>>> + #clock-cells = <0>;
>>> + compatible = "allwinner,sun8i-a23-axi-clk";
>>> + reg = <0x01c20050 0x4>;
>>> + clocks = <&cpu>;
>>> + clock-output-names = "axi";
>>> + };
>>> +
>>> + ahb1_gates: clk@01c20060 {
>>> + #clock-cells = <1>;
>>> + compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
>>> + reg = <0x01c20060 0x8>;
>>> + clocks = <&ahb1>;
>>> + clock-output-names = "ahb1_mipidsi", "ahb1_dma",
>>> + "ahb1_mmc0", "ahb1_mmc1",
>>> "ahb1_mmc2",
>>> + "ahb1_nand", "ahb1_sdram",
>>> + "ahb1_hstimer", "ahb1_spi0",
>>> + "ahb1_spi1", "ahb1_otg",
>>> "ahb1_ehci",
>>> + "ahb1_ohci", "ahb1_ve",
>>> "ahb1_lcd",
>>> + "ahb1_csi", "ahb1_be", "ahb1_fe",
>>> + "ahb1_gpu", "ahb1_spinlock",
>>> + "ahb1_drc";
>>> + };
>>> +
>>> + apb1_gates: clk@01c20068 {
>>> + #clock-cells = <1>;
>>> + compatible = "allwinner,sun8i-a23-apb1-gates-clk";
>>> + reg = <0x01c20068 0x4>;
>>> + clocks = <&apb1>;
>>> + clock-output-names = "apb1_codec", "apb1_pio",
>>> + "apb1_daudio0", "apb1_daudio1";
>>> + };
>>> +
>>> + apb2: clk@01c20058 {
>>> + #clock-cells = <0>;
>>> + compatible = "allwinner,sun4i-a10-apb1-clk";
>>> + reg = <0x01c20058 0x4>;
>>> + clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6
>>> 0>;
>>> + clock-output-names = "apb2";
>>> + };
>>> +
>>> + apb2_gates: clk@01c2006c {
>>> + #clock-cells = <1>;
>>> + compatible = "allwinner,sun8i-a23-apb2-gates-clk";
>>> + reg = <0x01c2006c 0x4>;
>>> + clocks = <&apb2>;
>>> + clock-output-names = "apb2_i2c0", "apb2_i2c1",
>>> + "apb2_i2c2", "apb2_uart0",
>>> + "apb2_uart1", "apb2_uart2",
>>> + "apb2_uart3", "apb2_uart4";
>>> + };
>>> +
>>> + mbus_clk: clk@01c2015c {
>>> + #clock-cells = <0>;
>>> + compatible = "allwinner,sun8i-a23-mbus-clk";
>>> + reg = <0x01c2015c 0x4>;
>>> + clocks = <&osc24M>, <&pll6 1>, <&pll5>;
>>> + clock-output-names = "mbus";
>>> + };
>>> + };
>>> +
>>> + soc@01c00000 {
>>> + dma: dma-controller@01c02000 {
>>> + compatible = "allwinner,sun8i-a23-dma";
>>> + reg = <0x01c02000 0x1000>;
>>> + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>>> + clocks = <&ahb1_gates 6>;
>>> + resets = <&ahb1_rst 6>;
>>> + #dma-cells = <1>;
>>> + };
>>> +
>>> + pio: pinctrl@01c20800 {
>>> + compatible = "allwinner,sun8i-a33-pinctrl";
>>> + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
>>> +
>>> + uart0_pins_a: uart0@0 {
>>> + allwinner,pins = "PF2", "PF4";
>>> + allwinner,function = "uart0";
>>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>>> + };
>>> +
>>> + i2c0_pins_a: i2c0@0 {
>>> + allwinner,pins = "PH2", "PH3";
>>> + allwinner,function = "i2c0";
>>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>>> + };
>>> +
>>> + i2c1_pins_a: i2c1@0 {
>>> + allwinner,pins = "PH4", "PH5";
>>> + allwinner,function = "i2c1";
>>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>>> + };
>>> +
>>> + i2c2_pins_a: i2c2@0 {
>>> + allwinner,pins = "PE12", "PE13";
>>> + allwinner,function = "i2c2";
>>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>>> + };
>>> + };
>>> +
>>> + lradc: lradc@01c22800 {
>>> + compatible = "allwinner,sun4i-a10-lradc-keys";
>>> + reg = <0x01c22800 0x100>;
>>> + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
>>> + status = "disabled";
>>> + };
>>> +
>>> + uart4: serial@01c29000 {
>>> + compatible = "snps,dw-apb-uart";
>>> + reg = <0x01c29000 0x400>;
>>> + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
>>> + reg-shift = <2>;
>>> + reg-io-width = <4>;
>>> + clocks = <&apb2_gates 20>;
>>> + resets = <&apb2_rst 20>;
>>> + dmas = <&dma 10>, <&dma 10>;
>>> + dma-names = "rx", "tx";
>>> + status = "disabled";
>>> + };
>>> + };
>>> +};
>>>
>>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 3/6] clk: sunxi: Add A33 clock for compilation
2015-05-10 6:46 ` [PATCH 3/6] clk: sunxi: Add A33 clock for compilation Vishnu Patekar
@ 2015-05-10 10:17 ` Maxime Ripard
2015-05-11 8:53 ` Vishnu Patekar
0 siblings, 1 reply; 30+ messages in thread
From: Maxime Ripard @ 2015-05-10 10:17 UTC (permalink / raw)
To: Vishnu Patekar
Cc: emilio, linus.walleij, robh+dt, hdegoede, wens, jenskuske, arnd,
linux-arm-kernel, linux-kernel, linux-sunxi, devicetree
[-- Attachment #1: Type: text/plain, Size: 712 bytes --]
Hi,
On Sun, May 10, 2015 at 12:16:20PM +0530, Vishnu Patekar wrote:
> A33 clock control unit is similar to A23.
>
> A33 specific clocks are not yet implemented, added CLK_OF_DECLARE
> to get it compiled for A33.
That commit log doesn't make any sense.
What you're doing isn't about whether or not that will be compiled,
but whether you're registering the clocks and which clocks you
protect.
> Signed-off-by: VishnuPatekar <vishnupatekar0510@gmail.com>
Isn't it supposed to have a space in the middle of your name, just
like you have in your mail address?
Thanks,
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 1/6] ARM: sunxi: Add Machine support for A33
2015-05-10 6:46 ` [PATCH 1/6] ARM: sunxi: Add Machine support for A33 Vishnu Patekar
2015-05-10 8:49 ` Hans de Goede
@ 2015-05-10 10:33 ` Maxime Ripard
2015-05-11 8:52 ` Vishnu Patekar
1 sibling, 1 reply; 30+ messages in thread
From: Maxime Ripard @ 2015-05-10 10:33 UTC (permalink / raw)
To: Vishnu Patekar
Cc: emilio, linus.walleij, robh+dt, hdegoede, wens, jenskuske, arnd,
linux-arm-kernel, linux-kernel, linux-sunxi, devicetree
[-- Attachment #1: Type: text/plain, Size: 4442 bytes --]
Hi,
On Sun, May 10, 2015 at 12:16:18PM +0530, Vishnu Patekar wrote:
> Allwinnner A33 quad core cortex-a7 based SOC.
There's one n to many in Allwinner, and having a verb in that sentence
would help
> It is similar to A23.
>
> Renamed cpu method to "allwinner,sun8i" for common sun8i smp.
> smp code is generic for A23, A33 and hopefully H3.
Please do only one thing in a patch.
> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
> ---
> Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
> arch/arm/mach-sunxi/Kconfig | 2 +-
> arch/arm/mach-sunxi/platsmp.c | 2 +-
> arch/arm/mach-sunxi/sunxi.c | 4 ++--
> 4 files changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
> index 42941fd..e32f082 100644
> --- a/Documentation/devicetree/bindings/arm/sunxi.txt
> +++ b/Documentation/devicetree/bindings/arm/sunxi.txt
> @@ -9,4 +9,5 @@ using one of the following compatible strings:
> allwinner,sun6i-a31
> allwinner,sun7i-a20
> allwinner,sun8i-a23
> + allwinner,sun8i-a33
Here you're introducing a new compatible for a machine that is
sun8i-a33.... [1]
> allwinner,sun9i-a80
> diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
> index 81502b9..38bedd8 100644
> --- a/arch/arm/mach-sunxi/Kconfig
> +++ b/arch/arm/mach-sunxi/Kconfig
> @@ -35,7 +35,7 @@ config MACH_SUN7I
> select SUN5I_HSTIMER
>
> config MACH_SUN8I
> - bool "Allwinner A23 (sun8i) SoCs support"
> + bool "Allwinner (sun8i) SoCs support"
> default ARCH_SUNXI
> select ARM_GIC
> select MFD_SUN6I_PRCM
> diff --git a/arch/arm/mach-sunxi/platsmp.c b/arch/arm/mach-sunxi/platsmp.c
> index e8483ec..c56b501 100644
> --- a/arch/arm/mach-sunxi/platsmp.c
> +++ b/arch/arm/mach-sunxi/platsmp.c
> @@ -189,4 +189,4 @@ struct smp_operations sun8i_smp_ops __initdata = {
> .smp_prepare_cpus = sun8i_smp_prepare_cpus,
> .smp_boot_secondary = sun8i_smp_boot_secondary,
> };
> -CPU_METHOD_OF_DECLARE(sun8i_a23_smp, "allwinner,sun8i-a23", &sun8i_smp_ops);
> +CPU_METHOD_OF_DECLARE(sun8i_smp, "allwinner,sun8i", &sun8i_smp_ops);
Like I was saying, this is an unrelated thing, it should be in a
separate patch.
And this is wrong.
A compatible should be made for the first IP that uses it. The first
user of that particular method has been the A23, it should be what's
in the compatible.
If the A33 is by chance using the exact same code, then we have two
choices, either reuse that compatible, or introduce a new one if it
slightly differs. And since the A33 has more cores than the A23, it
does differ.
So please add a new compatible.
That also breaks the SMP code in the A23 which is a no-go, since the
compatible would have changed but not the DT.
> diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
> index 1bc811a..8937d0d 100644
> --- a/arch/arm/mach-sunxi/sunxi.c
> +++ b/arch/arm/mach-sunxi/sunxi.c
> @@ -66,11 +66,11 @@ DT_MACHINE_START(SUN7I_DT, "Allwinner sun7i (A20) Family")
> MACHINE_END
>
> static const char * const sun8i_board_dt_compat[] = {
> - "allwinner,sun8i-a23",
> + "allwinner,sun8i",
[1] ... And here, you don't introduce that new machine compatible, but
remove one a use another one instead....
Apart from the documentation mismatch, you really shouldn't do that.
The machine compatible should be a identifier for the board and the
SoC, so that we can identify both easily, and possibly enable
quirks. The only question you should ask yourself whenever you add a
new compatible is "is this exactly the same IP" ?
In such a case, is the A23 *exactly* the same as the H3 and the A33?
The answer is obviously no, otherwise we would not have this patchset
in the first place.
So you just need to introduce a new compatible for the A33, just like
you did in the Documentation, and add that new compatible in the machine.
> NULL,
> };
>
> -DT_MACHINE_START(SUN8I_DT, "Allwinner sun8i (A23) Family")
> +DT_MACHINE_START(SUN8I_DT, "Allwinner sun8i Family")
> .dt_compat = sun8i_board_dt_compat,
> .init_late = sunxi_dt_cpufreq_init,
> MACHINE_END
> --
> 1.9.1
>
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 2/6] pinctrl: sunxi: add allwinner A33 PIO controller support
2015-05-10 6:46 ` [PATCH 2/6] pinctrl: sunxi: add allwinner A33 PIO controller support Vishnu Patekar
2015-05-10 8:50 ` Hans de Goede
@ 2015-05-10 10:34 ` Maxime Ripard
2015-05-11 7:22 ` Paul Bolle
2 siblings, 0 replies; 30+ messages in thread
From: Maxime Ripard @ 2015-05-10 10:34 UTC (permalink / raw)
To: Vishnu Patekar
Cc: emilio, linus.walleij, robh+dt, hdegoede, wens, jenskuske, arnd,
linux-arm-kernel, linux-kernel, linux-sunxi, devicetree
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On Sun, May 10, 2015 at 12:16:19PM +0530, Vishnu Patekar wrote:
> A33 PIO has 7 ports which starts from PB and has two interrupt ports.
>
> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 4/6] ARM: dts: sunxi: add common sun8i dtsi
2015-05-10 6:46 ` [PATCH 4/6] ARM: dts: sunxi: add common sun8i dtsi Vishnu Patekar
2015-05-10 8:52 ` Hans de Goede
@ 2015-05-10 10:41 ` Maxime Ripard
2015-05-11 11:18 ` Vishnu Patekar
1 sibling, 1 reply; 30+ messages in thread
From: Maxime Ripard @ 2015-05-10 10:41 UTC (permalink / raw)
To: Vishnu Patekar
Cc: emilio, linus.walleij, robh+dt, hdegoede, wens, jenskuske, arnd,
linux-arm-kernel, linux-kernel, linux-sunxi, devicetree
[-- Attachment #1: Type: text/plain, Size: 33166 bytes --]
Hi,
On Sun, May 10, 2015 at 12:16:21PM +0530, Vishnu Patekar wrote:
> added the common sun8i.dtsi and "allwinner,sun8i" compatible for common
> sun8i features, I've referred the h3 dtsi by Jens Kuske.
> accordingly modified the sun8i-a23.dtsi and a23 dts.
>
> I don't have a23 device, however, dts got compiled.
>
> Signed-off-by: VishnuPatekar <vishnupatekar0510@gmail.com>
Once again, that patch does several unrelated things at once.
> ---
> arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts | 6 +-
> arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts | 6 +-
> arch/arm/boot/dts/sun8i-a23.dtsi | 432 +----------------------
> arch/arm/boot/dts/sun8i.dtsi | 481 ++++++++++++++++++++++++++
> 4 files changed, 486 insertions(+), 439 deletions(-)
> create mode 100644 arch/arm/boot/dts/sun8i.dtsi
>
> diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts
> index dd31c53..b3f19e7 100644
> --- a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts
> +++ b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts
> @@ -16,10 +16,6 @@
> * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> * GNU General Public License for more details.
> *
> - * You should have received a copy of the GNU General Public
> - * License along with this file; if not, write to the Free
> - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
> - * MA 02110-1301 USA
It removes some check patch warning (and it's not even mentionned in
the commit log).
> * Or, alternatively,
> *
> @@ -55,5 +51,5 @@
>
> / {
> model = "Ippo Q8H Dual Core Tablet (v1.2)";
> - compatible = "ippo,q8h-v1.2", "allwinner,sun8i-a23";
> + compatible = "ippo,q8h-v1.2", "allwinner,sun8i", "allwinner,sun8i-a23";
It adds a new compatible to boards.
> };
> diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
> index f5658d1..5db4010 100644
> --- a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
> +++ b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
> @@ -18,10 +18,6 @@
> * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> * GNU General Public License for more details.
> *
> - * You should have received a copy of the GNU General Public
> - * License along with this file; if not, write to the Free
> - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
> - * MA 02110-1301 USA
> *
> * Or, alternatively,
> *
> @@ -57,7 +53,7 @@
>
> / {
> model = "Ippo Q8H Dual Core Tablet (v5)";
> - compatible = "ippo,q8h-v5", "allwinner,sun8i-a23";
> + compatible = "ippo,q8h-v5", "allwinner,sun8i", "allwinner,sun8i-a23";
>
> aliases {
> serial0 = &r_uart;
> diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi
> index 6d6eda3..c17be9e 100644
> --- a/arch/arm/boot/dts/sun8i-a23.dtsi
> +++ b/arch/arm/boot/dts/sun8i-a23.dtsi
> @@ -18,10 +18,6 @@
> * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> * GNU General Public License for more details.
> *
> - * You should have received a copy of the GNU General Public
> - * License along with this file; if not, write to the Free
> - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
> - * MA 02110-1301 USA
> *
> * Or, alternatively,
> *
> @@ -47,41 +43,11 @@
> * OTHER DEALINGS IN THE SOFTWARE.
> */
>
> -#include "skeleton.dtsi"
> -
> -#include <dt-bindings/interrupt-controller/arm-gic.h>
> -
> -#include <dt-bindings/pinctrl/sun4i-a10.h>
> +#include "sun8i.dtsi"
>
> / {
> - interrupt-parent = <&gic>;
> -
> - chosen {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - ranges;
> -
> - framebuffer@0 {
> - compatible = "allwinner,simple-framebuffer",
> - "simple-framebuffer";
> - allwinner,pipeline = "de_be0-lcd0";
> - clocks = <&pll6 0>;
> - status = "disabled";
> - };
> - };
> -
> - timer {
> - compatible = "arm,armv7-timer";
> - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> - clock-frequency = <24000000>;
> - arm,cpu-registers-not-fw-configured;
> - };
> -
> cpus {
> - enable-method = "allwinner,sun8i-a23";
> + enable-method = "allwinner,sun8i";
It updates a CPU enable method.
> #address-cells = <1>;
> #size-cells = <0>;
>
> @@ -103,32 +69,6 @@
> };
>
> clocks {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - ranges;
> -
> - osc24M: osc24M_clk {
> - #clock-cells = <0>;
> - compatible = "fixed-clock";
> - clock-frequency = <24000000>;
> - clock-output-names = "osc24M";
> - };
> -
> - osc32k: osc32k_clk {
> - #clock-cells = <0>;
> - compatible = "fixed-clock";
> - clock-frequency = <32768>;
> - clock-output-names = "osc32k";
> - };
> -
> - pll1: clk@01c20000 {
> - #clock-cells = <0>;
> - compatible = "allwinner,sun8i-a23-pll1-clk";
> - reg = <0x01c20000 0x4>;
> - clocks = <&osc24M>;
> - clock-output-names = "pll1";
> - };
> -
> /* dummy clock until actually implemented */
> pll5: pll5_clk {
> #clock-cells = <0>;
> @@ -137,29 +77,6 @@
> clock-output-names = "pll5";
> };
>
> - pll6: clk@01c20028 {
> - #clock-cells = <1>;
> - compatible = "allwinner,sun6i-a31-pll6-clk";
> - reg = <0x01c20028 0x4>;
> - clocks = <&osc24M>;
> - clock-output-names = "pll6", "pll6x2";
> - };
> -
> - cpu: cpu_clk@01c20050 {
> - #clock-cells = <0>;
> - compatible = "allwinner,sun4i-a10-cpu-clk";
> - reg = <0x01c20050 0x4>;
> -
> - /*
> - * PLL1 is listed twice here.
> - * While it looks suspicious, it's actually documented
> - * that way both in the datasheet and in the code from
> - * Allwinner.
> - */
> - clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
> - clock-output-names = "cpu";
> - };
> -
> axi: axi_clk@01c20050 {
> #clock-cells = <0>;
> compatible = "allwinner,sun8i-a23-axi-clk";
> @@ -168,22 +85,6 @@
> clock-output-names = "axi";
> };
>
> - ahb1: ahb1_clk@01c20054 {
> - #clock-cells = <0>;
> - compatible = "allwinner,sun6i-a31-ahb1-clk";
> - reg = <0x01c20054 0x4>;
> - clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
> - clock-output-names = "ahb1";
> - };
> -
> - apb1: apb1_clk@01c20054 {
> - #clock-cells = <0>;
> - compatible = "allwinner,sun4i-a10-apb0-clk";
> - reg = <0x01c20054 0x4>;
> - clocks = <&ahb1>;
> - clock-output-names = "apb1";
> - };
> -
> ahb1_gates: clk@01c20060 {
> #clock-cells = <1>;
> compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
> @@ -228,36 +129,6 @@
> "apb2_uart3", "apb2_uart4";
> };
>
> - mmc0_clk: clk@01c20088 {
> - #clock-cells = <1>;
> - compatible = "allwinner,sun4i-a10-mmc-clk";
> - reg = <0x01c20088 0x4>;
> - clocks = <&osc24M>, <&pll6 0>;
> - clock-output-names = "mmc0",
> - "mmc0_output",
> - "mmc0_sample";
> - };
> -
> - mmc1_clk: clk@01c2008c {
> - #clock-cells = <1>;
> - compatible = "allwinner,sun4i-a10-mmc-clk";
> - reg = <0x01c2008c 0x4>;
> - clocks = <&osc24M>, <&pll6 0>;
> - clock-output-names = "mmc1",
> - "mmc1_output",
> - "mmc1_sample";
> - };
> -
> - mmc2_clk: clk@01c20090 {
> - #clock-cells = <1>;
> - compatible = "allwinner,sun4i-a10-mmc-clk";
> - reg = <0x01c20090 0x4>;
> - clocks = <&osc24M>, <&pll6 0>;
> - clock-output-names = "mmc2",
> - "mmc2_output",
> - "mmc2_sample";
> - };
> -
> mbus_clk: clk@01c2015c {
> #clock-cells = <0>;
> compatible = "allwinner,sun8i-a23-mbus-clk";
> @@ -268,11 +139,6 @@
> };
>
> soc@01c00000 {
> - compatible = "simple-bus";
> - #address-cells = <1>;
> - #size-cells = <1>;
> - ranges;
> -
> dma: dma-controller@01c02000 {
> compatible = "allwinner,sun8i-a23-dma";
> reg = <0x01c02000 0x1000>;
> @@ -282,75 +148,12 @@
> #dma-cells = <1>;
> };
>
> - mmc0: mmc@01c0f000 {
> - compatible = "allwinner,sun5i-a13-mmc";
> - reg = <0x01c0f000 0x1000>;
> - clocks = <&ahb1_gates 8>,
> - <&mmc0_clk 0>,
> - <&mmc0_clk 1>,
> - <&mmc0_clk 2>;
> - clock-names = "ahb",
> - "mmc",
> - "output",
> - "sample";
> - resets = <&ahb1_rst 8>;
> - reset-names = "ahb";
> - interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
> - status = "disabled";
> - #address-cells = <1>;
> - #size-cells = <0>;
> - };
> -
> - mmc1: mmc@01c10000 {
> - compatible = "allwinner,sun5i-a13-mmc";
> - reg = <0x01c10000 0x1000>;
> - clocks = <&ahb1_gates 9>,
> - <&mmc1_clk 0>,
> - <&mmc1_clk 1>,
> - <&mmc1_clk 2>;
> - clock-names = "ahb",
> - "mmc",
> - "output",
> - "sample";
> - resets = <&ahb1_rst 9>;
> - reset-names = "ahb";
> - interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
> - status = "disabled";
> - #address-cells = <1>;
> - #size-cells = <0>;
> - };
> -
> - mmc2: mmc@01c11000 {
> - compatible = "allwinner,sun5i-a13-mmc";
> - reg = <0x01c11000 0x1000>;
> - clocks = <&ahb1_gates 10>,
> - <&mmc2_clk 0>,
> - <&mmc2_clk 1>,
> - <&mmc2_clk 2>;
> - clock-names = "ahb",
> - "mmc",
> - "output",
> - "sample";
> - resets = <&ahb1_rst 10>;
> - reset-names = "ahb";
> - interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
> - status = "disabled";
> - #address-cells = <1>;
> - #size-cells = <0>;
> - };
> -
> pio: pinctrl@01c20800 {
> compatible = "allwinner,sun8i-a23-pinctrl";
> - reg = <0x01c20800 0x400>;
> interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&apb1_gates 5>;
> - gpio-controller;
> - interrupt-controller;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - #gpio-cells = <3>;
> +
>
> uart0_pins_a: uart0@0 {
> allwinner,pins = "PF2", "PF4";
> @@ -359,20 +162,6 @@
> allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> };
>
> - mmc0_pins_a: mmc0@0 {
> - allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
> - allwinner,function = "mmc0";
> - allwinner,drive = <SUN4I_PINCTRL_30_MA>;
> - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> - };
> -
> - mmc1_pins_a: mmc1@0 {
> - allwinner,pins = "PG0","PG1","PG2","PG3","PG4","PG5";
> - allwinner,function = "mmc1";
> - allwinner,drive = <SUN4I_PINCTRL_30_MA>;
> - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> - };
> -
> i2c0_pins_a: i2c0@0 {
> allwinner,pins = "PH2", "PH3";
> allwinner,function = "i2c0";
> @@ -395,38 +184,6 @@
> };
> };
>
> - ahb1_rst: reset@01c202c0 {
> - #reset-cells = <1>;
> - compatible = "allwinner,sun6i-a31-clock-reset";
> - reg = <0x01c202c0 0xc>;
> - };
> -
> - apb1_rst: reset@01c202d0 {
> - #reset-cells = <1>;
> - compatible = "allwinner,sun6i-a31-clock-reset";
> - reg = <0x01c202d0 0x4>;
> - };
> -
> - apb2_rst: reset@01c202d8 {
> - #reset-cells = <1>;
> - compatible = "allwinner,sun6i-a31-clock-reset";
> - reg = <0x01c202d8 0x4>;
> - };
> -
> - timer@01c20c00 {
> - compatible = "allwinner,sun4i-a10-timer";
> - reg = <0x01c20c00 0xa0>;
> - interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&osc24M>;
> - };
> -
> - wdt0: watchdog@01c20ca0 {
> - compatible = "allwinner,sun6i-a31-wdt";
> - reg = <0x01c20ca0 0x20>;
> - interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
> - };
> -
> lradc: lradc@01c22800 {
> compatible = "allwinner,sun4i-a10-lradc-keys";
> reg = <0x01c22800 0x100>;
> @@ -434,58 +191,6 @@
> status = "disabled";
> };
>
> - uart0: serial@01c28000 {
> - compatible = "snps,dw-apb-uart";
> - reg = <0x01c28000 0x400>;
> - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> - reg-shift = <2>;
> - reg-io-width = <4>;
> - clocks = <&apb2_gates 16>;
> - resets = <&apb2_rst 16>;
> - dmas = <&dma 6>, <&dma 6>;
> - dma-names = "rx", "tx";
> - status = "disabled";
> - };
> -
> - uart1: serial@01c28400 {
> - compatible = "snps,dw-apb-uart";
> - reg = <0x01c28400 0x400>;
> - interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
> - reg-shift = <2>;
> - reg-io-width = <4>;
> - clocks = <&apb2_gates 17>;
> - resets = <&apb2_rst 17>;
> - dmas = <&dma 7>, <&dma 7>;
> - dma-names = "rx", "tx";
> - status = "disabled";
> - };
> -
> - uart2: serial@01c28800 {
> - compatible = "snps,dw-apb-uart";
> - reg = <0x01c28800 0x400>;
> - interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
> - reg-shift = <2>;
> - reg-io-width = <4>;
> - clocks = <&apb2_gates 18>;
> - resets = <&apb2_rst 18>;
> - dmas = <&dma 8>, <&dma 8>;
> - dma-names = "rx", "tx";
> - status = "disabled";
> - };
> -
> - uart3: serial@01c28c00 {
> - compatible = "snps,dw-apb-uart";
> - reg = <0x01c28c00 0x400>;
> - interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> - reg-shift = <2>;
> - reg-io-width = <4>;
> - clocks = <&apb2_gates 19>;
> - resets = <&apb2_rst 19>;
> - dmas = <&dma 9>, <&dma 9>;
> - dma-names = "rx", "tx";
> - status = "disabled";
> - };
> -
> uart4: serial@01c29000 {
> compatible = "snps,dw-apb-uart";
> reg = <0x01c29000 0x400>;
> @@ -498,136 +203,5 @@
> dma-names = "rx", "tx";
> status = "disabled";
> };
> -
> - i2c0: i2c@01c2ac00 {
> - compatible = "allwinner,sun6i-a31-i2c";
> - reg = <0x01c2ac00 0x400>;
> - interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&apb2_gates 0>;
> - resets = <&apb2_rst 0>;
> - status = "disabled";
> - #address-cells = <1>;
> - #size-cells = <0>;
> - };
> -
> - i2c1: i2c@01c2b000 {
> - compatible = "allwinner,sun6i-a31-i2c";
> - reg = <0x01c2b000 0x400>;
> - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&apb2_gates 1>;
> - resets = <&apb2_rst 1>;
> - status = "disabled";
> - #address-cells = <1>;
> - #size-cells = <0>;
> - };
> -
> - i2c2: i2c@01c2b400 {
> - compatible = "allwinner,sun6i-a31-i2c";
> - reg = <0x01c2b400 0x400>;
> - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&apb2_gates 2>;
> - resets = <&apb2_rst 2>;
> - status = "disabled";
> - #address-cells = <1>;
> - #size-cells = <0>;
> - };
> -
> - gic: interrupt-controller@01c81000 {
> - compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
> - reg = <0x01c81000 0x1000>,
> - <0x01c82000 0x1000>,
> - <0x01c84000 0x2000>,
> - <0x01c86000 0x2000>;
> - interrupt-controller;
> - #interrupt-cells = <3>;
> - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> - };
> -
> - rtc: rtc@01f00000 {
> - compatible = "allwinner,sun6i-a31-rtc";
> - reg = <0x01f00000 0x54>;
> - interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> - };
> -
> - prcm@01f01400 {
> - compatible = "allwinner,sun8i-a23-prcm";
> - reg = <0x01f01400 0x200>;
> -
> - ar100: ar100_clk {
> - compatible = "fixed-factor-clock";
> - #clock-cells = <0>;
> - clock-div = <1>;
> - clock-mult = <1>;
> - clocks = <&osc24M>;
> - clock-output-names = "ar100";
> - };
> -
> - ahb0: ahb0_clk {
> - compatible = "fixed-factor-clock";
> - #clock-cells = <0>;
> - clock-div = <1>;
> - clock-mult = <1>;
> - clocks = <&ar100>;
> - clock-output-names = "ahb0";
> - };
> -
> - apb0: apb0_clk {
> - compatible = "allwinner,sun8i-a23-apb0-clk";
> - #clock-cells = <0>;
> - clocks = <&ahb0>;
> - clock-output-names = "apb0";
> - };
> -
> - apb0_gates: apb0_gates_clk {
> - compatible = "allwinner,sun8i-a23-apb0-gates-clk";
> - #clock-cells = <1>;
> - clocks = <&apb0>;
> - clock-output-names = "apb0_pio", "apb0_timer",
> - "apb0_rsb", "apb0_uart",
> - "apb0_i2c";
> - };
> -
> - apb0_rst: apb0_rst {
> - compatible = "allwinner,sun6i-a31-clock-reset";
> - #reset-cells = <1>;
> - };
> - };
> -
> - cpucfg@01f01c00 {
> - compatible = "allwinner,sun8i-a23-cpuconfig";
> - reg = <0x01f01c00 0x300>;
> - };
> -
> - r_uart: serial@01f02800 {
> - compatible = "snps,dw-apb-uart";
> - reg = <0x01f02800 0x400>;
> - interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
> - reg-shift = <2>;
> - reg-io-width = <4>;
> - clocks = <&apb0_gates 4>;
> - resets = <&apb0_rst 4>;
> - status = "disabled";
> - };
> -
> - r_pio: pinctrl@01f02c00 {
> - compatible = "allwinner,sun8i-a23-r-pinctrl";
> - reg = <0x01f02c00 0x400>;
> - interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&apb0_gates 0>;
> - resets = <&apb0_rst 0>;
> - gpio-controller;
> - interrupt-controller;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - #gpio-cells = <3>;
> -
> - r_uart_pins_a: r_uart@0 {
> - allwinner,pins = "PL2", "PL3";
> - allwinner,function = "s_uart";
> - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> - };
> - };
> };
> };
> diff --git a/arch/arm/boot/dts/sun8i.dtsi b/arch/arm/boot/dts/sun8i.dtsi
> new file mode 100644
> index 0000000..cf481e5
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun8i.dtsi
> @@ -0,0 +1,481 @@
> +/*
> + * Copyright 2014 Chen-Yu Tsai
> + *
> + * Chen-Yu Tsai <wens@csie.org>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + *
> + * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +#include "skeleton.dtsi"
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +#include <dt-bindings/pinctrl/sun4i-a10.h>
> +
> +/ {
> + interrupt-parent = <&gic>;
> +
> + chosen {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + framebuffer@0 {
> + compatible = "allwinner,simple-framebuffer",
> + "simple-framebuffer";
> + allwinner,pipeline = "de_be0-lcd0";
> + clocks = <&pll6 0>;
> + status = "disabled";
> + };
> + };
> +
> + timer {
> + compatible = "arm,armv7-timer";
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> + clock-frequency = <24000000>;
> + arm,cpu-registers-not-fw-configured;
> + };
> +
> + clocks {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + osc24M: osc24M_clk {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <24000000>;
> + clock-output-names = "osc24M";
> + };
> +
> + osc32k: osc32k_clk {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <32768>;
> + clock-output-names = "osc32k";
> + };
> +
> + pll1: clk@01c20000 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun8i-a23-pll1-clk";
> + reg = <0x01c20000 0x4>;
> + clocks = <&osc24M>;
> + clock-output-names = "pll1";
> + };
> +
> + pll6: clk@01c20028 {
> + #clock-cells = <1>;
> + compatible = "allwinner,sun6i-a31-pll6-clk";
> + reg = <0x01c20028 0x4>;
> + clocks = <&osc24M>;
> + clock-output-names = "pll6", "pll6x2";
> + };
> +
> + cpu: cpu_clk@01c20050 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-cpu-clk";
> + reg = <0x01c20050 0x4>;
> +
> + /*
> + * PLL1 is listed twice here.
> + * While it looks suspicious, it's actually documented
> + * that way both in the datasheet and in the code from
> + * Allwinner.
> + */
> + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
> + clock-output-names = "cpu";
> + };
> +
> +
> + ahb1: ahb1_clk@01c20054 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun6i-a31-ahb1-clk";
> + reg = <0x01c20054 0x4>;
> + clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
> + clock-output-names = "ahb1";
> + };
> +
> + apb1: apb1_clk@01c20054 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-apb0-clk";
> + reg = <0x01c20054 0x4>;
> + clocks = <&ahb1>;
> + clock-output-names = "apb1";
> + };
> +
> + mmc0_clk: clk@01c20088 {
> + #clock-cells = <1>;
> + compatible = "allwinner,sun4i-a10-mmc-clk";
> + reg = <0x01c20088 0x4>;
> + clocks = <&osc24M>, <&pll6 0>;
> + clock-output-names = "mmc0",
> + "mmc0_output",
> + "mmc0_sample";
> + };
> +
> + mmc1_clk: clk@01c2008c {
> + #clock-cells = <1>;
> + compatible = "allwinner,sun4i-a10-mmc-clk";
> + reg = <0x01c2008c 0x4>;
> + clocks = <&osc24M>, <&pll6 0>;
> + clock-output-names = "mmc1",
> + "mmc1_output",
> + "mmc1_sample";
> + };
> +
> + mmc2_clk: clk@01c20090 {
> + #clock-cells = <1>;
> + compatible = "allwinner,sun4i-a10-mmc-clk";
> + reg = <0x01c20090 0x4>;
> + clocks = <&osc24M>, <&pll6 0>;
> + clock-output-names = "mmc2",
> + "mmc2_output",
> + "mmc2_sample";
> + };
> +
> + };
> +
> + soc@01c00000 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> +
> + mmc0: mmc@01c0f000 {
> + compatible = "allwinner,sun5i-a13-mmc";
> + reg = <0x01c0f000 0x1000>;
> + clocks = <&ahb1_gates 8>,
> + <&mmc0_clk 0>,
> + <&mmc0_clk 1>,
> + <&mmc0_clk 2>;
> + clock-names = "ahb",
> + "mmc",
> + "output",
> + "sample";
> + resets = <&ahb1_rst 8>;
> + reset-names = "ahb";
> + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + mmc1: mmc@01c10000 {
> + compatible = "allwinner,sun5i-a13-mmc";
> + reg = <0x01c10000 0x1000>;
> + clocks = <&ahb1_gates 9>,
> + <&mmc1_clk 0>,
> + <&mmc1_clk 1>,
> + <&mmc1_clk 2>;
> + clock-names = "ahb",
> + "mmc",
> + "output",
> + "sample";
> + resets = <&ahb1_rst 9>;
> + reset-names = "ahb";
> + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + mmc2: mmc@01c11000 {
> + compatible = "allwinner,sun5i-a13-mmc";
> + reg = <0x01c11000 0x1000>;
> + clocks = <&ahb1_gates 10>,
> + <&mmc2_clk 0>,
> + <&mmc2_clk 1>,
> + <&mmc2_clk 2>;
> + clock-names = "ahb",
> + "mmc",
> + "output",
> + "sample";
> + resets = <&ahb1_rst 10>;
> + reset-names = "ahb";
> + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + pio: pinctrl@01c20800 {
> + reg = <0x01c20800 0x400>;
> + clocks = <&apb1_gates 5>;
> + gpio-controller;
> + interrupt-controller;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #gpio-cells = <3>;
> +
> + mmc0_pins_a: mmc0@0 {
> + allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
> + allwinner,function = "mmc0";
> + allwinner,drive = <SUN4I_PINCTRL_30_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> + mmc1_pins_a: mmc1@0 {
> + allwinner,pins = "PG0","PG1","PG2","PG3","PG4","PG5";
> + allwinner,function = "mmc1";
> + allwinner,drive = <SUN4I_PINCTRL_30_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> + };
> +
> + ahb1_rst: reset@01c202c0 {
> + #reset-cells = <1>;
> + compatible = "allwinner,sun6i-a31-clock-reset";
> + reg = <0x01c202c0 0xc>;
> + };
> +
> + apb1_rst: reset@01c202d0 {
> + #reset-cells = <1>;
> + compatible = "allwinner,sun6i-a31-clock-reset";
> + reg = <0x01c202d0 0x4>;
> + };
> +
> + apb2_rst: reset@01c202d8 {
> + #reset-cells = <1>;
> + compatible = "allwinner,sun6i-a31-clock-reset";
> + reg = <0x01c202d8 0x4>;
> + };
> +
> + timer@01c20c00 {
> + compatible = "allwinner,sun4i-a10-timer";
> + reg = <0x01c20c00 0xa0>;
> + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&osc24M>;
> + };
> +
> + wdt0: watchdog@01c20ca0 {
> + compatible = "allwinner,sun6i-a31-wdt";
> + reg = <0x01c20ca0 0x20>;
> + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + uart0: serial@01c28000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c28000 0x400>;
> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&apb2_gates 16>;
> + resets = <&apb2_rst 16>;
> + dmas = <&dma 6>, <&dma 6>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + uart1: serial@01c28400 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c28400 0x400>;
> + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&apb2_gates 17>;
> + resets = <&apb2_rst 17>;
> + dmas = <&dma 7>, <&dma 7>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + uart2: serial@01c28800 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c28800 0x400>;
> + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&apb2_gates 18>;
> + resets = <&apb2_rst 18>;
> + dmas = <&dma 8>, <&dma 8>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + uart3: serial@01c28c00 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c28c00 0x400>;
> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&apb2_gates 19>;
> + resets = <&apb2_rst 19>;
> + dmas = <&dma 9>, <&dma 9>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + i2c0: i2c@01c2ac00 {
> + compatible = "allwinner,sun6i-a31-i2c";
> + reg = <0x01c2ac00 0x400>;
> + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&apb2_gates 0>;
> + resets = <&apb2_rst 0>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c1: i2c@01c2b000 {
> + compatible = "allwinner,sun6i-a31-i2c";
> + reg = <0x01c2b000 0x400>;
> + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&apb2_gates 1>;
> + resets = <&apb2_rst 1>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c2: i2c@01c2b400 {
> + compatible = "allwinner,sun6i-a31-i2c";
> + reg = <0x01c2b400 0x400>;
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&apb2_gates 2>;
> + resets = <&apb2_rst 2>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + gic: interrupt-controller@01c81000 {
> + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
> + reg = <0x01c81000 0x1000>,
> + <0x01c82000 0x1000>,
> + <0x01c84000 0x2000>,
> + <0x01c86000 0x2000>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> + };
> +
> + rtc: rtc@01f00000 {
> + compatible = "allwinner,sun6i-a31-rtc";
> + reg = <0x01f00000 0x54>;
> + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + prcm@01f01400 {
> + compatible = "allwinner,sun8i-a23-prcm";
> + reg = <0x01f01400 0x200>;
> +
> + ar100: ar100_clk {
> + compatible = "fixed-factor-clock";
> + #clock-cells = <0>;
> + clock-div = <1>;
> + clock-mult = <1>;
> + clocks = <&osc24M>;
> + clock-output-names = "ar100";
> + };
> +
> + ahb0: ahb0_clk {
> + compatible = "fixed-factor-clock";
> + #clock-cells = <0>;
> + clock-div = <1>;
> + clock-mult = <1>;
> + clocks = <&ar100>;
> + clock-output-names = "ahb0";
> + };
> +
> + apb0: apb0_clk {
> + compatible = "allwinner,sun8i-a23-apb0-clk";
> + #clock-cells = <0>;
> + clocks = <&ahb0>;
> + clock-output-names = "apb0";
> + };
> +
> + apb0_gates: apb0_gates_clk {
> + compatible = "allwinner,sun8i-a23-apb0-gates-clk";
> + #clock-cells = <1>;
> + clocks = <&apb0>;
> + clock-output-names = "apb0_pio", "apb0_timer",
> + "apb0_rsb", "apb0_uart",
> + "apb0_i2c";
> + };
> +
> + apb0_rst: apb0_rst {
> + compatible = "allwinner,sun6i-a31-clock-reset";
> + #reset-cells = <1>;
> + };
> + };
> +
> + cpucfg@01f01c00 {
> + compatible = "allwinner,sun8i-a23-cpuconfig";
> + reg = <0x01f01c00 0x300>;
> + };
> +
> + r_uart: serial@01f02800 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01f02800 0x400>;
> + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&apb0_gates 4>;
> + resets = <&apb0_rst 4>;
> + status = "disabled";
> + };
> +
> + r_pio: pinctrl@01f02c00 {
> + compatible = "allwinner,sun8i-a23-r-pinctrl";
> + reg = <0x01f02c00 0x400>;
> + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&apb0_gates 0>;
> + resets = <&apb0_rst 0>;
> + gpio-controller;
> + interrupt-controller;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #gpio-cells = <3>;
> +
> + r_uart_pins_a: r_uart@0 {
> + allwinner,pins = "PL2", "PL3";
> + allwinner,function = "s_uart";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> + };
> + };
> +};
And moves stuff between the A23 DTSI and sun8i DTSI.
All these things should be in separate patches.
Apart from that, as I told on IRC, I'd really like to have the H3
support merged and support for the A33 and H3 settle down a bit before
we create such a DTSI.
There's a lot of IPs that are enabled here that I'm pretty sure have
never been tested and/or even apply to the H3 and/or A33 (PRCM, arch
timers, A10 timers, etc.)
So let's merge everything in separate DTSI, and then, once we have a
clear view of what needs what, we will create a common DTSI.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner A33 DTSI
2015-05-10 6:46 ` [PATCH 5/6] ARM: dts: sunxi: Add Allwinner A33 DTSI Vishnu Patekar
2015-05-10 8:53 ` Hans de Goede
@ 2015-05-10 10:43 ` Maxime Ripard
1 sibling, 0 replies; 30+ messages in thread
From: Maxime Ripard @ 2015-05-10 10:43 UTC (permalink / raw)
To: Vishnu Patekar
Cc: emilio, linus.walleij, robh+dt, hdegoede, wens, jenskuske, arnd,
linux-arm-kernel, linux-kernel, linux-sunxi, devicetree
[-- Attachment #1: Type: text/plain, Size: 6126 bytes --]
Hi,
On Sun, May 10, 2015 at 12:16:22PM +0530, Vishnu Patekar wrote:
> this is based on common sun8i.dtsi patch.
> sun8i-a23.dtsi and sun8i-a33.dtsi are same, A33 specific features
> e.g. clocks can be added in future.
>
> Signed-off-by: VishnuPatekar <vishnupatekar0510@gmail.com>
> ---
> arch/arm/boot/dts/sun8i-a33.dtsi | 217 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 217 insertions(+)
> create mode 100644 arch/arm/boot/dts/sun8i-a33.dtsi
>
> diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi
> new file mode 100644
> index 0000000..32489fc
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun8i-a33.dtsi
> @@ -0,0 +1,217 @@
> +/*
> + * Copyright 2014 Chen-Yu Tsai
> + *
> + * Chen-Yu Tsai <wens@csie.org>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + *
> + * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +#include "sun8i.dtsi"
> +
> +/ {
> + cpus {
> + enable-method = "allwinner,sun8i";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + compatible = "arm,cortex-a7";
> + device_type = "cpu";
> + reg = <0>;
> + };
> +
> + cpu@1 {
> + compatible = "arm,cortex-a7";
> + device_type = "cpu";
> + reg = <1>;
> + };
> +
> + cpu@2 {
> + compatible = "arm,cortex-a7";
> + device_type = "cpu";
> + reg = <2>;
> + };
> +
> + cpu@3 {
> + compatible = "arm,cortex-a7";
> + device_type = "cpu";
> + reg = <3>;
> + };
> + };
> +
> + memory {
> + reg = <0x40000000 0x80000000>;
> + };
> +
> + clocks {
> + /* dummy clock until actually implemented */
> + pll5: pll5_clk {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <0>;
> + clock-output-names = "pll5";
> + };
> +
> + axi: axi_clk@01c20050 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun8i-a23-axi-clk";
> + reg = <0x01c20050 0x4>;
> + clocks = <&cpu>;
> + clock-output-names = "axi";
> + };
> +
> + ahb1_gates: clk@01c20060 {
> + #clock-cells = <1>;
> + compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
> + reg = <0x01c20060 0x8>;
> + clocks = <&ahb1>;
> + clock-output-names = "ahb1_mipidsi", "ahb1_dma",
> + "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
> + "ahb1_nand", "ahb1_sdram",
> + "ahb1_hstimer", "ahb1_spi0",
> + "ahb1_spi1", "ahb1_otg", "ahb1_ehci",
> + "ahb1_ohci", "ahb1_ve", "ahb1_lcd",
> + "ahb1_csi", "ahb1_be", "ahb1_fe",
> + "ahb1_gpu", "ahb1_spinlock",
> + "ahb1_drc";
> + };
> +
> + apb1_gates: clk@01c20068 {
> + #clock-cells = <1>;
> + compatible = "allwinner,sun8i-a23-apb1-gates-clk";
> + reg = <0x01c20068 0x4>;
> + clocks = <&apb1>;
> + clock-output-names = "apb1_codec", "apb1_pio",
> + "apb1_daudio0", "apb1_daudio1";
> + };
> +
> + apb2: clk@01c20058 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-apb1-clk";
> + reg = <0x01c20058 0x4>;
> + clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
> + clock-output-names = "apb2";
> + };
> +
> + apb2_gates: clk@01c2006c {
> + #clock-cells = <1>;
> + compatible = "allwinner,sun8i-a23-apb2-gates-clk";
> + reg = <0x01c2006c 0x4>;
> + clocks = <&apb2>;
> + clock-output-names = "apb2_i2c0", "apb2_i2c1",
> + "apb2_i2c2", "apb2_uart0",
> + "apb2_uart1", "apb2_uart2",
> + "apb2_uart3", "apb2_uart4";
> + };
> +
> + mbus_clk: clk@01c2015c {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun8i-a23-mbus-clk";
> + reg = <0x01c2015c 0x4>;
> + clocks = <&osc24M>, <&pll6 1>, <&pll5>;
> + clock-output-names = "mbus";
> + };
> + };
> +
> + soc@01c00000 {
> + dma: dma-controller@01c02000 {
> + compatible = "allwinner,sun8i-a23-dma";
> + reg = <0x01c02000 0x1000>;
> + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ahb1_gates 6>;
> + resets = <&ahb1_rst 6>;
> + #dma-cells = <1>;
> + };
With what device did you test DMA?
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 6/6] ARM: dts: sun8i: Add ET-Q8 A33 support
2015-05-10 6:46 ` [PATCH 6/6] ARM: dts: sun8i: Add ET-Q8 A33 support Vishnu Patekar
2015-05-10 8:54 ` Hans de Goede
@ 2015-05-10 10:47 ` Maxime Ripard
1 sibling, 0 replies; 30+ messages in thread
From: Maxime Ripard @ 2015-05-10 10:47 UTC (permalink / raw)
To: Vishnu Patekar
Cc: emilio, linus.walleij, robh+dt, hdegoede, wens, jenskuske, arnd,
linux-arm-kernel, linux-kernel, linux-sunxi, devicetree
[-- Attachment #1: Type: text/plain, Size: 5185 bytes --]
On Sun, May 10, 2015 at 12:16:23PM +0530, Vishnu Patekar wrote:
> ET-Q8_A33 is A33 based cheap tablet in common Q8 format.
>
> It has 512MB RAM, 4GB Nand, 7" Display, RDA5900P wifi, GSL1680 touch, etc.
>
> Signed-off-by: VishnuPatekar <vishnupatekar0510@gmail.com>
> ---
> arch/arm/boot/dts/Makefile | 3 +-
> arch/arm/boot/dts/sun8i-a33-et-q8.dts | 108 ++++++++++++++++++++++++++++++++++
> 2 files changed, 110 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/boot/dts/sun8i-a33-et-q8.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 82f4b9b..d44b1d6 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -570,7 +570,8 @@ dtb-$(CONFIG_MACH_SUN7I) += \
> sun7i-a20-wexler-tab7200.dtb
> dtb-$(CONFIG_MACH_SUN8I) += \
> sun8i-a23-ippo-q8h-v5.dtb \
> - sun8i-a23-ippo-q8h-v1.2.dtb
> + sun8i-a23-ippo-q8h-v1.2.dtb \
> + sun8i-a33-et-q8.dtb
> dtb-$(CONFIG_MACH_SUN9I) += \
> sun9i-a80-optimus.dtb \
> sun9i-a80-cubieboard4.dtb
> diff --git a/arch/arm/boot/dts/sun8i-a33-et-q8.dts b/arch/arm/boot/dts/sun8i-a33-et-q8.dts
> new file mode 100644
> index 0000000..260d5a3
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun8i-a33-et-q8.dts
> @@ -0,0 +1,108 @@
> +/*
> + * Copyright 2015 Vishnu Patekar
> + * Vishnu Patekar <vishnupatekar0510@gmail.com>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + *
> + * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/dts-v1/;
> +#include "sun8i-a33.dtsi"
> +#include "sunxi-common-regulators.dtsi"
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/pinctrl/sun4i-a10.h>
> +
> +/ {
> + model = "ET Q8 A33 ";
There's one trailing space here.
> + compatible = "et-q8-q33", "allwinner,sun8i", "allwinner,sun8i-a33";
All compatibles must be under the vendor,IP format.
What is the maker of your board? That should also be in the DT name,
under the format sun8i-a33-vendor-board.dts
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + bootargs = "earlyprintk console=ttyS0,115200";
> + };
Please use stdout-path here, just like we're doing on the other
boards.
> +};
> +
> +&lradc {
> + vref-supply = <®_vcc3v0>;
> + status = "okay";
> +
> + button@200 {
> + label = "Volume Up";
> + linux,code = <KEY_VOLUMEUP>;
> + channel = <0>;
> + voltage = <200000>;
> + };
> +
> + button@400 {
> + label = "Volume Down";
> + linux,code = <KEY_VOLUMEDOWN>;
> + channel = <0>;
> + voltage = <400000>;
> + };
> +};
> +
> +&i2c0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c0_pins_a>;
> + status = "okay";
> +};
> +
> +&i2c1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c1_pins_a>;
> + status = "okay";
> +};
> +
> +&i2c2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c2_pins_a>;
> + /* pull-ups and devices require PMIC regulator */
> + status = "failed";
> +};
Is this still true, or is it just a copy/paste mistake?
Thanks,
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 2/6] pinctrl: sunxi: add allwinner A33 PIO controller support
2015-05-10 6:46 ` [PATCH 2/6] pinctrl: sunxi: add allwinner A33 PIO controller support Vishnu Patekar
2015-05-10 8:50 ` Hans de Goede
2015-05-10 10:34 ` Maxime Ripard
@ 2015-05-11 7:22 ` Paul Bolle
2 siblings, 0 replies; 30+ messages in thread
From: Paul Bolle @ 2015-05-11 7:22 UTC (permalink / raw)
To: Vishnu Patekar
Cc: maxime.ripard, emilio, linus.walleij, robh+dt, hdegoede, wens,
jenskuske, arnd, linux-arm-kernel, linux-kernel, linux-sunxi,
devicetree
On Sun, 2015-05-10 at 12:16 +0530, Vishnu Patekar wrote:
> --- a/drivers/pinctrl/sunxi/Kconfig
> +++ b/drivers/pinctrl/sunxi/Kconfig
> +
(Unneeded white line.)
> +config PINCTRL_SUN8I_A33
> + def_bool MACH_SUN8I
> + select PINCTRL_SUNXI_COMMON
> --- a/drivers/pinctrl/sunxi/Makefile
> +++ b/drivers/pinctrl/sunxi/Makefile
> +obj-$(CONFIG_PINCTRL_SUN8I_A33) += pinctrl-sun8i-a33.o
PINCTRL_SUN8I_A33 is a bool symbol, so pinctrl-sun8i-a33.o will never be
part of a module, right?
> --- /dev/null
> +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
> @@ -0,0 +1,513 @@
> +#include <linux/module.h>
> +MODULE_DEVICE_TABLE(of, sun8i_a33_pinctrl_match);
> +
> +static struct platform_driver sun8i_a33_pinctrl_driver = {
> + .probe = sun8i_a33_pinctrl_probe,
> + .driver = {
> + .name = "sun8i-a33-pinctrl",
> + .of_match_table = sun8i_a33_pinctrl_match,
> + },
> +};
> +module_platform_driver(sun8i_a33_pinctrl_driver);
(The series starting at https://lkml.org/lkml/2015/5/10/131 would allow
to use builtin_platform_driver() for built-in only code.)
> +MODULE_AUTHOR("Vishnu Patekar <vishnupatekar0510@gmail.com>");
> +MODULE_DESCRIPTION("Allwinner a33 pinctrl driver");
> +MODULE_LICENSE("GPL");
This adds some module specific boilerplate. Was it perhaps your
intention to make PINCTRL_SUN8I_A33 a tristate symbol? If I understand
Maxime correctly drivers like these can be made modular (see
https://lkml.org/lkml/2015/5/9/96 ).
Thanks,
Paul Bolle
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 1/6] ARM: sunxi: Add Machine support for A33
2015-05-10 10:33 ` Maxime Ripard
@ 2015-05-11 8:52 ` Vishnu Patekar
0 siblings, 0 replies; 30+ messages in thread
From: Vishnu Patekar @ 2015-05-11 8:52 UTC (permalink / raw)
To: Maxime Ripard
Cc: emilio, Linus Walleij, robh+dt, Hans de Goede, Chen-Yu Tsai,
Jens Kuske, Arnd Bergmann, linux-arm-kernel, linux-kernel,
linux-sunxi, devicetree
Hi,
On Sun, May 10, 2015 at 4:03 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Hi,
>
> On Sun, May 10, 2015 at 12:16:18PM +0530, Vishnu Patekar wrote:
>> Allwinnner A33 quad core cortex-a7 based SOC.
>
> There's one n to many in Allwinner, and having a verb in that sentence
> would help
Yes, Correct.
>
>> It is similar to A23.
>>
>> Renamed cpu method to "allwinner,sun8i" for common sun8i smp.
>> smp code is generic for A23, A33 and hopefully H3.
>
> Please do only one thing in a patch.
OKie.
>
>> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
>> ---
>> Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
>> arch/arm/mach-sunxi/Kconfig | 2 +-
>> arch/arm/mach-sunxi/platsmp.c | 2 +-
>> arch/arm/mach-sunxi/sunxi.c | 4 ++--
>> 4 files changed, 5 insertions(+), 4 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
>> index 42941fd..e32f082 100644
>> --- a/Documentation/devicetree/bindings/arm/sunxi.txt
>> +++ b/Documentation/devicetree/bindings/arm/sunxi.txt
>> @@ -9,4 +9,5 @@ using one of the following compatible strings:
>> allwinner,sun6i-a31
>> allwinner,sun7i-a20
>> allwinner,sun8i-a23
>> + allwinner,sun8i-a33
>
> Here you're introducing a new compatible for a machine that is
> sun8i-a33.... [1]
>
>> allwinner,sun9i-a80
>> diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
>> index 81502b9..38bedd8 100644
>> --- a/arch/arm/mach-sunxi/Kconfig
>> +++ b/arch/arm/mach-sunxi/Kconfig
>> @@ -35,7 +35,7 @@ config MACH_SUN7I
>> select SUN5I_HSTIMER
>>
>> config MACH_SUN8I
>> - bool "Allwinner A23 (sun8i) SoCs support"
>> + bool "Allwinner (sun8i) SoCs support"
>> default ARCH_SUNXI
>> select ARM_GIC
>> select MFD_SUN6I_PRCM
>> diff --git a/arch/arm/mach-sunxi/platsmp.c b/arch/arm/mach-sunxi/platsmp.c
>> index e8483ec..c56b501 100644
>> --- a/arch/arm/mach-sunxi/platsmp.c
>> +++ b/arch/arm/mach-sunxi/platsmp.c
>> @@ -189,4 +189,4 @@ struct smp_operations sun8i_smp_ops __initdata = {
>> .smp_prepare_cpus = sun8i_smp_prepare_cpus,
>> .smp_boot_secondary = sun8i_smp_boot_secondary,
>> };
>> -CPU_METHOD_OF_DECLARE(sun8i_a23_smp, "allwinner,sun8i-a23", &sun8i_smp_ops);
>> +CPU_METHOD_OF_DECLARE(sun8i_smp, "allwinner,sun8i", &sun8i_smp_ops);
>
> Like I was saying, this is an unrelated thing, it should be in a
> separate patch.
>
> And this is wrong.
>
> A compatible should be made for the first IP that uses it. The first
> user of that particular method has been the A23, it should be what's
> in the compatible.
>
> If the A33 is by chance using the exact same code, then we have two
> choices, either reuse that compatible, or introduce a new one if it
> slightly differs. And since the A33 has more cores than the A23, it
> does differ.
>
> So please add a new compatible.
>
> That also breaks the SMP code in the A23 which is a no-go, since the
> compatible would have changed but not the DT.
I think adding something like below is good way to enable smp on a33
as we are going to use separate dtsi for a33,
and a23 for now.
CPU_METHOD_OF_DECLARE(sun8i_smp_a33, "allwinner,sun8i-a33", &sun8i_smp_ops);
>
>> diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
>> index 1bc811a..8937d0d 100644
>> --- a/arch/arm/mach-sunxi/sunxi.c
>> +++ b/arch/arm/mach-sunxi/sunxi.c
>> @@ -66,11 +66,11 @@ DT_MACHINE_START(SUN7I_DT, "Allwinner sun7i (A20) Family")
>> MACHINE_END
>>
>> static const char * const sun8i_board_dt_compat[] = {
>> - "allwinner,sun8i-a23",
>> + "allwinner,sun8i",
>
> [1] ... And here, you don't introduce that new machine compatible, but
> remove one a use another one instead....
>
> Apart from the documentation mismatch, you really shouldn't do that.
>
> The machine compatible should be a identifier for the board and the
> SoC, so that we can identify both easily, and possibly enable
> quirks. The only question you should ask yourself whenever you add a
> new compatible is "is this exactly the same IP" ?
>
> In such a case, is the A23 *exactly* the same as the H3 and the A33?
>
> The answer is obviously no, otherwise we would not have this patchset
> in the first place.
>
> So you just need to introduce a new compatible for the A33, just like
> you did in the Documentation, and add that new compatible in the machine.
I'll add new compatible, "allwinner,sun8i-a33"
>
>> NULL,
>> };
>>
>> -DT_MACHINE_START(SUN8I_DT, "Allwinner sun8i (A23) Family")
>> +DT_MACHINE_START(SUN8I_DT, "Allwinner sun8i Family")
>> .dt_compat = sun8i_board_dt_compat,
>> .init_late = sunxi_dt_cpufreq_init,
>> MACHINE_END
>> --
>> 1.9.1
>>
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux, Kernel and Android engineering
> http://free-electrons.com
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 3/6] clk: sunxi: Add A33 clock for compilation
2015-05-10 10:17 ` Maxime Ripard
@ 2015-05-11 8:53 ` Vishnu Patekar
2015-07-17 8:57 ` Chen-Yu Tsai
0 siblings, 1 reply; 30+ messages in thread
From: Vishnu Patekar @ 2015-05-11 8:53 UTC (permalink / raw)
To: Maxime Ripard
Cc: emilio, Linus Walleij, robh+dt, Hans de Goede, Chen-Yu Tsai,
Jens Kuske, Arnd Bergmann, linux-arm-kernel, linux-kernel,
linux-sunxi, devicetree
Hi,
On Sun, May 10, 2015 at 3:47 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Hi,
>
> On Sun, May 10, 2015 at 12:16:20PM +0530, Vishnu Patekar wrote:
>> A33 clock control unit is similar to A23.
>>
>> A33 specific clocks are not yet implemented, added CLK_OF_DECLARE
>> to get it compiled for A33.
>
> That commit log doesn't make any sense.
>
> What you're doing isn't about whether or not that will be compiled,
> but whether you're registering the clocks and which clocks you
> protect.
Actually, It's just registering the a33 clocks and reusing a23 code.
nothing to do with compile. I'll correct it in next patch version.
>
>> Signed-off-by: VishnuPatekar <vishnupatekar0510@gmail.com>
>
> Isn't it supposed to have a space in the middle of your name, just
> like you have in your mail address?
Yes, There should be space.
>
> Thanks,
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux, Kernel and Android engineering
> http://free-electrons.com
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 4/6] ARM: dts: sunxi: add common sun8i dtsi
2015-05-10 10:41 ` Maxime Ripard
@ 2015-05-11 11:18 ` Vishnu Patekar
0 siblings, 0 replies; 30+ messages in thread
From: Vishnu Patekar @ 2015-05-11 11:18 UTC (permalink / raw)
To: Maxime Ripard
Cc: emilio, Linus Walleij, robh+dt, Hans de Goede, Chen-Yu Tsai,
Jens Kuske, Arnd Bergmann, linux-arm-kernel, linux-kernel,
linux-sunxi, devicetree
Hi,
On Sun, May 10, 2015 at 4:11 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Hi,
>
> On Sun, May 10, 2015 at 12:16:21PM +0530, Vishnu Patekar wrote:
>> added the common sun8i.dtsi and "allwinner,sun8i" compatible for common
>> sun8i features, I've referred the h3 dtsi by Jens Kuske.
>> accordingly modified the sun8i-a23.dtsi and a23 dts.
>>
>> I don't have a23 device, however, dts got compiled.
>>
>> Signed-off-by: VishnuPatekar <vishnupatekar0510@gmail.com>
>
> Once again, that patch does several unrelated things at once.
>
>> ---
>> arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts | 6 +-
>> arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts | 6 +-
>> arch/arm/boot/dts/sun8i-a23.dtsi | 432 +----------------------
>> arch/arm/boot/dts/sun8i.dtsi | 481 ++++++++++++++++++++++++++
>> 4 files changed, 486 insertions(+), 439 deletions(-)
>> create mode 100644 arch/arm/boot/dts/sun8i.dtsi
>>
>> diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts
>> index dd31c53..b3f19e7 100644
>> --- a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts
>> +++ b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts
>> @@ -16,10 +16,6 @@
>> * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> * GNU General Public License for more details.
>> *
>> - * You should have received a copy of the GNU General Public
>> - * License along with this file; if not, write to the Free
>> - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
>> - * MA 02110-1301 USA
>
> It removes some check patch warning (and it's not even mentionned in
> the commit log).
I'll mention it in commit log wherever I'll remove it.
>
>> * Or, alternatively,
>> *
>> @@ -55,5 +51,5 @@
>>
>> / {
>> model = "Ippo Q8H Dual Core Tablet (v1.2)";
>> - compatible = "ippo,q8h-v1.2", "allwinner,sun8i-a23";
>> + compatible = "ippo,q8h-v1.2", "allwinner,sun8i", "allwinner,sun8i-a23";
>
> It adds a new compatible to boards.
>
>> };
>> diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
>> index f5658d1..5db4010 100644
>> --- a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
>> +++ b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
>> @@ -18,10 +18,6 @@
>> * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> * GNU General Public License for more details.
>> *
>> - * You should have received a copy of the GNU General Public
>> - * License along with this file; if not, write to the Free
>> - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
>> - * MA 02110-1301 USA
>> *
>> * Or, alternatively,
>> *
>> @@ -57,7 +53,7 @@
>>
>> / {
>> model = "Ippo Q8H Dual Core Tablet (v5)";
>> - compatible = "ippo,q8h-v5", "allwinner,sun8i-a23";
>> + compatible = "ippo,q8h-v5", "allwinner,sun8i", "allwinner,sun8i-a23";
>>
>> aliases {
>> serial0 = &r_uart;
>> diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi
>> index 6d6eda3..c17be9e 100644
>> --- a/arch/arm/boot/dts/sun8i-a23.dtsi
>> +++ b/arch/arm/boot/dts/sun8i-a23.dtsi
>> @@ -18,10 +18,6 @@
>> * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> * GNU General Public License for more details.
>> *
>> - * You should have received a copy of the GNU General Public
>> - * License along with this file; if not, write to the Free
>> - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
>> - * MA 02110-1301 USA
>> *
>> * Or, alternatively,
>> *
>> @@ -47,41 +43,11 @@
>> * OTHER DEALINGS IN THE SOFTWARE.
>> */
>>
>> -#include "skeleton.dtsi"
>> -
>> -#include <dt-bindings/interrupt-controller/arm-gic.h>
>> -
>> -#include <dt-bindings/pinctrl/sun4i-a10.h>
>> +#include "sun8i.dtsi"
>>
>> / {
>> - interrupt-parent = <&gic>;
>> -
>> - chosen {
>> - #address-cells = <1>;
>> - #size-cells = <1>;
>> - ranges;
>> -
>> - framebuffer@0 {
>> - compatible = "allwinner,simple-framebuffer",
>> - "simple-framebuffer";
>> - allwinner,pipeline = "de_be0-lcd0";
>> - clocks = <&pll6 0>;
>> - status = "disabled";
>> - };
>> - };
>> -
>> - timer {
>> - compatible = "arm,armv7-timer";
>> - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
>> - clock-frequency = <24000000>;
>> - arm,cpu-registers-not-fw-configured;
>> - };
>> -
>> cpus {
>> - enable-method = "allwinner,sun8i-a23";
>> + enable-method = "allwinner,sun8i";
>
> It updates a CPU enable method.
>
>> #address-cells = <1>;
>> #size-cells = <0>;
>>
>> @@ -103,32 +69,6 @@
>> };
>>
>> clocks {
>> - #address-cells = <1>;
>> - #size-cells = <1>;
>> - ranges;
>> -
>> - osc24M: osc24M_clk {
>> - #clock-cells = <0>;
>> - compatible = "fixed-clock";
>> - clock-frequency = <24000000>;
>> - clock-output-names = "osc24M";
>> - };
>> -
>> - osc32k: osc32k_clk {
>> - #clock-cells = <0>;
>> - compatible = "fixed-clock";
>> - clock-frequency = <32768>;
>> - clock-output-names = "osc32k";
>> - };
>> -
>> - pll1: clk@01c20000 {
>> - #clock-cells = <0>;
>> - compatible = "allwinner,sun8i-a23-pll1-clk";
>> - reg = <0x01c20000 0x4>;
>> - clocks = <&osc24M>;
>> - clock-output-names = "pll1";
>> - };
>> -
>> /* dummy clock until actually implemented */
>> pll5: pll5_clk {
>> #clock-cells = <0>;
>> @@ -137,29 +77,6 @@
>> clock-output-names = "pll5";
>> };
>>
>> - pll6: clk@01c20028 {
>> - #clock-cells = <1>;
>> - compatible = "allwinner,sun6i-a31-pll6-clk";
>> - reg = <0x01c20028 0x4>;
>> - clocks = <&osc24M>;
>> - clock-output-names = "pll6", "pll6x2";
>> - };
>> -
>> - cpu: cpu_clk@01c20050 {
>> - #clock-cells = <0>;
>> - compatible = "allwinner,sun4i-a10-cpu-clk";
>> - reg = <0x01c20050 0x4>;
>> -
>> - /*
>> - * PLL1 is listed twice here.
>> - * While it looks suspicious, it's actually documented
>> - * that way both in the datasheet and in the code from
>> - * Allwinner.
>> - */
>> - clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
>> - clock-output-names = "cpu";
>> - };
>> -
>> axi: axi_clk@01c20050 {
>> #clock-cells = <0>;
>> compatible = "allwinner,sun8i-a23-axi-clk";
>> @@ -168,22 +85,6 @@
>> clock-output-names = "axi";
>> };
>>
>> - ahb1: ahb1_clk@01c20054 {
>> - #clock-cells = <0>;
>> - compatible = "allwinner,sun6i-a31-ahb1-clk";
>> - reg = <0x01c20054 0x4>;
>> - clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
>> - clock-output-names = "ahb1";
>> - };
>> -
>> - apb1: apb1_clk@01c20054 {
>> - #clock-cells = <0>;
>> - compatible = "allwinner,sun4i-a10-apb0-clk";
>> - reg = <0x01c20054 0x4>;
>> - clocks = <&ahb1>;
>> - clock-output-names = "apb1";
>> - };
>> -
>> ahb1_gates: clk@01c20060 {
>> #clock-cells = <1>;
>> compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
>> @@ -228,36 +129,6 @@
>> "apb2_uart3", "apb2_uart4";
>> };
>>
>> - mmc0_clk: clk@01c20088 {
>> - #clock-cells = <1>;
>> - compatible = "allwinner,sun4i-a10-mmc-clk";
>> - reg = <0x01c20088 0x4>;
>> - clocks = <&osc24M>, <&pll6 0>;
>> - clock-output-names = "mmc0",
>> - "mmc0_output",
>> - "mmc0_sample";
>> - };
>> -
>> - mmc1_clk: clk@01c2008c {
>> - #clock-cells = <1>;
>> - compatible = "allwinner,sun4i-a10-mmc-clk";
>> - reg = <0x01c2008c 0x4>;
>> - clocks = <&osc24M>, <&pll6 0>;
>> - clock-output-names = "mmc1",
>> - "mmc1_output",
>> - "mmc1_sample";
>> - };
>> -
>> - mmc2_clk: clk@01c20090 {
>> - #clock-cells = <1>;
>> - compatible = "allwinner,sun4i-a10-mmc-clk";
>> - reg = <0x01c20090 0x4>;
>> - clocks = <&osc24M>, <&pll6 0>;
>> - clock-output-names = "mmc2",
>> - "mmc2_output",
>> - "mmc2_sample";
>> - };
>> -
>> mbus_clk: clk@01c2015c {
>> #clock-cells = <0>;
>> compatible = "allwinner,sun8i-a23-mbus-clk";
>> @@ -268,11 +139,6 @@
>> };
>>
>> soc@01c00000 {
>> - compatible = "simple-bus";
>> - #address-cells = <1>;
>> - #size-cells = <1>;
>> - ranges;
>> -
>> dma: dma-controller@01c02000 {
>> compatible = "allwinner,sun8i-a23-dma";
>> reg = <0x01c02000 0x1000>;
>> @@ -282,75 +148,12 @@
>> #dma-cells = <1>;
>> };
>>
>> - mmc0: mmc@01c0f000 {
>> - compatible = "allwinner,sun5i-a13-mmc";
>> - reg = <0x01c0f000 0x1000>;
>> - clocks = <&ahb1_gates 8>,
>> - <&mmc0_clk 0>,
>> - <&mmc0_clk 1>,
>> - <&mmc0_clk 2>;
>> - clock-names = "ahb",
>> - "mmc",
>> - "output",
>> - "sample";
>> - resets = <&ahb1_rst 8>;
>> - reset-names = "ahb";
>> - interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
>> - status = "disabled";
>> - #address-cells = <1>;
>> - #size-cells = <0>;
>> - };
>> -
>> - mmc1: mmc@01c10000 {
>> - compatible = "allwinner,sun5i-a13-mmc";
>> - reg = <0x01c10000 0x1000>;
>> - clocks = <&ahb1_gates 9>,
>> - <&mmc1_clk 0>,
>> - <&mmc1_clk 1>,
>> - <&mmc1_clk 2>;
>> - clock-names = "ahb",
>> - "mmc",
>> - "output",
>> - "sample";
>> - resets = <&ahb1_rst 9>;
>> - reset-names = "ahb";
>> - interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
>> - status = "disabled";
>> - #address-cells = <1>;
>> - #size-cells = <0>;
>> - };
>> -
>> - mmc2: mmc@01c11000 {
>> - compatible = "allwinner,sun5i-a13-mmc";
>> - reg = <0x01c11000 0x1000>;
>> - clocks = <&ahb1_gates 10>,
>> - <&mmc2_clk 0>,
>> - <&mmc2_clk 1>,
>> - <&mmc2_clk 2>;
>> - clock-names = "ahb",
>> - "mmc",
>> - "output",
>> - "sample";
>> - resets = <&ahb1_rst 10>;
>> - reset-names = "ahb";
>> - interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
>> - status = "disabled";
>> - #address-cells = <1>;
>> - #size-cells = <0>;
>> - };
>> -
>> pio: pinctrl@01c20800 {
>> compatible = "allwinner,sun8i-a23-pinctrl";
>> - reg = <0x01c20800 0x400>;
>> interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
>> <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
>> <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
>> - clocks = <&apb1_gates 5>;
>> - gpio-controller;
>> - interrupt-controller;
>> - #address-cells = <1>;
>> - #size-cells = <0>;
>> - #gpio-cells = <3>;
>> +
>>
>> uart0_pins_a: uart0@0 {
>> allwinner,pins = "PF2", "PF4";
>> @@ -359,20 +162,6 @@
>> allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> };
>>
>> - mmc0_pins_a: mmc0@0 {
>> - allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
>> - allwinner,function = "mmc0";
>> - allwinner,drive = <SUN4I_PINCTRL_30_MA>;
>> - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> - };
>> -
>> - mmc1_pins_a: mmc1@0 {
>> - allwinner,pins = "PG0","PG1","PG2","PG3","PG4","PG5";
>> - allwinner,function = "mmc1";
>> - allwinner,drive = <SUN4I_PINCTRL_30_MA>;
>> - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> - };
>> -
>> i2c0_pins_a: i2c0@0 {
>> allwinner,pins = "PH2", "PH3";
>> allwinner,function = "i2c0";
>> @@ -395,38 +184,6 @@
>> };
>> };
>>
>> - ahb1_rst: reset@01c202c0 {
>> - #reset-cells = <1>;
>> - compatible = "allwinner,sun6i-a31-clock-reset";
>> - reg = <0x01c202c0 0xc>;
>> - };
>> -
>> - apb1_rst: reset@01c202d0 {
>> - #reset-cells = <1>;
>> - compatible = "allwinner,sun6i-a31-clock-reset";
>> - reg = <0x01c202d0 0x4>;
>> - };
>> -
>> - apb2_rst: reset@01c202d8 {
>> - #reset-cells = <1>;
>> - compatible = "allwinner,sun6i-a31-clock-reset";
>> - reg = <0x01c202d8 0x4>;
>> - };
>> -
>> - timer@01c20c00 {
>> - compatible = "allwinner,sun4i-a10-timer";
>> - reg = <0x01c20c00 0xa0>;
>> - interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
>> - <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>> - clocks = <&osc24M>;
>> - };
>> -
>> - wdt0: watchdog@01c20ca0 {
>> - compatible = "allwinner,sun6i-a31-wdt";
>> - reg = <0x01c20ca0 0x20>;
>> - interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
>> - };
>> -
>> lradc: lradc@01c22800 {
>> compatible = "allwinner,sun4i-a10-lradc-keys";
>> reg = <0x01c22800 0x100>;
>> @@ -434,58 +191,6 @@
>> status = "disabled";
>> };
>>
>> - uart0: serial@01c28000 {
>> - compatible = "snps,dw-apb-uart";
>> - reg = <0x01c28000 0x400>;
>> - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
>> - reg-shift = <2>;
>> - reg-io-width = <4>;
>> - clocks = <&apb2_gates 16>;
>> - resets = <&apb2_rst 16>;
>> - dmas = <&dma 6>, <&dma 6>;
>> - dma-names = "rx", "tx";
>> - status = "disabled";
>> - };
>> -
>> - uart1: serial@01c28400 {
>> - compatible = "snps,dw-apb-uart";
>> - reg = <0x01c28400 0x400>;
>> - interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
>> - reg-shift = <2>;
>> - reg-io-width = <4>;
>> - clocks = <&apb2_gates 17>;
>> - resets = <&apb2_rst 17>;
>> - dmas = <&dma 7>, <&dma 7>;
>> - dma-names = "rx", "tx";
>> - status = "disabled";
>> - };
>> -
>> - uart2: serial@01c28800 {
>> - compatible = "snps,dw-apb-uart";
>> - reg = <0x01c28800 0x400>;
>> - interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
>> - reg-shift = <2>;
>> - reg-io-width = <4>;
>> - clocks = <&apb2_gates 18>;
>> - resets = <&apb2_rst 18>;
>> - dmas = <&dma 8>, <&dma 8>;
>> - dma-names = "rx", "tx";
>> - status = "disabled";
>> - };
>> -
>> - uart3: serial@01c28c00 {
>> - compatible = "snps,dw-apb-uart";
>> - reg = <0x01c28c00 0x400>;
>> - interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
>> - reg-shift = <2>;
>> - reg-io-width = <4>;
>> - clocks = <&apb2_gates 19>;
>> - resets = <&apb2_rst 19>;
>> - dmas = <&dma 9>, <&dma 9>;
>> - dma-names = "rx", "tx";
>> - status = "disabled";
>> - };
>> -
>> uart4: serial@01c29000 {
>> compatible = "snps,dw-apb-uart";
>> reg = <0x01c29000 0x400>;
>> @@ -498,136 +203,5 @@
>> dma-names = "rx", "tx";
>> status = "disabled";
>> };
>> -
>> - i2c0: i2c@01c2ac00 {
>> - compatible = "allwinner,sun6i-a31-i2c";
>> - reg = <0x01c2ac00 0x400>;
>> - interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
>> - clocks = <&apb2_gates 0>;
>> - resets = <&apb2_rst 0>;
>> - status = "disabled";
>> - #address-cells = <1>;
>> - #size-cells = <0>;
>> - };
>> -
>> - i2c1: i2c@01c2b000 {
>> - compatible = "allwinner,sun6i-a31-i2c";
>> - reg = <0x01c2b000 0x400>;
>> - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
>> - clocks = <&apb2_gates 1>;
>> - resets = <&apb2_rst 1>;
>> - status = "disabled";
>> - #address-cells = <1>;
>> - #size-cells = <0>;
>> - };
>> -
>> - i2c2: i2c@01c2b400 {
>> - compatible = "allwinner,sun6i-a31-i2c";
>> - reg = <0x01c2b400 0x400>;
>> - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
>> - clocks = <&apb2_gates 2>;
>> - resets = <&apb2_rst 2>;
>> - status = "disabled";
>> - #address-cells = <1>;
>> - #size-cells = <0>;
>> - };
>> -
>> - gic: interrupt-controller@01c81000 {
>> - compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
>> - reg = <0x01c81000 0x1000>,
>> - <0x01c82000 0x1000>,
>> - <0x01c84000 0x2000>,
>> - <0x01c86000 0x2000>;
>> - interrupt-controller;
>> - #interrupt-cells = <3>;
>> - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>> - };
>> -
>> - rtc: rtc@01f00000 {
>> - compatible = "allwinner,sun6i-a31-rtc";
>> - reg = <0x01f00000 0x54>;
>> - interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
>> - <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
>> - };
>> -
>> - prcm@01f01400 {
>> - compatible = "allwinner,sun8i-a23-prcm";
>> - reg = <0x01f01400 0x200>;
>> -
>> - ar100: ar100_clk {
>> - compatible = "fixed-factor-clock";
>> - #clock-cells = <0>;
>> - clock-div = <1>;
>> - clock-mult = <1>;
>> - clocks = <&osc24M>;
>> - clock-output-names = "ar100";
>> - };
>> -
>> - ahb0: ahb0_clk {
>> - compatible = "fixed-factor-clock";
>> - #clock-cells = <0>;
>> - clock-div = <1>;
>> - clock-mult = <1>;
>> - clocks = <&ar100>;
>> - clock-output-names = "ahb0";
>> - };
>> -
>> - apb0: apb0_clk {
>> - compatible = "allwinner,sun8i-a23-apb0-clk";
>> - #clock-cells = <0>;
>> - clocks = <&ahb0>;
>> - clock-output-names = "apb0";
>> - };
>> -
>> - apb0_gates: apb0_gates_clk {
>> - compatible = "allwinner,sun8i-a23-apb0-gates-clk";
>> - #clock-cells = <1>;
>> - clocks = <&apb0>;
>> - clock-output-names = "apb0_pio", "apb0_timer",
>> - "apb0_rsb", "apb0_uart",
>> - "apb0_i2c";
>> - };
>> -
>> - apb0_rst: apb0_rst {
>> - compatible = "allwinner,sun6i-a31-clock-reset";
>> - #reset-cells = <1>;
>> - };
>> - };
>> -
>> - cpucfg@01f01c00 {
>> - compatible = "allwinner,sun8i-a23-cpuconfig";
>> - reg = <0x01f01c00 0x300>;
>> - };
>> -
>> - r_uart: serial@01f02800 {
>> - compatible = "snps,dw-apb-uart";
>> - reg = <0x01f02800 0x400>;
>> - interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
>> - reg-shift = <2>;
>> - reg-io-width = <4>;
>> - clocks = <&apb0_gates 4>;
>> - resets = <&apb0_rst 4>;
>> - status = "disabled";
>> - };
>> -
>> - r_pio: pinctrl@01f02c00 {
>> - compatible = "allwinner,sun8i-a23-r-pinctrl";
>> - reg = <0x01f02c00 0x400>;
>> - interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
>> - clocks = <&apb0_gates 0>;
>> - resets = <&apb0_rst 0>;
>> - gpio-controller;
>> - interrupt-controller;
>> - #address-cells = <1>;
>> - #size-cells = <0>;
>> - #gpio-cells = <3>;
>> -
>> - r_uart_pins_a: r_uart@0 {
>> - allwinner,pins = "PL2", "PL3";
>> - allwinner,function = "s_uart";
>> - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> - };
>> - };
>> };
>> };
>> diff --git a/arch/arm/boot/dts/sun8i.dtsi b/arch/arm/boot/dts/sun8i.dtsi
>> new file mode 100644
>> index 0000000..cf481e5
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/sun8i.dtsi
>> @@ -0,0 +1,481 @@
>> +/*
>> + * Copyright 2014 Chen-Yu Tsai
>> + *
>> + * Chen-Yu Tsai <wens@csie.org>
>> + *
>> + * This file is dual-licensed: you can use it either under the terms
>> + * of the GPL or the X11 license, at your option. Note that this dual
>> + * licensing only applies to this file, and not this project as a
>> + * whole.
>> + *
>> + * a) This file is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of the
>> + * License, or (at your option) any later version.
>> + *
>> + * This file is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + *
>> + * Or, alternatively,
>> + *
>> + * b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated documentation
>> + * files (the "Software"), to deal in the Software without
>> + * restriction, including without limitation the rights to use,
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following
>> + * conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be
>> + * included in all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> + */
>> +
>> +#include "skeleton.dtsi"
>> +
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>> +#include <dt-bindings/pinctrl/sun4i-a10.h>
>> +
>> +/ {
>> + interrupt-parent = <&gic>;
>> +
>> + chosen {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + framebuffer@0 {
>> + compatible = "allwinner,simple-framebuffer",
>> + "simple-framebuffer";
>> + allwinner,pipeline = "de_be0-lcd0";
>> + clocks = <&pll6 0>;
>> + status = "disabled";
>> + };
>> + };
>> +
>> + timer {
>> + compatible = "arm,armv7-timer";
>> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
>> + clock-frequency = <24000000>;
>> + arm,cpu-registers-not-fw-configured;
>> + };
>> +
>> + clocks {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + osc24M: osc24M_clk {
>> + #clock-cells = <0>;
>> + compatible = "fixed-clock";
>> + clock-frequency = <24000000>;
>> + clock-output-names = "osc24M";
>> + };
>> +
>> + osc32k: osc32k_clk {
>> + #clock-cells = <0>;
>> + compatible = "fixed-clock";
>> + clock-frequency = <32768>;
>> + clock-output-names = "osc32k";
>> + };
>> +
>> + pll1: clk@01c20000 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun8i-a23-pll1-clk";
>> + reg = <0x01c20000 0x4>;
>> + clocks = <&osc24M>;
>> + clock-output-names = "pll1";
>> + };
>> +
>> + pll6: clk@01c20028 {
>> + #clock-cells = <1>;
>> + compatible = "allwinner,sun6i-a31-pll6-clk";
>> + reg = <0x01c20028 0x4>;
>> + clocks = <&osc24M>;
>> + clock-output-names = "pll6", "pll6x2";
>> + };
>> +
>> + cpu: cpu_clk@01c20050 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-cpu-clk";
>> + reg = <0x01c20050 0x4>;
>> +
>> + /*
>> + * PLL1 is listed twice here.
>> + * While it looks suspicious, it's actually documented
>> + * that way both in the datasheet and in the code from
>> + * Allwinner.
>> + */
>> + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
>> + clock-output-names = "cpu";
>> + };
>> +
>> +
>> + ahb1: ahb1_clk@01c20054 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun6i-a31-ahb1-clk";
>> + reg = <0x01c20054 0x4>;
>> + clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
>> + clock-output-names = "ahb1";
>> + };
>> +
>> + apb1: apb1_clk@01c20054 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-apb0-clk";
>> + reg = <0x01c20054 0x4>;
>> + clocks = <&ahb1>;
>> + clock-output-names = "apb1";
>> + };
>> +
>> + mmc0_clk: clk@01c20088 {
>> + #clock-cells = <1>;
>> + compatible = "allwinner,sun4i-a10-mmc-clk";
>> + reg = <0x01c20088 0x4>;
>> + clocks = <&osc24M>, <&pll6 0>;
>> + clock-output-names = "mmc0",
>> + "mmc0_output",
>> + "mmc0_sample";
>> + };
>> +
>> + mmc1_clk: clk@01c2008c {
>> + #clock-cells = <1>;
>> + compatible = "allwinner,sun4i-a10-mmc-clk";
>> + reg = <0x01c2008c 0x4>;
>> + clocks = <&osc24M>, <&pll6 0>;
>> + clock-output-names = "mmc1",
>> + "mmc1_output",
>> + "mmc1_sample";
>> + };
>> +
>> + mmc2_clk: clk@01c20090 {
>> + #clock-cells = <1>;
>> + compatible = "allwinner,sun4i-a10-mmc-clk";
>> + reg = <0x01c20090 0x4>;
>> + clocks = <&osc24M>, <&pll6 0>;
>> + clock-output-names = "mmc2",
>> + "mmc2_output",
>> + "mmc2_sample";
>> + };
>> +
>> + };
>> +
>> + soc@01c00000 {
>> + compatible = "simple-bus";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> +
>> + mmc0: mmc@01c0f000 {
>> + compatible = "allwinner,sun5i-a13-mmc";
>> + reg = <0x01c0f000 0x1000>;
>> + clocks = <&ahb1_gates 8>,
>> + <&mmc0_clk 0>,
>> + <&mmc0_clk 1>,
>> + <&mmc0_clk 2>;
>> + clock-names = "ahb",
>> + "mmc",
>> + "output",
>> + "sample";
>> + resets = <&ahb1_rst 8>;
>> + reset-names = "ahb";
>> + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + mmc1: mmc@01c10000 {
>> + compatible = "allwinner,sun5i-a13-mmc";
>> + reg = <0x01c10000 0x1000>;
>> + clocks = <&ahb1_gates 9>,
>> + <&mmc1_clk 0>,
>> + <&mmc1_clk 1>,
>> + <&mmc1_clk 2>;
>> + clock-names = "ahb",
>> + "mmc",
>> + "output",
>> + "sample";
>> + resets = <&ahb1_rst 9>;
>> + reset-names = "ahb";
>> + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + mmc2: mmc@01c11000 {
>> + compatible = "allwinner,sun5i-a13-mmc";
>> + reg = <0x01c11000 0x1000>;
>> + clocks = <&ahb1_gates 10>,
>> + <&mmc2_clk 0>,
>> + <&mmc2_clk 1>,
>> + <&mmc2_clk 2>;
>> + clock-names = "ahb",
>> + "mmc",
>> + "output",
>> + "sample";
>> + resets = <&ahb1_rst 10>;
>> + reset-names = "ahb";
>> + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + pio: pinctrl@01c20800 {
>> + reg = <0x01c20800 0x400>;
>> + clocks = <&apb1_gates 5>;
>> + gpio-controller;
>> + interrupt-controller;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + #gpio-cells = <3>;
>> +
>> + mmc0_pins_a: mmc0@0 {
>> + allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
>> + allwinner,function = "mmc0";
>> + allwinner,drive = <SUN4I_PINCTRL_30_MA>;
>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> + };
>> +
>> + mmc1_pins_a: mmc1@0 {
>> + allwinner,pins = "PG0","PG1","PG2","PG3","PG4","PG5";
>> + allwinner,function = "mmc1";
>> + allwinner,drive = <SUN4I_PINCTRL_30_MA>;
>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> + };
>> + };
>> +
>> + ahb1_rst: reset@01c202c0 {
>> + #reset-cells = <1>;
>> + compatible = "allwinner,sun6i-a31-clock-reset";
>> + reg = <0x01c202c0 0xc>;
>> + };
>> +
>> + apb1_rst: reset@01c202d0 {
>> + #reset-cells = <1>;
>> + compatible = "allwinner,sun6i-a31-clock-reset";
>> + reg = <0x01c202d0 0x4>;
>> + };
>> +
>> + apb2_rst: reset@01c202d8 {
>> + #reset-cells = <1>;
>> + compatible = "allwinner,sun6i-a31-clock-reset";
>> + reg = <0x01c202d8 0x4>;
>> + };
>> +
>> + timer@01c20c00 {
>> + compatible = "allwinner,sun4i-a10-timer";
>> + reg = <0x01c20c00 0xa0>;
>> + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&osc24M>;
>> + };
>> +
>> + wdt0: watchdog@01c20ca0 {
>> + compatible = "allwinner,sun6i-a31-wdt";
>> + reg = <0x01c20ca0 0x20>;
>> + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
>> + };
>> +
>> + uart0: serial@01c28000 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x01c28000 0x400>;
>> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + clocks = <&apb2_gates 16>;
>> + resets = <&apb2_rst 16>;
>> + dmas = <&dma 6>, <&dma 6>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + };
>> +
>> + uart1: serial@01c28400 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x01c28400 0x400>;
>> + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + clocks = <&apb2_gates 17>;
>> + resets = <&apb2_rst 17>;
>> + dmas = <&dma 7>, <&dma 7>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + };
>> +
>> + uart2: serial@01c28800 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x01c28800 0x400>;
>> + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + clocks = <&apb2_gates 18>;
>> + resets = <&apb2_rst 18>;
>> + dmas = <&dma 8>, <&dma 8>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + };
>> +
>> + uart3: serial@01c28c00 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x01c28c00 0x400>;
>> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + clocks = <&apb2_gates 19>;
>> + resets = <&apb2_rst 19>;
>> + dmas = <&dma 9>, <&dma 9>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + };
>> +
>> + i2c0: i2c@01c2ac00 {
>> + compatible = "allwinner,sun6i-a31-i2c";
>> + reg = <0x01c2ac00 0x400>;
>> + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&apb2_gates 0>;
>> + resets = <&apb2_rst 0>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + i2c1: i2c@01c2b000 {
>> + compatible = "allwinner,sun6i-a31-i2c";
>> + reg = <0x01c2b000 0x400>;
>> + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&apb2_gates 1>;
>> + resets = <&apb2_rst 1>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + i2c2: i2c@01c2b400 {
>> + compatible = "allwinner,sun6i-a31-i2c";
>> + reg = <0x01c2b400 0x400>;
>> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&apb2_gates 2>;
>> + resets = <&apb2_rst 2>;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + gic: interrupt-controller@01c81000 {
>> + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
>> + reg = <0x01c81000 0x1000>,
>> + <0x01c82000 0x1000>,
>> + <0x01c84000 0x2000>,
>> + <0x01c86000 0x2000>;
>> + interrupt-controller;
>> + #interrupt-cells = <3>;
>> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>> + };
>> +
>> + rtc: rtc@01f00000 {
>> + compatible = "allwinner,sun6i-a31-rtc";
>> + reg = <0x01f00000 0x54>;
>> + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
>> + };
>> +
>> + prcm@01f01400 {
>> + compatible = "allwinner,sun8i-a23-prcm";
>> + reg = <0x01f01400 0x200>;
>> +
>> + ar100: ar100_clk {
>> + compatible = "fixed-factor-clock";
>> + #clock-cells = <0>;
>> + clock-div = <1>;
>> + clock-mult = <1>;
>> + clocks = <&osc24M>;
>> + clock-output-names = "ar100";
>> + };
>> +
>> + ahb0: ahb0_clk {
>> + compatible = "fixed-factor-clock";
>> + #clock-cells = <0>;
>> + clock-div = <1>;
>> + clock-mult = <1>;
>> + clocks = <&ar100>;
>> + clock-output-names = "ahb0";
>> + };
>> +
>> + apb0: apb0_clk {
>> + compatible = "allwinner,sun8i-a23-apb0-clk";
>> + #clock-cells = <0>;
>> + clocks = <&ahb0>;
>> + clock-output-names = "apb0";
>> + };
>> +
>> + apb0_gates: apb0_gates_clk {
>> + compatible = "allwinner,sun8i-a23-apb0-gates-clk";
>> + #clock-cells = <1>;
>> + clocks = <&apb0>;
>> + clock-output-names = "apb0_pio", "apb0_timer",
>> + "apb0_rsb", "apb0_uart",
>> + "apb0_i2c";
>> + };
>> +
>> + apb0_rst: apb0_rst {
>> + compatible = "allwinner,sun6i-a31-clock-reset";
>> + #reset-cells = <1>;
>> + };
>> + };
>> +
>> + cpucfg@01f01c00 {
>> + compatible = "allwinner,sun8i-a23-cpuconfig";
>> + reg = <0x01f01c00 0x300>;
>> + };
>> +
>> + r_uart: serial@01f02800 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x01f02800 0x400>;
>> + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
>> + reg-shift = <2>;
>> + reg-io-width = <4>;
>> + clocks = <&apb0_gates 4>;
>> + resets = <&apb0_rst 4>;
>> + status = "disabled";
>> + };
>> +
>> + r_pio: pinctrl@01f02c00 {
>> + compatible = "allwinner,sun8i-a23-r-pinctrl";
>> + reg = <0x01f02c00 0x400>;
>> + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&apb0_gates 0>;
>> + resets = <&apb0_rst 0>;
>> + gpio-controller;
>> + interrupt-controller;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + #gpio-cells = <3>;
>> +
>> + r_uart_pins_a: r_uart@0 {
>> + allwinner,pins = "PL2", "PL3";
>> + allwinner,function = "s_uart";
>> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> + };
>> + };
>> + };
>> +};
>
> And moves stuff between the A23 DTSI and sun8i DTSI.
>
> All these things should be in separate patches.
>
> Apart from that, as I told on IRC, I'd really like to have the H3
> support merged and support for the A33 and H3 settle down a bit before
> we create such a DTSI.
>
> There's a lot of IPs that are enabled here that I'm pretty sure have
> never been tested and/or even apply to the H3 and/or A33 (PRCM, arch
> timers, A10 timers, etc.)
>
> So let's merge everything in separate DTSI, and then, once we have a
> clear view of what needs what, we will create a common DTSI.
Okie, I'll drop this patch, and use separate dtsi for A33 for now.
>
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux, Kernel and Android engineering
> http://free-electrons.com
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 0/6] Introduce Allwinner A33 support
2015-05-10 6:46 [PATCH 0/6] Introduce Allwinner A33 support Vishnu Patekar
` (5 preceding siblings ...)
2015-05-10 6:46 ` [PATCH 6/6] ARM: dts: sun8i: Add ET-Q8 A33 support Vishnu Patekar
@ 2015-05-12 11:37 ` Linus Walleij
6 siblings, 0 replies; 30+ messages in thread
From: Linus Walleij @ 2015-05-12 11:37 UTC (permalink / raw)
To: Vishnu Patekar
Cc: Maxime Ripard, Emilio Lopez, Rob Herring, Hans de Goede,
Chen-Yu Tsai, jenskuske, Arnd Bergmann, linux-arm-kernel,
linux-kernel, linux-sunxi, devicetree
On Sun, May 10, 2015 at 8:46 AM, Vishnu Patekar
<vishnupatekar0510@gmail.com> wrote:
> Hello everyone,
>
> This patch series introduces basic kernel support for Allwinner's A33 SoC,
I'll wait for a new set addressing Paul's comments before commiting
the pinctrl portions. Add Maxime's ACKs to the patches so I know
he's verified them.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 3/6] clk: sunxi: Add A33 clock for compilation
2015-05-11 8:53 ` Vishnu Patekar
@ 2015-07-17 8:57 ` Chen-Yu Tsai
2015-07-17 9:09 ` Maxime Ripard
0 siblings, 1 reply; 30+ messages in thread
From: Chen-Yu Tsai @ 2015-07-17 8:57 UTC (permalink / raw)
To: Vishnu Patekar
Cc: Maxime Ripard, Emilio Lopez, Linus Walleij, robh+dt,
Hans de Goede, Chen-Yu Tsai, Jens Kuske, Arnd Bergmann,
linux-arm-kernel, linux-kernel, linux-sunxi, devicetree
Hi Vishnu,
This patch did not make v4.2-rc1.
A33 support requires this patch. Otherwise the clock tree
is absent and nothing works.
On Mon, May 11, 2015 at 4:53 PM, Vishnu Patekar
<vishnupatekar0510@gmail.com> wrote:
> Hi,
>
> On Sun, May 10, 2015 at 3:47 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
>> Hi,
>>
>> On Sun, May 10, 2015 at 12:16:20PM +0530, Vishnu Patekar wrote:
>>> A33 clock control unit is similar to A23.
>>>
>>> A33 specific clocks are not yet implemented, added CLK_OF_DECLARE
>>> to get it compiled for A33.
>>
>> That commit log doesn't make any sense.
>>
>> What you're doing isn't about whether or not that will be compiled,
>> but whether you're registering the clocks and which clocks you
>> protect.
> Actually, It's just registering the a33 clocks and reusing a23 code.
> nothing to do with compile. I'll correct it in next patch version.
>>
>>> Signed-off-by: VishnuPatekar <vishnupatekar0510@gmail.com>
>>
>> Isn't it supposed to have a space in the middle of your name, just
>> like you have in your mail address?
> Yes, There should be space.
>>
>> Thanks,
>> Maxime
>>
>> --
>> Maxime Ripard, Free Electrons
>> Embedded Linux, Kernel and Android engineering
>> http://free-electrons.com
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 3/6] clk: sunxi: Add A33 clock for compilation
2015-07-17 8:57 ` Chen-Yu Tsai
@ 2015-07-17 9:09 ` Maxime Ripard
2015-07-17 9:13 ` Chen-Yu Tsai
0 siblings, 1 reply; 30+ messages in thread
From: Maxime Ripard @ 2015-07-17 9:09 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: Vishnu Patekar, Emilio Lopez, Linus Walleij, robh+dt,
Hans de Goede, Jens Kuske, Arnd Bergmann, linux-arm-kernel,
linux-kernel, linux-sunxi, devicetree
[-- Attachment #1: Type: text/plain, Size: 383 bytes --]
Hi,
On Fri, Jul 17, 2015 at 04:57:11PM +0800, Chen-Yu Tsai wrote:
> Hi Vishnu,
>
> This patch did not make v4.2-rc1.
>
> A33 support requires this patch. Otherwise the clock tree
> is absent and nothing works.
It got delayed and is in v4.2-rc2.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 3/6] clk: sunxi: Add A33 clock for compilation
2015-07-17 9:09 ` Maxime Ripard
@ 2015-07-17 9:13 ` Chen-Yu Tsai
0 siblings, 0 replies; 30+ messages in thread
From: Chen-Yu Tsai @ 2015-07-17 9:13 UTC (permalink / raw)
To: Maxime Ripard
Cc: Chen-Yu Tsai, Vishnu Patekar, Emilio Lopez, Linus Walleij,
robh+dt, Hans de Goede, Jens Kuske, Arnd Bergmann,
linux-arm-kernel, linux-kernel, linux-sunxi, devicetree
On Fri, Jul 17, 2015 at 5:09 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Hi,
>
> On Fri, Jul 17, 2015 at 04:57:11PM +0800, Chen-Yu Tsai wrote:
>> Hi Vishnu,
>>
>> This patch did not make v4.2-rc1.
>>
>> A33 support requires this patch. Otherwise the clock tree
>> is absent and nothing works.
>
> It got delayed and is in v4.2-rc2.
Ah, it's in the A33 machine support patch.
Not where I was expecting it.
Thanks.
ChenYu
^ permalink raw reply [flat|nested] 30+ messages in thread
end of thread, other threads:[~2015-07-17 9:14 UTC | newest]
Thread overview: 30+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-05-10 6:46 [PATCH 0/6] Introduce Allwinner A33 support Vishnu Patekar
2015-05-10 6:46 ` [PATCH 1/6] ARM: sunxi: Add Machine support for A33 Vishnu Patekar
2015-05-10 8:49 ` Hans de Goede
2015-05-10 10:33 ` Maxime Ripard
2015-05-11 8:52 ` Vishnu Patekar
2015-05-10 6:46 ` [PATCH 2/6] pinctrl: sunxi: add allwinner A33 PIO controller support Vishnu Patekar
2015-05-10 8:50 ` Hans de Goede
2015-05-10 9:00 ` Chen-Yu Tsai
2015-05-10 9:10 ` Hans de Goede
2015-05-10 10:34 ` Maxime Ripard
2015-05-11 7:22 ` Paul Bolle
2015-05-10 6:46 ` [PATCH 3/6] clk: sunxi: Add A33 clock for compilation Vishnu Patekar
2015-05-10 10:17 ` Maxime Ripard
2015-05-11 8:53 ` Vishnu Patekar
2015-07-17 8:57 ` Chen-Yu Tsai
2015-07-17 9:09 ` Maxime Ripard
2015-07-17 9:13 ` Chen-Yu Tsai
2015-05-10 6:46 ` [PATCH 4/6] ARM: dts: sunxi: add common sun8i dtsi Vishnu Patekar
2015-05-10 8:52 ` Hans de Goede
2015-05-10 10:41 ` Maxime Ripard
2015-05-11 11:18 ` Vishnu Patekar
2015-05-10 6:46 ` [PATCH 5/6] ARM: dts: sunxi: Add Allwinner A33 DTSI Vishnu Patekar
2015-05-10 8:53 ` Hans de Goede
2015-05-10 9:33 ` Vishnu Patekar
2015-05-10 9:54 ` Hans de Goede
2015-05-10 10:43 ` Maxime Ripard
2015-05-10 6:46 ` [PATCH 6/6] ARM: dts: sun8i: Add ET-Q8 A33 support Vishnu Patekar
2015-05-10 8:54 ` Hans de Goede
2015-05-10 10:47 ` Maxime Ripard
2015-05-12 11:37 ` [PATCH 0/6] Introduce Allwinner " Linus Walleij
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