[PATCH_V3 0/2] mtd: nand: jz4780: Add nand and bch driver

[PATCH_V3 0/2] mtd: nand: jz4780: Add nand and bch driver

[Zubair Lutfullah Kakakhel]

Hi,

Two patches based on 4.0-rc6 that add NAND and BCH controller
drivers for the Ingenic JZ4780 SoC.

Hope these can make it in time for 4.1.

Tested on the MIPS Creator CI20.

Core JZ4780 support is still in-flight.

Review and feedback welcome.

V2 - > V3
Rebase to 4.0-rc6
Binding changes and fixes based on feedback by Brian Norris (Thank-you)

V1 - > V2
Fixed module license macros
Rebase to 4.0-rc3

Thanks,
ZubairLK

Alex Smith (2):
  dt-bindings: binding for jz4780-{nand,bch}
  mtd: nand: jz4780: driver for NAND devices on JZ4780 SoCs

 .../bindings/mtd/ingenic,jz4780-nand.txt           |  57 ++++
 drivers/mtd/nand/Kconfig                           |   7 +
 drivers/mtd/nand/Makefile                          |   1 +
 drivers/mtd/nand/jz4780_bch.c                      | 353 +++++++++++++++++++
 drivers/mtd/nand/jz4780_bch.h                      |  42 +++
 drivers/mtd/nand/jz4780_nand.c                     | 376 +++++++++++++++++++++
 6 files changed, 836 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt
 create mode 100644 drivers/mtd/nand/jz4780_bch.c
 create mode 100644 drivers/mtd/nand/jz4780_bch.h
 create mode 100644 drivers/mtd/nand/jz4780_nand.c

-- 
1.9.1

[PATCH_V3 1/2] dt-bindings: binding for jz4780-{nand,bch}

[Zubair Lutfullah Kakakhel]

From: Alex Smith <alex.smith@imgtec.com>

Add DT bindings for NAND devices connected to the NEMC on JZ4780 SoCs,
as well as the hardware BCH controller, used by the jz4780_{nand,bch}
drivers.

Signed-off-by: Alex Smith <alex@alex-smith.me.uk>
Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>

---
V2 - > V3
Rebase to 4.0-rc6
Changed ingenic,ecc-size to common nand-ecc-step-size
Changed ingenic,ecc-strength to common nand-ecc-strength
Changed ingenic,busy-gpio to common rb-gpios
Changed ingenic,wp-gpio to common wp-gpios

V1 - > V2
Rebase to 4.0-rc3
---
 .../bindings/mtd/ingenic,jz4780-nand.txt           | 57 ++++++++++++++++++++++
 1 file changed, 57 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt

diff --git a/Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt b/Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt
new file mode 100644
index 0000000..1e8e2eef
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt
@@ -0,0 +1,57 @@
+* Ingenic JZ4780 NAND/BCH
+
+This file documents the device tree bindings for NAND flash devices on the
+JZ4780. NAND devices are connected to the NEMC controller (described in
+memory-controllers/ingenic,jz4780-nemc.txt), and thus NAND device nodes must
+be children of the NEMC node.
+
+Required NAND device properties:
+- compatible: Should be set to "ingenic,jz4780-nand".
+- reg: For each bank with a NAND chip attached, should specify a bank number,
+  an offset of 0 and a size of 0x1000000 (i.e. the whole NEMC bank).
+
+Optional NAND device properties:
+- ingenic,bch-device: To make use of the hardware BCH controller, this property
+  must contain a phandle for the BCH controller node. The required properties
+  for this node are described below. If this is not specified, software BCH
+  will be used instead.
+- nand-ecc-step-size: ECC block size in bytes.
+- nand-ecc-strength: ECC strength (max number of correctable bits).
+- rb-gpios: GPIO specifier for the busy pin.
+- wp-gpios: GPIO specifier for the write protect pin.
+
+Example:
+
+nemc: nemc@13410000 {
+	...
+
+	nand: nand@1 {
+		compatible = "ingenic,jz4780-nand";
+		reg = <1 0 0x1000000>;	/* Bank 1 */
+
+		ingenic,bch-device = <&bch>;
+		nand-ecc-step-size = <1024>;
+		nand-ecc-strength = <24>;
+
+		rb-gpios = <&gpa 20 GPIO_ACTIVE_LOW>;
+		wp-gpios = <&gpf 22 GPIO_ACTIVE_LOW>;
+	};
+};
+
+The BCH controller is a separate SoC component used for error correction on
+NAND devices. The following is a description of the device properties for a
+BCH controller.
+
+Required BCH properties:
+- compatible: Should be set to "ingenic,jz4780-bch".
+- reg: Should specify the BCH controller registers location and length.
+- clocks: Clock for the BCH controller.
+
+Example:
+
+bch: bch@134d0000 {
+	compatible = "ingenic,jz4780-bch";
+	reg = <0x134d0000 0x10000>;
+
+	clocks = <&cgu JZ4780_CLK_BCH>;
+};
-- 
1.9.1

[PATCH_V3 2/2] mtd: nand: jz4780: driver for NAND devices on JZ4780 SoCs

[Zubair Lutfullah Kakakhel]

From: Alex Smith <alex.smith@imgtec.com>

Add a driver for NAND devices connected to the NEMC on JZ4780 SoCs, as
well as the hardware BCH controller. DMA is not currently implemented.

While older 47xx SoCs also have a BCH controller, they are incompatible
with the one in the 4780 due to differing register/bit positions, which
would make implementing a common driver for them quite messy.

Signed-off-by: Alex Smith <alex@alex-smith.me.uk>
Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>

---
V2 -> V3
Rebase to 4.0-rc6
Reflect binding changes
get/put_device in bch get/release
Removed empty .remove() callback
Removed .owner
Set mtd->dev.parent

V1 - > V2
Fixed module license macro
Rebase to 4.0-rc3

Tested on MIPS Creator CI20
---
 drivers/mtd/nand/Kconfig       |   7 +
 drivers/mtd/nand/Makefile      |   1 +
 drivers/mtd/nand/jz4780_bch.c  | 353 ++++++++++++++++++++++++++++++++++++++
 drivers/mtd/nand/jz4780_bch.h  |  42 +++++
 drivers/mtd/nand/jz4780_nand.c | 376 +++++++++++++++++++++++++++++++++++++++++
 5 files changed, 779 insertions(+)
 create mode 100644 drivers/mtd/nand/jz4780_bch.c
 create mode 100644 drivers/mtd/nand/jz4780_bch.h
 create mode 100644 drivers/mtd/nand/jz4780_nand.c

diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 5897d8d..1d6f98a 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -503,6 +503,13 @@ config MTD_NAND_JZ4740
 	help
 		Enables support for NAND Flash on JZ4740 SoC based boards.
 
+config MTD_NAND_JZ4780
+	tristate "Support for NAND on JZ4780 SoC"
+	depends on MACH_JZ4780 && JZ4780_NEMC
+	help
+	  Enables support for NAND Flash connected to the NEMC on JZ4780 SoC
+	  based boards, using the BCH controller for hardware error correction.
+
 config MTD_NAND_FSMC
 	tristate "Support for NAND on ST Micros FSMC"
 	depends on PLAT_SPEAR || ARCH_NOMADIK || ARCH_U8500 || MACH_U300
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 582bbd05..7c1ebca 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -47,6 +47,7 @@ obj-$(CONFIG_MTD_NAND_NUC900)		+= nuc900_nand.o
 obj-$(CONFIG_MTD_NAND_MPC5121_NFC)	+= mpc5121_nfc.o
 obj-$(CONFIG_MTD_NAND_RICOH)		+= r852.o
 obj-$(CONFIG_MTD_NAND_JZ4740)		+= jz4740_nand.o
+obj-$(CONFIG_MTD_NAND_JZ4780)		+= jz4780_nand.o jz4780_bch.o
 obj-$(CONFIG_MTD_NAND_GPMI_NAND)	+= gpmi-nand/
 obj-$(CONFIG_MTD_NAND_XWAY)		+= xway_nand.o
 obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH)	+= bcm47xxnflash/
diff --git a/drivers/mtd/nand/jz4780_bch.c b/drivers/mtd/nand/jz4780_bch.c
new file mode 100644
index 0000000..7e2481f
--- /dev/null
+++ b/drivers/mtd/nand/jz4780_bch.c
@@ -0,0 +1,353 @@
+/*
+ * JZ4780 BCH controller
+ *
+ * Copyright (c) 2015 Imagination Technologies
+ * Author: Alex Smith <alex@alex-smith.me.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+
+#include "jz4780_bch.h"
+
+#define BCH_BHCR			0x0
+#define BCH_BHCCR			0x8
+#define BCH_BHCNT			0xc
+#define BCH_BHDR			0x10
+#define BCH_BHPAR0			0x14
+#define BCH_BHERR0			0x84
+#define BCH_BHINT			0x184
+#define BCH_BHINTES			0x188
+#define BCH_BHINTEC			0x18c
+#define BCH_BHINTE			0x190
+
+#define BCH_BHCR_BSEL_SHIFT		4
+#define BCH_BHCR_BSEL_MASK		(0x7f << BCH_BHCR_BSEL_SHIFT)
+#define BCH_BHCR_ENCE			BIT(2)
+#define BCH_BHCR_INIT			BIT(1)
+#define BCH_BHCR_BCHE			BIT(0)
+
+#define BCH_BHCNT_PARITYSIZE_SHIFT	16
+#define BCH_BHCNT_PARITYSIZE_MASK	(0x7f << BCH_BHCNT_PARITYSIZE_SHIFT)
+#define BCH_BHCNT_BLOCKSIZE_SHIFT	0
+#define BCH_BHCNT_BLOCKSIZE_MASK	(0x7ff << BCH_BHCNT_BLOCKSIZE_SHIFT)
+
+#define BCH_BHERR_MASK_SHIFT		16
+#define BCH_BHERR_MASK_MASK		(0xffff << BCH_BHERR_MASK_SHIFT)
+#define BCH_BHERR_INDEX_SHIFT		0
+#define BCH_BHERR_INDEX_MASK		(0x7ff << BCH_BHERR_INDEX_SHIFT)
+
+#define BCH_BHINT_ERRC_SHIFT		24
+#define BCH_BHINT_ERRC_MASK		(0x7f << BCH_BHINT_ERRC_SHIFT)
+#define BCH_BHINT_TERRC_SHIFT		16
+#define BCH_BHINT_TERRC_MASK		(0x7f << BCH_BHINT_TERRC_SHIFT)
+#define BCH_BHINT_DECF			BIT(3)
+#define BCH_BHINT_ENCF			BIT(2)
+#define BCH_BHINT_UNCOR			BIT(1)
+#define BCH_BHINT_ERR			BIT(0)
+
+#define BCH_CLK_RATE			(200 * 1000 * 1000)
+
+/* Timeout for BCH calculation/correction in milliseconds. */
+#define BCH_TIMEOUT			100
+
+struct jz4780_bch {
+	void __iomem *base;
+	struct clk *clk;
+};
+
+static void jz4780_bch_init(struct jz4780_bch *bch,
+			    struct jz4780_bch_params *params, bool encode)
+{
+	uint32_t reg;
+
+	/* Clear interrupt status. */
+	writel(readl(bch->base + BCH_BHINT), bch->base + BCH_BHINT);
+
+	/* Set up BCH count register. */
+	reg = params->size << BCH_BHCNT_BLOCKSIZE_SHIFT;
+	reg |= params->bytes << BCH_BHCNT_PARITYSIZE_SHIFT;
+	writel(reg, bch->base + BCH_BHCNT);
+
+	/* Initialise and enable BCH. */
+	reg = BCH_BHCR_BCHE | BCH_BHCR_INIT;
+	reg |= params->strength << BCH_BHCR_BSEL_SHIFT;
+	if (encode)
+		reg |= BCH_BHCR_ENCE;
+	writel(reg, bch->base + BCH_BHCR);
+}
+
+static void jz4780_bch_disable(struct jz4780_bch *bch)
+{
+	writel(readl(bch->base + BCH_BHINT), bch->base + BCH_BHINT);
+	writel(BCH_BHCR_BCHE, bch->base + BCH_BHCCR);
+}
+
+static void jz4780_bch_write_data(struct jz4780_bch *bch, const void *buf,
+				  size_t size)
+{
+	size_t size32 = size / sizeof(uint32_t);
+	size_t size8 = size & (sizeof(uint32_t) - 1);
+	const uint32_t *src32;
+	const uint8_t *src8;
+
+	src32 = (const uint32_t *)buf;
+	while (size32--)
+		writel(*src32++, bch->base + BCH_BHDR);
+
+	src8 = (const uint8_t *)src32;
+	while (size8--)
+		writeb(*src8++, bch->base + BCH_BHDR);
+}
+
+static void jz4780_bch_read_parity(struct jz4780_bch *bch, void *buf,
+				   size_t size)
+{
+	size_t size32 = size / sizeof(uint32_t);
+	size_t size8 = size & (sizeof(uint32_t) - 1);
+	uint32_t *dest32;
+	uint8_t *dest8;
+	uint32_t val, offset = 0;
+
+	dest32 = (uint32_t *)buf;
+	while (size32--) {
+		*dest32++ = readl(bch->base + BCH_BHPAR0 + offset);
+		offset += sizeof(uint32_t);
+	}
+
+	dest8 = (uint8_t *)dest32;
+	val = readl(bch->base + BCH_BHPAR0 + offset);
+	switch (size8) {
+	case 3:
+		dest8[2] = (val >> 16) & 0xff;
+	case 2:
+		dest8[1] = (val >> 8) & 0xff;
+	case 1:
+		dest8[0] = val & 0xff;
+		break;
+	}
+}
+
+static bool jz4780_bch_wait_complete(struct jz4780_bch *bch, unsigned int irq,
+				     uint32_t *status)
+{
+	unsigned long timeout = jiffies + msecs_to_jiffies(BCH_TIMEOUT);
+	uint32_t reg;
+
+	/*
+	 * While we could use use interrupts here and sleep until the operation
+	 * completes, the controller works fairly quickly (usually a few
+	 * microseconds), so the overhead of sleeping until we get an interrupt
+	 * actually quite noticably decreases performance.
+	 */
+	do {
+		reg = readl(bch->base + BCH_BHINT);
+		if ((reg & irq) == irq) {
+			if (status)
+				*status = reg;
+
+			writel(reg, bch->base + BCH_BHINT);
+			return true;
+		}
+
+		cond_resched();
+	} while (time_before(jiffies, timeout));
+
+	return false;
+}
+
+/**
+ * jz4780_bch_calculate() - calculate ECC for a data buffer
+ * @dev: BCH device.
+ * @params: BCH parameters.
+ * @buf: input buffer with raw data.
+ * @ecc_code: output buffer with ECC.
+ *
+ * Return: 0 on success, -ETIMEDOUT if timed out while waiting for BCH
+ * controller.
+ */
+int jz4780_bch_calculate(struct device *dev, struct jz4780_bch_params *params,
+			 const uint8_t *buf, uint8_t *ecc_code)
+{
+	struct jz4780_bch *bch = dev_get_drvdata(dev);
+	int ret = 0;
+
+	jz4780_bch_init(bch, params, true);
+	jz4780_bch_write_data(bch, buf, params->size);
+
+	if (jz4780_bch_wait_complete(bch, BCH_BHINT_ENCF, NULL)) {
+		jz4780_bch_read_parity(bch, ecc_code, params->bytes);
+	} else {
+		dev_err(dev, "timed out while calculating ECC\n");
+		ret = -ETIMEDOUT;
+	}
+
+	jz4780_bch_disable(bch);
+	return ret;
+}
+EXPORT_SYMBOL(jz4780_bch_calculate);
+
+/**
+ * jz4780_bch_correct() - detect and correct bit errors
+ * @dev: BCH device.
+ * @params: BCH parameters.
+ * @buf: raw data read from the chip.
+ * @ecc_code: ECC read from the chip.
+ *
+ * Given the raw data and the ECC read from the NAND device, detects and
+ * corrects errors in the data.
+ *
+ * Return: the number of bit errors corrected, or -1 if there are too many
+ * errors to correct or we timed out waiting for the controller.
+ */
+int jz4780_bch_correct(struct device *dev, struct jz4780_bch_params *params,
+		       uint8_t *buf, uint8_t *ecc_code)
+{
+	struct jz4780_bch *bch = dev_get_drvdata(dev);
+	uint32_t reg, mask, index;
+	int i, ret, count;
+
+	jz4780_bch_init(bch, params, false);
+	jz4780_bch_write_data(bch, buf, params->size);
+	jz4780_bch_write_data(bch, ecc_code, params->bytes);
+
+	if (!jz4780_bch_wait_complete(bch, BCH_BHINT_DECF, &reg)) {
+		dev_err(dev, "timed out while correcting data\n");
+		ret = -1;
+		goto out;
+	}
+
+	if (reg & BCH_BHINT_UNCOR) {
+		dev_warn(dev, "uncorrectable ECC error\n");
+		ret = -1;
+		goto out;
+	}
+
+	/* Correct any detected errors. */
+	if (reg & BCH_BHINT_ERR) {
+		count = (reg & BCH_BHINT_ERRC_MASK) >> BCH_BHINT_ERRC_SHIFT;
+		ret = (reg & BCH_BHINT_TERRC_MASK) >> BCH_BHINT_TERRC_SHIFT;
+
+		for (i = 0; i < count; i++) {
+			reg = readl(bch->base + BCH_BHERR0 + (i * 4));
+			mask = (reg & BCH_BHERR_MASK_MASK) >>
+						BCH_BHERR_MASK_SHIFT;
+			index = (reg & BCH_BHERR_INDEX_MASK) >>
+						BCH_BHERR_INDEX_SHIFT;
+			buf[(index * 2) + 0] ^= mask;
+			buf[(index * 2) + 1] ^= mask >> 8;
+		}
+	} else {
+		ret = 0;
+	}
+
+out:
+	jz4780_bch_disable(bch);
+	return ret;
+}
+EXPORT_SYMBOL(jz4780_bch_correct);
+
+/**
+ * jz4780_bch_get() - get the BCH controller device
+ * @np: BCH device tree node.
+ * @dev: where to store pointer to BCH controller device.
+ *
+ * Gets the BCH controller device from the specified device tree node. The
+ * device must be released with jz4780_bch_release() when it is no longer being
+ * used.
+ *
+ * Return: 0 on success, -EPROBE_DEFER if the controller has not yet been
+ * initialised.
+ */
+int jz4780_bch_get(struct device_node *np, struct device **dev)
+{
+	struct platform_device *pdev;
+	struct jz4780_bch *bch;
+
+	pdev = of_find_device_by_node(np);
+	if (!pdev || !platform_get_drvdata(pdev))
+		return -EPROBE_DEFER;
+
+	bch = platform_get_drvdata(pdev);
+	clk_prepare_enable(bch->clk);
+	get_device(*dev);
+
+	*dev = &pdev->dev;
+	return 0;
+}
+EXPORT_SYMBOL(jz4780_bch_get);
+
+/**
+ * jz4780_bch_release() - release the BCH controller device
+ * @dev: BCH device.
+ */
+void jz4780_bch_release(struct device *dev)
+{
+	struct jz4780_bch *bch = dev_get_drvdata(dev);
+
+	clk_disable_unprepare(bch->clk);
+	put_device(dev);
+}
+EXPORT_SYMBOL(jz4780_bch_release);
+
+static int jz4780_bch_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct jz4780_bch *bch;
+	struct resource *res;
+
+	bch = devm_kzalloc(dev, sizeof(*bch), GFP_KERNEL);
+	if (!bch)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	bch->base = devm_ioremap_resource(dev, res);
+	if (IS_ERR(bch->base)) {
+		dev_err(dev, "failed to get I/O memory\n");
+		return PTR_ERR(bch->base);
+	}
+
+	jz4780_bch_disable(bch);
+
+	bch->clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(bch->clk)) {
+		dev_err(dev, "failed to get clock: %ld\n", PTR_ERR(bch->clk));
+		return PTR_ERR(bch->clk);
+	}
+
+	clk_set_rate(bch->clk, BCH_CLK_RATE);
+
+	platform_set_drvdata(pdev, bch);
+	dev_info(dev, "JZ4780 BCH initialised\n");
+	return 0;
+}
+
+static const struct of_device_id jz4780_bch_dt_match[] = {
+	{ .compatible = "ingenic,jz4780-bch" },
+	{},
+};
+MODULE_DEVICE_TABLE(of, jz4780_bch_dt_match);
+
+static struct platform_driver jz4780_bch_driver = {
+	.probe		= jz4780_bch_probe,
+	.driver	= {
+		.name	= "jz4780-bch",
+		.of_match_table = of_match_ptr(jz4780_bch_dt_match),
+	},
+};
+module_platform_driver(jz4780_bch_driver);
+
+MODULE_AUTHOR("Alex Smith <alex@alex-smith.me.uk>");
+MODULE_DESCRIPTION("Ingenic JZ4780 BCH error correction driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/mtd/nand/jz4780_bch.h b/drivers/mtd/nand/jz4780_bch.h
new file mode 100644
index 0000000..cf315f3
--- /dev/null
+++ b/drivers/mtd/nand/jz4780_bch.h
@@ -0,0 +1,42 @@
+/*
+ * JZ4780 BCH controller
+ *
+ * Copyright (c) 2015 Imagination Technologies
+ * Author: Alex Smith <alex@alex-smith.me.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#ifndef __DRIVERS_MTD_NAND_JZ4780_BCH_H__
+#define __DRIVERS_MTD_NAND_JZ4780_BCH_H__
+
+#include <linux/types.h>
+
+struct device;
+struct device_node;
+
+/**
+ * struct jz4780_bch_params - BCH parameters
+ * @size: data bytes per ECC step.
+ * @bytes: ECC bytes per step.
+ * @strength: number of correctable bits per ECC step.
+ */
+struct jz4780_bch_params {
+	int size;
+	int bytes;
+	int strength;
+};
+
+extern int jz4780_bch_calculate(struct device *dev,
+				struct jz4780_bch_params *params,
+				const uint8_t *buf, uint8_t *ecc_code);
+extern int jz4780_bch_correct(struct device *dev,
+			      struct jz4780_bch_params *params, uint8_t *buf,
+			      uint8_t *ecc_code);
+
+extern int jz4780_bch_get(struct device_node *np, struct device **dev);
+extern void jz4780_bch_release(struct device *dev);
+
+#endif /* __DRIVERS_MTD_NAND_JZ4780_BCH_H__ */
diff --git a/drivers/mtd/nand/jz4780_nand.c b/drivers/mtd/nand/jz4780_nand.c
new file mode 100644
index 0000000..7e440d8
--- /dev/null
+++ b/drivers/mtd/nand/jz4780_nand.c
@@ -0,0 +1,376 @@
+/*
+ * JZ4780 NAND driver
+ *
+ * Copyright (c) 2015 Imagination Technologies
+ * Author: Alex Smith <alex@alex-smith.me.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_gpio.h>
+#include <linux/of_mtd.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+
+#include <linux/jz47xx-nemc.h>
+
+#include "jz4780_bch.h"
+
+#define OFFSET_DATA	0x00000000
+#define OFFSET_CMD	0x00400000
+#define OFFSET_ADDR	0x00800000
+
+/* Command delay when there is no R/B pin (in microseconds). */
+#define RB_DELAY	50
+
+struct jz4780_nand_chip {
+	unsigned int bank;
+	void __iomem *base;
+};
+
+struct jz4780_nand {
+	struct mtd_info mtd;
+	struct nand_chip chip;
+
+	struct device *dev;
+	struct device *bch;
+
+	struct nand_ecclayout ecclayout;
+
+	int busy_gpio;
+	int wp_gpio;
+	unsigned int busy_gpio_active_low: 1;
+	unsigned int wp_gpio_active_low: 1;
+	unsigned int reading: 1;
+
+	unsigned int num_banks;
+	int selected;
+	struct jz4780_nand_chip chips[];
+};
+
+static inline struct jz4780_nand *to_jz4780_nand(struct mtd_info *mtd)
+{
+	return container_of(mtd, struct jz4780_nand, mtd);
+}
+
+static void jz4780_nand_select_chip(struct mtd_info *mtd, int chipnr)
+{
+	struct jz4780_nand *nand = to_jz4780_nand(mtd);
+	struct jz4780_nand_chip *chip;
+
+	if (chipnr == -1) {
+		/* Ensure the currently selected chip is deasserted. */
+		if (nand->selected >= 0) {
+			chip = &nand->chips[nand->selected];
+			jz47xx_nemc_assert(nand->dev, chip->bank, false);
+		}
+	} else {
+		chip = &nand->chips[chipnr];
+		nand->chip.IO_ADDR_R = chip->base + OFFSET_DATA;
+		nand->chip.IO_ADDR_W = chip->base + OFFSET_DATA;
+	}
+
+	nand->selected = chipnr;
+}
+
+static void jz4780_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
+				 unsigned int ctrl)
+{
+	struct jz4780_nand *nand = to_jz4780_nand(mtd);
+	struct jz4780_nand_chip *chip;
+
+	BUG_ON(nand->selected < 0);
+	chip = &nand->chips[nand->selected];
+
+	if (ctrl & NAND_CTRL_CHANGE) {
+		if (ctrl & NAND_ALE)
+			nand->chip.IO_ADDR_W = chip->base + OFFSET_ADDR;
+		else if (ctrl & NAND_CLE)
+			nand->chip.IO_ADDR_W = chip->base + OFFSET_CMD;
+		else
+			nand->chip.IO_ADDR_W = chip->base + OFFSET_DATA;
+
+		jz47xx_nemc_assert(nand->dev, chip->bank, ctrl & NAND_NCE);
+	}
+
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, nand->chip.IO_ADDR_W);
+}
+
+static int jz4780_nand_dev_ready(struct mtd_info *mtd)
+{
+	struct jz4780_nand *nand = to_jz4780_nand(mtd);
+
+	return !(gpio_get_value(nand->busy_gpio) ^ nand->busy_gpio_active_low);
+}
+
+static void jz4780_nand_ecc_hwctl(struct mtd_info *mtd, int mode)
+{
+	struct jz4780_nand *nand = to_jz4780_nand(mtd);
+
+	nand->reading = (mode == NAND_ECC_READ);
+}
+
+static int jz4780_nand_ecc_calculate(struct mtd_info *mtd, const uint8_t *dat,
+				     uint8_t *ecc_code)
+{
+	struct jz4780_nand *nand = to_jz4780_nand(mtd);
+	struct jz4780_bch_params params;
+
+	/*
+	 * Don't need to generate the ECC when reading, BCH does it for us as
+	 * part of decoding/correction.
+	 */
+	if (nand->reading)
+		return 0;
+
+	params.size = nand->chip.ecc.size;
+	params.bytes = nand->chip.ecc.bytes;
+	params.strength = nand->chip.ecc.strength;
+
+	return jz4780_bch_calculate(nand->bch, &params, dat, ecc_code);
+}
+
+static int jz4780_nand_ecc_correct(struct mtd_info *mtd, uint8_t *dat,
+				   uint8_t *read_ecc, uint8_t *calc_ecc)
+{
+	struct jz4780_nand *nand = to_jz4780_nand(mtd);
+	struct jz4780_bch_params params;
+
+	params.size = nand->chip.ecc.size;
+	params.bytes = nand->chip.ecc.bytes;
+	params.strength = nand->chip.ecc.strength;
+
+	return jz4780_bch_correct(nand->bch, &params, dat, read_ecc);
+}
+
+static void jz4780_nand_init_ecc(struct jz4780_nand *nand, struct device *dev)
+{
+	struct mtd_info *mtd = &nand->mtd;
+	struct nand_chip *chip = &nand->chip;
+	struct nand_ecclayout *layout = &nand->ecclayout;
+	uint32_t start, i;
+
+	chip->ecc.size = of_get_nand_ecc_step_size(dev->of_node);
+	if (chip->ecc.size < 0)
+		chip->ecc.size = 1024;
+
+	chip->ecc.strength = of_get_nand_ecc_strength(dev->of_node);
+	if (chip->ecc.strength < 0)
+		chip->ecc.strength = 24;
+
+	chip->ecc.bytes = fls(1 + 8 * chip->ecc.size) * chip->ecc.strength / 8;
+
+	dev_info(dev, "using %s BCH (strength %d, size %d, bytes %d)\n",
+		 (nand->bch) ? "hardware" : "software", chip->ecc.strength,
+		 chip->ecc.size, chip->ecc.bytes);
+
+	if (nand->bch) {
+		chip->ecc.mode = NAND_ECC_HW_OOB_FIRST;
+		chip->ecc.hwctl = jz4780_nand_ecc_hwctl;
+		chip->ecc.calculate = jz4780_nand_ecc_calculate;
+		chip->ecc.correct = jz4780_nand_ecc_correct;
+	} else {
+		chip->ecc.mode = NAND_ECC_SOFT_BCH;
+	}
+
+	/* Generate ECC layout. ECC codes are right aligned in the OOB area. */
+	layout->eccbytes = mtd->writesize / chip->ecc.size * chip->ecc.bytes;
+	start = mtd->oobsize - layout->eccbytes;
+	for (i = 0; i < layout->eccbytes; i++)
+		layout->eccpos[i] = start + i;
+
+	layout->oobfree[0].offset = 2;
+	layout->oobfree[0].length = mtd->oobsize - layout->eccbytes - 2;
+
+	chip->ecc.layout = layout;
+}
+
+static int jz4780_nand_init_chips(struct jz4780_nand *nand, struct device *dev)
+{
+	struct jz4780_nand_chip *chip;
+	const __be32 *prop;
+	u64 addr, size;
+	int i = 0;
+
+	/*
+	 * Iterate over each bank assigned to this device and request resources.
+	 * The bank numbers may not be consecutive, but nand_scan_ident()
+	 * expects chip numbers to be, so fill out a consecutive array of chips
+	 * which map chip number to actual bank number.
+	 */
+	while ((prop = of_get_address(dev->of_node, i, &size, NULL))) {
+		chip = &nand->chips[i];
+		chip->bank = of_read_number(prop, 1);
+
+		jz47xx_nemc_set_type(nand->dev, chip->bank,
+				     JZ47XX_NEMC_BANK_NAND);
+
+		addr = of_translate_address(dev->of_node, prop);
+		if (addr == OF_BAD_ADDR)
+			return -EINVAL;
+
+		chip->base = devm_ioremap(dev, addr, size);
+		if (IS_ERR(chip->base)) {
+			dev_err(dev, "failed to map bank %u: %ld\n", chip->bank,
+				PTR_ERR(chip->base));
+			return PTR_ERR(chip->base);
+		}
+
+		i++;
+	}
+
+	return 0;
+}
+
+static int jz4780_nand_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	unsigned int num_banks;
+	struct jz4780_nand *nand;
+	struct device_node *bch_np;
+	struct mtd_info *mtd;
+	struct nand_chip *chip;
+	enum of_gpio_flags flags;
+	struct mtd_part_parser_data ppdata;
+	int ret;
+
+	num_banks = jz47xx_nemc_num_banks(dev);
+
+	nand = devm_kzalloc(dev,
+			sizeof(*nand) + (sizeof(nand->chips[0]) * num_banks),
+			GFP_KERNEL);
+	if (!nand)
+		return -ENOMEM;
+
+	nand->dev = dev;
+	nand->num_banks = num_banks;
+	nand->selected = -1;
+
+	/* Look for the BCH controller. */
+	bch_np = of_parse_phandle(dev->of_node, "ingenic,bch-device", 0);
+	if (bch_np) {
+		ret = jz4780_bch_get(bch_np, &nand->bch);
+		of_node_put(bch_np);
+		if (ret)
+			return ret;
+	}
+
+	mtd = &nand->mtd;
+	chip = &nand->chip;
+	mtd->priv = chip;
+	mtd->owner = THIS_MODULE;
+	mtd->name = "jz4780-nand";
+	mtd->dev.parent = dev;
+
+	chip->chip_delay = RB_DELAY;
+	chip->options = NAND_NO_SUBPAGE_WRITE;
+	chip->bbt_options = NAND_BBT_USE_FLASH;
+	chip->select_chip = jz4780_nand_select_chip;
+	chip->cmd_ctrl = jz4780_nand_cmd_ctrl;
+
+	nand->busy_gpio = of_get_named_gpio_flags(dev->of_node,
+						  "rb-gpios",
+						  0, &flags);
+	if (gpio_is_valid(nand->busy_gpio)) {
+		ret = devm_gpio_request(dev, nand->busy_gpio, "NAND busy");
+		if (ret) {
+			dev_err(dev, "failed to request busy GPIO %d: %d\n",
+				nand->busy_gpio, ret);
+			goto err_release_bch;
+		}
+
+		nand->busy_gpio_active_low = flags & OF_GPIO_ACTIVE_LOW;
+		gpio_direction_input(nand->busy_gpio);
+
+		chip->dev_ready = jz4780_nand_dev_ready;
+	}
+
+	nand->wp_gpio = of_get_named_gpio_flags(dev->of_node, "wp-gpios",
+						0, &flags);
+	if (gpio_is_valid(nand->wp_gpio)) {
+		ret = devm_gpio_request(dev, nand->wp_gpio, "NAND WP");
+		if (ret) {
+			dev_err(dev, "failed to request WP GPIO %d: %d\n",
+				nand->wp_gpio, ret);
+			goto err_release_bch;
+		}
+
+		nand->wp_gpio_active_low = flags & OF_GPIO_ACTIVE_LOW;
+		gpio_direction_output(nand->wp_gpio, nand->wp_gpio_active_low);
+	}
+
+	ret = jz4780_nand_init_chips(nand, dev);
+	if (ret)
+		goto err_release_bch;
+
+	ret = nand_scan_ident(mtd, num_banks, NULL);
+	if (ret)
+		goto err_release_bch;
+
+	jz4780_nand_init_ecc(nand, dev);
+
+	ret = nand_scan_tail(mtd);
+	if (ret)
+		goto err_release_bch;
+
+	ppdata.of_node = dev->of_node;
+	ret = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
+	if (ret)
+		goto err_release_nand;
+
+	platform_set_drvdata(pdev, nand);
+	dev_info(dev, "JZ4780 NAND initialised\n");
+	return 0;
+
+err_release_nand:
+	nand_release(mtd);
+
+err_release_bch:
+	if (nand->bch)
+		jz4780_bch_release(nand->bch);
+
+	return ret;
+}
+
+static int jz4780_nand_remove(struct platform_device *pdev)
+{
+	struct jz4780_nand *nand = platform_get_drvdata(pdev);
+
+	if (nand->bch)
+		jz4780_bch_release(nand->bch);
+
+	return 0;
+}
+
+static const struct of_device_id jz4780_nand_dt_match[] = {
+	{ .compatible = "ingenic,jz4780-nand" },
+	{},
+};
+MODULE_DEVICE_TABLE(of, jz4780_nand_dt_match);
+
+static struct platform_driver jz4780_nand_driver = {
+	.probe		= jz4780_nand_probe,
+	.remove		= jz4780_nand_remove,
+	.driver	= {
+		.name	= "jz4780-nand",
+		.of_match_table = of_match_ptr(jz4780_nand_dt_match),
+	},
+};
+module_platform_driver(jz4780_nand_driver);
+
+MODULE_AUTHOR("Alex Smith <alex.smith@imgtec.com>");
+MODULE_DESCRIPTION("Ingenic JZ4780 NAND driver");
+MODULE_LICENSE("GPL v2");
-- 
1.9.1

Re: [PATCH_V3 0/2] mtd: nand: jz4780: Add nand and bch driver

[Brian Norris]

On Tue, Mar 31, 2015 at 05:59:39PM +0100, Zubair Lutfullah Kakakhel wrote:
> Hi,

Hi!

Nit: can you drop the underscore in your 'PATCH_Vx' subjects? It'd make
my filtering a bit easier. I usually expect 'PATCH v3'. Thanks!

> Two patches based on 4.0-rc6 that add NAND and BCH controller
> drivers for the Ingenic JZ4780 SoC.
> 
> Hope these can make it in time for 4.1.
> 
> Tested on the MIPS Creator CI20.
> 
> Core JZ4780 support is still in-flight.

Sorry, I can't even compile test your patches, since I don't have the
dependencies. So I can't accept your patches yet, and they most likely
won't make it to 4.1. Or if you can point me to the right place, perhaps
we can work something out between the tree(s) that will contain the
dependencies.

Note that I'm not worried about the missing MACH_JZ4780 sybmol and your
core platform support, as much as the missing JZ4780_NEMC support.

> Review and feedback welcome.
> 
> V2 - > V3
> Rebase to 4.0-rc6
> Binding changes and fixes based on feedback by Brian Norris (Thank-you)

I had a few questions on the driver that you didn't answer, I believe.
It looks like maybe you silently answered them in this v3 code?

> V1 - > V2
> Fixed module license macros
> Rebase to 4.0-rc3
> 
> Thanks,
> ZubairLK
> 
> Alex Smith (2):
>   dt-bindings: binding for jz4780-{nand,bch}
>   mtd: nand: jz4780: driver for NAND devices on JZ4780 SoCs
> 
>  .../bindings/mtd/ingenic,jz4780-nand.txt           |  57 ++++
>  drivers/mtd/nand/Kconfig                           |   7 +
>  drivers/mtd/nand/Makefile                          |   1 +
>  drivers/mtd/nand/jz4780_bch.c                      | 353 +++++++++++++++++++
>  drivers/mtd/nand/jz4780_bch.h                      |  42 +++
>  drivers/mtd/nand/jz4780_nand.c                     | 376 +++++++++++++++++++++
>  6 files changed, 836 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt
>  create mode 100644 drivers/mtd/nand/jz4780_bch.c
>  create mode 100644 drivers/mtd/nand/jz4780_bch.h
>  create mode 100644 drivers/mtd/nand/jz4780_nand.c
> 

Brian

Re: [PATCH_V3 0/2] mtd: nand: jz4780: Add nand and bch driver

[Zubair Lutfullah Kakakhel]

Hi,

On 31/03/15 18:20, Brian Norris wrote:
> On Tue, Mar 31, 2015 at 05:59:39PM +0100, Zubair Lutfullah Kakakhel wrote:
>> Hi,
> 
> Hi!
> 
> Nit: can you drop the underscore in your 'PATCH_Vx' subjects? It'd make
> my filtering a bit easier. I usually expect 'PATCH v3'. Thanks!

Sure. Will do that for v4 if we get there.

Responses below.

> 
>> Two patches based on 4.0-rc6 that add NAND and BCH controller
>> drivers for the Ingenic JZ4780 SoC.
>>
>> Hope these can make it in time for 4.1.
>>
>> Tested on the MIPS Creator CI20.
>>
>> Core JZ4780 support is still in-flight.
> 
> Sorry, I can't even compile test your patches, since I don't have the
> dependencies. So I can't accept your patches yet, and they most likely
> won't make it to 4.1. Or if you can point me to the right place, perhaps
> we can work something out between the tree(s) that will contain the
> dependencies.
> 
> Note that I'm not worried about the missing MACH_JZ4780 sybmol and your
> core platform support, as much as the missing JZ4780_NEMC support.

I understand. Just trying to spread the load and sending everywhere
via separate subsystems.

NEMC is going via greg-kh. They went through greg's char-misc-testing and
just got applied here.

https://git.kernel.org/cgit/linux/kernel/git/gregkh/char-misc.git/log/?h=char-misc-next

Do you think that can work for compile testing? It is the upstream tree with nemc.

I could point our github ones for the ci20 board.
But it has quite a bit of other code too for jz4780 support.

> 
>> Review and feedback welcome.
>>
>> V2 - > V3
>> Rebase to 4.0-rc6
>> Binding changes and fixes based on feedback by Brian Norris (Thank-you)
> 
> I had a few questions on the driver that you didn't answer, I believe.
> It looks like maybe you silently answered them in this v3 code?
> 

I apologize for the confusion. Rushing cause of 4.0-rc6

Yes. I followed all changes accordingly except one.

>> +static int jz4780_nand_init_chips(struct jz4780_nand *nand, struct device *dev)
>> +{
>> +	struct jz4780_nand_chip *chip;
>> +	const __be32 *prop;
>> +	u64 addr, size;
>> +	int i = 0;
>> +
>> +	/*
>> +	 * Iterate over each bank assigned to this device and request resources.
>> +	 * The bank numbers may not be consecutive, but nand_scan_ident()
>> +	 * expects chip numbers to be, so fill out a consecutive array of chips
>> +	 * which map chip number to actual bank number.
>> +	 */
>> +	while ((prop = of_get_address(dev->of_node, i, &size, NULL))) {
>> +		chip = &nand->chips[i];
>> +		chip->bank = of_read_number(prop, 1);
>> +
>> +		jz47xx_nemc_set_type(nand->dev, chip->bank,
>> +				     JZ47XX_NEMC_BANK_NAND);
>> +
>> +		addr = of_translate_address(dev->of_node, prop);
>> +		if (addr == OF_BAD_ADDR)
>> +			return -EINVAL;
> 
> Is it not possible to use platform_get_resource() here? I'm not real
> sure about the platform and resource APIs vs. of_* APIs here, so I'm not
> sure.

I don't think so.

of_translate_address traverses the DT nodes tree to get the addresses.
platform_get_resource would just give the sub-address.

the DT node in the SoC file for nemc is

		nemc: nemc@13410000 {
			compatible = "ingenic,jz4780-nemc";
			reg = <0x13410000 0x10000>;
			#address-cells = <2>;
			#size-cells = <1>;
			ranges = <1 0 0x1b000000 0x1000000
			          2 0 0x1a000000 0x1000000
			          3 0 0x19000000 0x1000000
			          4 0 0x18000000 0x1000000
			          5 0 0x17000000 0x1000000
			          6 0 0x16000000 0x1000000>;

			clocks = <&cgu JZ4780_CLK_NEMC>;
		};

Then the DT node in the board file is

&nemc {
	/*
	 * Only CLE/ALE are needed for the devices that are connected, rather
	 * than the full address line set.
	 */
	pinctrl-names = "default";
	pinctrl-0 = <&pins_nemc_data &pins_nemc_cle_ale &pins_nemc_frd_fwe>;

	nand: nand@1 {
		compatible = "ingenic,jz4780-nand";
		reg = <1 0 0x1000000>;

		ingenic,nemc-tAS = <10>;
		ingenic,nemc-tAH = <5>;
		ingenic,nemc-tBP = <10>;
		ingenic,nemc-tAW = <15>;
		ingenic,nemc-tSTRV = <100>;

		ingenic,bch-device = <&bch>;
		nand-ecc-step-size = <1024>;
		nand-ecc-strength = <24>;

		rb-gpios = <&gpa 20 GPIO_ACTIVE_LOW>;
		wp-gpios = <&gpf 22 GPIO_ACTIVE_LOW>;

		pinctrl-names = "default";
		pinctrl-0 = <&pins_nemc_cs1>;

		#address-cells = <2>;
		#size-cells = <2>;

		partition@0 {
			label = "u-boot-spl";
			reg = <0x0 0x0 0x0 0x800000>;
		};

		partition@0x800000 {
			label = "u-boot";
			reg = <0x0 0x800000 0x0 0x200000>;
		};

		partition@0xa00000 {
			label = "u-boot-env";
			reg = <0x0 0xa00000 0x0 0x200000>;
		};

		partition@0xc00000 {
			label = "system";
			reg = <0x0 0xc00000 0x1 0xff400000>;
		};
	};

	dm9000@6 {
		compatible = "davicom,dm9000";
		davicom,no-eeprom;

		reg = <6 0x0 1   /* addr */
		       6 0x2 1>; /* data */

		ingenic,nemc-tAS = <15>;
		ingenic,nemc-tAH = <10>;
		ingenic,nemc-tBP = <20>;
		ingenic,nemc-tAW = <50>;
		ingenic,nemc-tSTRV = <100>;

		reset-gpios = <&gpf 12 GPIO_ACTIVE_HIGH>;
		vcc-supply = <&eth0_power>;

		interrupt-parent = <&gpe>;
		interrupts = <19 0x4>;
	};
};

Hope this clears the use of of_translate_address

Regards,
ZubairLK

>> V1 - > V2
>> Fixed module license macros
>> Rebase to 4.0-rc3
>>
>> Thanks,
>> ZubairLK
>>
>> Alex Smith (2):
>>   dt-bindings: binding for jz4780-{nand,bch}
>>   mtd: nand: jz4780: driver for NAND devices on JZ4780 SoCs
>>
>>  .../bindings/mtd/ingenic,jz4780-nand.txt           |  57 ++++
>>  drivers/mtd/nand/Kconfig                           |   7 +
>>  drivers/mtd/nand/Makefile                          |   1 +
>>  drivers/mtd/nand/jz4780_bch.c                      | 353 +++++++++++++++++++
>>  drivers/mtd/nand/jz4780_bch.h                      |  42 +++
>>  drivers/mtd/nand/jz4780_nand.c                     | 376 +++++++++++++++++++++
>>  6 files changed, 836 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt
>>  create mode 100644 drivers/mtd/nand/jz4780_bch.c
>>  create mode 100644 drivers/mtd/nand/jz4780_bch.h
>>  create mode 100644 drivers/mtd/nand/jz4780_nand.c
>>
> 
> Brian
> 

Re: [PATCH_V3 0/2] mtd: nand: jz4780: Add nand and bch driver

[Richard Weinberger]

Zubair,

On Wed, Apr 1, 2015 at 11:30 AM, Zubair Lutfullah Kakakhel
<Zubair.Kakakhel@imgtec.com> wrote:
> NEMC is going via greg-kh. They went through greg's char-misc-testing and
> just got applied here.
>
> https://git.kernel.org/cgit/linux/kernel/git/gregkh/char-misc.git/log/?h=char-misc-next
>
> Do you think that can work for compile testing? It is the upstream tree with nemc.
>
> I could point our github ones for the ci20 board.
> But it has quite a bit of other code too for jz4780 support.

what's the state of this driver? It would be nice to see it upstream.

-- 
Thanks,
//richard

Re: [PATCH_V3 0/2] mtd: nand: jz4780: Add nand and bch driver

[Brian Norris]

On Wed, Jun 03, 2015 at 11:02:05AM +0200, Richard Weinberger wrote:
> On Wed, Apr 1, 2015 at 11:30 AM, Zubair Lutfullah Kakakhel
> <Zubair.Kakakhel@imgtec.com> wrote:
> > NEMC is going via greg-kh. They went through greg's char-misc-testing and
> > just got applied here.
> >
> > https://git.kernel.org/cgit/linux/kernel/git/gregkh/char-misc.git/log/?h=char-misc-next
> >
> > Do you think that can work for compile testing? It is the upstream tree with nemc.
> >
> > I could point our github ones for the ci20 board.
> > But it has quite a bit of other code too for jz4780 support.
> 
> what's the state of this driver? It would be nice to see it upstream.

Status: doesn't build against mainline. Looks like a lot of 'jz47xx...'
names changed to 'jz4780...'. Please resubmit.

Thanks,
Brian