Re: [PATCH 1/2] regulator: DT: Add support to scale ramp delay based on platform behavior

From: Mark Brown <broonie@kernel.org>
To: Laxman Dewangan <ldewangan@nvidia.com>
Cc: Bjorn Andersson <bjorn@kryo.se>,
	Bjorn Andersson <bjorn.andersson@linaro.org>,
	Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>,
	Mark Rutland <mark.rutland@arm.com>,
	Ian Campbell <ijc+devicetree@hellion.org.uk>,
	Liam Girdwood <lgirdwood@gmail.com>,
	Stephen Warren <swarren@wwwdotorg.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	Gandhar Dighe <gdighe@nvidia.com>,
	Stuart Yates <syates@nvidia.com>
Subject: Re: [PATCH 1/2] regulator: DT: Add support to scale ramp delay based on platform behavior
Date: Tue, 12 Apr 2016 02:02:26 +0100	[thread overview]
Message-ID: <20160412010226.GO3351@sirena.org.uk> (raw)
In-Reply-To: <570370E5.3070901@nvidia.com>

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On Tue, Apr 05, 2016 at 01:31:41PM +0530, Laxman Dewangan wrote:
> On Friday 01 April 2016 09:41 PM, Mark Brown wrote:

> >>As per datasheet, There is no direct equation for ramp time deviation when
> >>regulator output current cross the regulator current limit.

> >OK, so it's really a current limit that's kicking in rather than a ramp
> >rate control (though if it's a current limit I'm still not clear why the
> >target rate limits where we cap)?  Can we do something based on the

> We are not having any control/configuration for this in this particular
> observations. All are set at maximum and still seeing this deviation.

I'm not sure how that follows from what I'm saying?  I'm saying we know
the limit, not that we can control the limit.

> During a DVS transition, the regulators output current will increase by
> COUT*dV/dt. In the event that the load current plus the additional current
> imposed by the DVS transition, reach the regulator’s current limit, the
> current limit will be enforced. When the current limit is enforced, the
> advertised DVS transition rate (dV/dt) will not occur.

> Now there is not really equation that how it control dV/dt with required
> current vs regulator’s current limit current limit.

I'm having a hard time tying this in with what you're saying.  You're
saying we have a predictable limit based on some hard maximum inrush
current but we can't tell what that limit is?  What I'd expect is that
we'd get the spec limit up to some maximum and then cap out at that.

> Working with HW team on LDO3 rail, we observed that Vendor recommend the
> Cout to 2.2uF. With having this capacitor in rail, we meet the advertised
> dv/dt i.e. 100mV/us.
> In Our platform, we have used 2x4.7uF for signal conditioning and we
> observed dv/dt went by half.
> When we changed the output capacitor to 2.2uF, we get exactly what vendor
> advertised.

The charge rate of the capactior should be a spec thing for the
capacitor shouldn't it?  

> So can we derive the configured value from the ramp time (platform) and some
> multiplication factor? If this is not common way then probably maxim
> specific as suggested by Bjorn.

How can we use a multiple of the advertised limit if we can't tell what
the limit is going to be?

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