Re: [PATCH 1/2] regulator: DT: Add support to scale ramp delay based on platform behavior

From: Laxman Dewangan <ldewangan@nvidia.com>
To: Mark Brown <broonie@kernel.org>
Cc: Bjorn Andersson <bjorn@kryo.se>,
	Bjorn Andersson <bjorn.andersson@linaro.org>,
	Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>,
	Mark Rutland <mark.rutland@arm.com>,
	Ian Campbell <ijc+devicetree@hellion.org.uk>,
	Liam Girdwood <lgirdwood@gmail.com>,
	Stephen Warren <swarren@wwwdotorg.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	Gandhar Dighe <gdighe@nvidia.com>,
	Stuart Yates <syates@nvidia.com>
Subject: Re: [PATCH 1/2] regulator: DT: Add support to scale ramp delay based on platform behavior
Date: Fri, 1 Apr 2016 12:45:21 +0530	[thread overview]
Message-ID: <56FE2009.4020302@nvidia.com> (raw)
In-Reply-To: <20160331203942.GV2350@sirena.org.uk>

On Friday 01 April 2016 02:09 AM, Mark Brown wrote:
> * PGP Signed by an unknown key
>
> On Fri, Apr 01, 2016 at 01:18:23AM +0530, Laxman Dewangan wrote:
>> On Friday 01 April 2016 12:52 AM, Mark Brown wrote:
>> So as per above, it will be adjusted to 13.75mV/us (nearest higher side) for
>> device configuration but this device need to configure for 27.5mV/us.
> You're saying that the device is so bad at regulating the ramp rate that
> it's not only failing to keep up with the desired ramp rate and capping
> at whatever rate but it's also doing even worse if configured for a
> slower rate?  That's not great, it sounds like it's doing the ramp
> control via some sort of dead reckoning thing rather than by actually
> ramping the voltage it's trying to regulate like it was asked to.
>
> Is the error in the observed values a function of the capacitance that
> we can calcuate here?
>
As per datasheet, There is no direct equation for ramp time deviation 
when regulator output current cross the regulator current limit.

 From data sheet:
/**

During a DVS transition, the regulators output current will increase by 
COUT*dV/dt. In the event that the load current plus the additional 
current imposed by the DVS transition, reach the regulator’s current 
limit, the current limit will be enforced. When the current limit is 
enforced, the advertised DVS transition rate (dV/dt) will not occur.

And there is calculation of Iinrush based on Cout and configured dv/dt.
Iinrush=min(Ilim & Cout*dV/dt).

IINRUSH calculation for Cout = 100uF

IINRUSH=min(ILIMP & COUT*dV/dt).
SD0 is a two phase regulator with a typical PMOS current limit (ILIMPP0) 
of 3.75A per phase. For ILIMP in the above equation we will use 
2x3.75A=7.5A.
SD0 has a typical soft-start rate (dV/dt_SS_SD0) of 25mV/us. For dv/dt 
in the above equation we will use 25mV/us.
IINRUSH=min(7.5A & 100uF*25mV/us).
IINRUSH=min(7.5A & 2.5A).
IINRUSH=2.5A

**/

So providing configured and observed value direct will help much here.