* [PATCH] clk: imx: fix ahb clock mux 1
@ 2016-04-28 21:07 Stefan Agner
2016-04-29 8:19 ` Uwe Kleine-König
2016-05-03 8:32 ` Shawn Guo
0 siblings, 2 replies; 6+ messages in thread
From: Stefan Agner @ 2016-04-28 21:07 UTC (permalink / raw)
To: shawnguo, kernel
Cc: mturquette, sboyd, linux-arm-kernel, linux-clk, linux-kernel,
Stefan Agner
The clock parent of the AHB root clock when using mux option 1
is the SYS PLL 270MHz clock. This is specified in Table 5-11
Clock Root Table of the i.MX 7Dual Applications Processor
Reference Manual.
While it could be a documentation error, the 270MHz parent is
also mentioned in the boot ROM configuration in Table 6-28: The
clock is by default at 135MHz due to a POST_PODF value of 1
(=> divider of 2).
Signed-off-by: Stefan Agner <stefan@agner.ch>
---
Hi Shawn,
I did not found a clock which was based on this clock which I
could measure externally... But the change is backed by the
documentation.
--
Stefan
drivers/clk/imx/clk-imx7d.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
index 7912be8..5229968 100644
--- a/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
@@ -56,7 +56,7 @@ static const char *nand_usdhc_bus_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
"pll_sys_pfd2_135m_clk", "pll_sys_pfd6_clk", "pll_enet_250m_clk",
"pll_audio_main_clk", };
-static const char *ahb_channel_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
+static const char *ahb_channel_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
"pll_dram_533m_clk", "pll_sys_pfd0_392m_clk",
"pll_enet_125m_clk", "pll_usb_main_clk", "pll_audio_main_clk",
"pll_video_main_clk", };
--
2.8.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] clk: imx: fix ahb clock mux 1
2016-04-28 21:07 [PATCH] clk: imx: fix ahb clock mux 1 Stefan Agner
@ 2016-04-29 8:19 ` Uwe Kleine-König
2016-05-03 12:36 ` Shawn Guo
2016-05-03 8:32 ` Shawn Guo
1 sibling, 1 reply; 6+ messages in thread
From: Uwe Kleine-König @ 2016-04-29 8:19 UTC (permalink / raw)
To: Stefan Agner
Cc: shawnguo, kernel, mturquette, sboyd, linux-kernel, linux-clk,
linux-arm-kernel
Hello,
$Subject ~= s/imx/imx7/
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-König |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] clk: imx: fix ahb clock mux 1
2016-04-28 21:07 [PATCH] clk: imx: fix ahb clock mux 1 Stefan Agner
2016-04-29 8:19 ` Uwe Kleine-König
@ 2016-05-03 8:32 ` Shawn Guo
2016-05-03 10:50 ` Dong Aisheng
1 sibling, 1 reply; 6+ messages in thread
From: Shawn Guo @ 2016-05-03 8:32 UTC (permalink / raw)
To: Stefan Agner, Anson Huang, Adrian Alonso, Frank Li
Cc: kernel, mturquette, sboyd, linux-arm-kernel, linux-clk, linux-kernel
On Thu, Apr 28, 2016 at 02:07:03PM -0700, Stefan Agner wrote:
> The clock parent of the AHB root clock when using mux option 1
> is the SYS PLL 270MHz clock. This is specified in Table 5-11
> Clock Root Table of the i.MX 7Dual Applications Processor
> Reference Manual.
>
> While it could be a documentation error, the 270MHz parent is
> also mentioned in the boot ROM configuration in Table 6-28: The
> clock is by default at 135MHz due to a POST_PODF value of 1
> (=> divider of 2).
>
> Signed-off-by: Stefan Agner <stefan@agner.ch>
Anson, Frank,
Can you guys confirm this change is correct?
Shawn
> ---
> Hi Shawn,
>
> I did not found a clock which was based on this clock which I
> could measure externally... But the change is backed by the
> documentation.
>
> --
> Stefan
>
> drivers/clk/imx/clk-imx7d.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
> index 7912be8..5229968 100644
> --- a/drivers/clk/imx/clk-imx7d.c
> +++ b/drivers/clk/imx/clk-imx7d.c
> @@ -56,7 +56,7 @@ static const char *nand_usdhc_bus_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
> "pll_sys_pfd2_135m_clk", "pll_sys_pfd6_clk", "pll_enet_250m_clk",
> "pll_audio_main_clk", };
>
> -static const char *ahb_channel_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
> +static const char *ahb_channel_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
> "pll_dram_533m_clk", "pll_sys_pfd0_392m_clk",
> "pll_enet_125m_clk", "pll_usb_main_clk", "pll_audio_main_clk",
> "pll_video_main_clk", };
> --
> 2.8.0
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] clk: imx: fix ahb clock mux 1
2016-05-03 8:32 ` Shawn Guo
@ 2016-05-03 10:50 ` Dong Aisheng
2016-05-03 12:37 ` Shawn Guo
0 siblings, 1 reply; 6+ messages in thread
From: Dong Aisheng @ 2016-05-03 10:50 UTC (permalink / raw)
To: Shawn Guo
Cc: Stefan Agner, Anson Huang, Adrian Alonso, Frank Li,
Michael Turquette, Stephen Boyd, linux-kernel, kernel, linux-clk,
linux-arm-kernel
Hi Shawn,
On Tue, May 3, 2016 at 4:32 PM, Shawn Guo <shawnguo@kernel.org> wrote:
> On Thu, Apr 28, 2016 at 02:07:03PM -0700, Stefan Agner wrote:
>> The clock parent of the AHB root clock when using mux option 1
>> is the SYS PLL 270MHz clock. This is specified in Table 5-11
>> Clock Root Table of the i.MX 7Dual Applications Processor
>> Reference Manual.
>>
>> While it could be a documentation error, the 270MHz parent is
>> also mentioned in the boot ROM configuration in Table 6-28: The
>> clock is by default at 135MHz due to a POST_PODF value of 1
>> (=> divider of 2).
>>
>> Signed-off-by: Stefan Agner <stefan@agner.ch>
>
> Anson, Frank,
>
> Can you guys confirm this change is correct?
>
I just checked the doc,
it's correct the parent should be SYS_PLL_PFD2(270Mhz).
It's a documentation error of early version and it's already fixed
in latest internal doc.
Regards
Dong Aisheng
> Shawn
>
>> ---
>> Hi Shawn,
>>
>> I did not found a clock which was based on this clock which I
>> could measure externally... But the change is backed by the
>> documentation.
>>
>> --
>> Stefan
>>
>> drivers/clk/imx/clk-imx7d.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
>> index 7912be8..5229968 100644
>> --- a/drivers/clk/imx/clk-imx7d.c
>> +++ b/drivers/clk/imx/clk-imx7d.c
>> @@ -56,7 +56,7 @@ static const char *nand_usdhc_bus_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
>> "pll_sys_pfd2_135m_clk", "pll_sys_pfd6_clk", "pll_enet_250m_clk",
>> "pll_audio_main_clk", };
>>
>> -static const char *ahb_channel_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
>> +static const char *ahb_channel_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
>> "pll_dram_533m_clk", "pll_sys_pfd0_392m_clk",
>> "pll_enet_125m_clk", "pll_usb_main_clk", "pll_audio_main_clk",
>> "pll_video_main_clk", };
>> --
>> 2.8.0
>>
>>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] clk: imx: fix ahb clock mux 1
2016-04-29 8:19 ` Uwe Kleine-König
@ 2016-05-03 12:36 ` Shawn Guo
0 siblings, 0 replies; 6+ messages in thread
From: Shawn Guo @ 2016-05-03 12:36 UTC (permalink / raw)
To: Uwe Kleine-König
Cc: Stefan Agner, kernel, mturquette, sboyd, linux-kernel, linux-clk,
linux-arm-kernel
On Fri, Apr 29, 2016 at 10:19:01AM +0200, Uwe Kleine-König wrote:
> Hello,
>
> $Subject ~= s/imx/imx7/
Updated the subject and applied the patch.
Shawn
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] clk: imx: fix ahb clock mux 1
2016-05-03 10:50 ` Dong Aisheng
@ 2016-05-03 12:37 ` Shawn Guo
0 siblings, 0 replies; 6+ messages in thread
From: Shawn Guo @ 2016-05-03 12:37 UTC (permalink / raw)
To: Dong Aisheng
Cc: Adrian Alonso, Frank Li, Michael Turquette, Stephen Boyd,
linux-kernel, Stefan Agner, kernel, Anson Huang, linux-clk,
linux-arm-kernel
On Tue, May 03, 2016 at 06:50:21PM +0800, Dong Aisheng wrote:
> Hi Shawn,
>
> On Tue, May 3, 2016 at 4:32 PM, Shawn Guo <shawnguo@kernel.org> wrote:
> > On Thu, Apr 28, 2016 at 02:07:03PM -0700, Stefan Agner wrote:
> >> The clock parent of the AHB root clock when using mux option 1
> >> is the SYS PLL 270MHz clock. This is specified in Table 5-11
> >> Clock Root Table of the i.MX 7Dual Applications Processor
> >> Reference Manual.
> >>
> >> While it could be a documentation error, the 270MHz parent is
> >> also mentioned in the boot ROM configuration in Table 6-28: The
> >> clock is by default at 135MHz due to a POST_PODF value of 1
> >> (=> divider of 2).
> >>
> >> Signed-off-by: Stefan Agner <stefan@agner.ch>
> >
> > Anson, Frank,
> >
> > Can you guys confirm this change is correct?
> >
>
> I just checked the doc,
> it's correct the parent should be SYS_PLL_PFD2(270Mhz).
> It's a documentation error of early version and it's already fixed
> in latest internal doc.
Thanks for the confirmation.
Shawn
^ permalink raw reply [flat|nested] 6+ messages in thread
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2016-04-28 21:07 [PATCH] clk: imx: fix ahb clock mux 1 Stefan Agner
2016-04-29 8:19 ` Uwe Kleine-König
2016-05-03 12:36 ` Shawn Guo
2016-05-03 8:32 ` Shawn Guo
2016-05-03 10:50 ` Dong Aisheng
2016-05-03 12:37 ` Shawn Guo
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