[PATCH v2 1/2] dt-bindings: pci: add DT binding for Axis ARTPEC-6 PCIe controller

[PATCH v2 1/2] dt-bindings: pci: add DT binding for Axis ARTPEC-6 PCIe controller

[Niklas Cassel]

From: Niklas Cassel <niklas.cassel@axis.com>

This commit adds the Device Tree binding documentation that allows to
describe the PCIe controller found in the Axis ARTPEC-6 SoC.

Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
---
Changes since v1:
 - Rename syscon node to be more descriptive

 .../devicetree/bindings/pci/axis,artpec6-pcie.txt  | 46 ++++++++++++++++++++++
 1 file changed, 46 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt

diff --git a/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt b/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt
new file mode 100644
index 0000000..f91b916
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt
@@ -0,0 +1,46 @@
+* Axis ARTPEC-6 PCIe interface
+
+This PCIe host controller is based on the Synopsys Designware PCIe IP
+and thus inherits all the common properties defined in designware-pcie.txt.
+
+Required properties:
+- compatible: "axis,artpec6-pcie", "snps,dw-pcie"
+- reg: base addresses and lengths of the pcie controller (DBI),
+	the phy controller, and configuration address space.
+- reg-names: Must include the following entries:
+	- "dbi"
+	- "phy"
+	- "config"
+- interrupts: A list of interrupt outputs of the controller. Must contain an
+  entry for each entry in the interrupt-names property.
+- interrupt-names: Must include the following entries:
+	- "msi": The interrupt that is asserted when an MSI is received
+- axis,syscon-pcie: A phandle pointing to the ARTPEC-6 system controller,
+	used to enable and control the Synopsys IP.
+
+Example:
+
+	pcie@f8050000 {
+		compatible = "axis,artpec6-pcie", "snps,dw-pcie";
+		reg = <0xf8050000 0x2000
+		       0xf8040000 0x1000
+		       0xc0000000 0x1000>;
+		reg-names = "dbi", "phy", "config";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+			  /* downstream I/O */
+		ranges = <0x81000000 0 0x00010000 0xc0010000 0 0x00010000
+			  /* non-prefetchable memory */
+			  0x82000000 0 0xc0020000 0xc0020000 0 0x1ffe0000>;
+		num-lanes = <2>;
+		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "msi";
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 0x7>;
+		interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+		                <0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+		                <0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+		                <0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+		axis,syscon-pcie = <&syscon>;
+	};
-- 
2.1.4

Re: [PATCH v2 1/2] dt-bindings: pci: add DT binding for Axis ARTPEC-6 PCIe controller

[Rob Herring]

On Mon, May 09, 2016 at 01:48:27PM +0200, Niklas Cassel wrote:
> From: Niklas Cassel <niklas.cassel@axis.com>
> 
> This commit adds the Device Tree binding documentation that allows to
> describe the PCIe controller found in the Axis ARTPEC-6 SoC.
> 
> Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
> ---
> Changes since v1:
>  - Rename syscon node to be more descriptive
> 
>  .../devicetree/bindings/pci/axis,artpec6-pcie.txt  | 46 ++++++++++++++++++++++
>  1 file changed, 46 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH v2 1/2] dt-bindings: pci: add DT binding for Axis ARTPEC-6 PCIe controller

[Bjorn Helgaas]

On Mon, May 09, 2016 at 01:48:27PM +0200, Niklas Cassel wrote:
> From: Niklas Cassel <niklas.cassel@axis.com>
> 
> This commit adds the Device Tree binding documentation that allows to
> describe the PCIe controller found in the Axis ARTPEC-6 SoC.
> 
> Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>

I applied both of these, with Rob's ack on the first, to
pci/host-artpec for v4.8, thanks!

I made the following minor edits; hopefully I didn't break anything:

diff --git a/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt b/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt
index f91b916..330a45b 100644
--- a/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt
@@ -1,11 +1,11 @@
 * Axis ARTPEC-6 PCIe interface
 
-This PCIe host controller is based on the Synopsys Designware PCIe IP
+This PCIe host controller is based on the Synopsys DesignWare PCIe IP
 and thus inherits all the common properties defined in designware-pcie.txt.
 
 Required properties:
 - compatible: "axis,artpec6-pcie", "snps,dw-pcie"
-- reg: base addresses and lengths of the pcie controller (DBI),
+- reg: base addresses and lengths of the PCIe controller (DBI),
 	the phy controller, and configuration address space.
 - reg-names: Must include the following entries:
 	- "dbi"
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index 1a2de8f..033d9ad 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -250,5 +250,8 @@ config PCIE_ARTPEC6
 	depends on MACH_ARTPEC6
 	select PCIE_DW
 	select PCIEPORTBUS
+	help
+	  Say Y here to enable PCIe controller support on Axis ARTPEC-6
+	  SoCs.  This PCIe controller uses the DesignWare core.
 
 endmenu
diff --git a/drivers/pci/host/pcie-artpec6.c b/drivers/pci/host/pcie-artpec6.c
index d53dbaf..19adc77 100644
--- a/drivers/pci/host/pcie-artpec6.c
+++ b/drivers/pci/host/pcie-artpec6.c
@@ -61,7 +61,7 @@ struct artpec6_pcie {
 #define PHY_STATUS			0x118
 #define PHY_COSPLLLOCK			(1 << 0)
 
-#define ARTPEC6_CPU_TO_BUS_ADDR		0x0FFFFFFF
+#define ARTPEC6_CPU_TO_BUS_ADDR		0x0fffffff
 
 static int artpec6_pcie_establish_link(struct pcie_port *pp)
 {
@@ -241,35 +241,26 @@ static int __init artpec6_pcie_probe(struct platform_device *pdev)
 
 	dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
 	pp->dbi_base = devm_ioremap_resource(&pdev->dev, dbi_base);
-	if (IS_ERR(pp->dbi_base)) {
-		ret = PTR_ERR(pp->dbi_base);
-		goto fail;
-	}
+	if (IS_ERR(pp->dbi_base))
+		return PTR_ERR(pp->dbi_base);
 
 	phy_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
 	artpec6_pcie->phy_base = devm_ioremap_resource(&pdev->dev, phy_base);
-	if (IS_ERR(artpec6_pcie->phy_base)) {
-		ret = PTR_ERR(artpec6_pcie->phy_base);
-		goto fail;
-	}
+	if (IS_ERR(artpec6_pcie->phy_base))
+		return PTR_ERR(artpec6_pcie->phy_base);
 
 	artpec6_pcie->regmap =
 		syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
 						"axis,syscon-pcie");
-	if (IS_ERR(artpec6_pcie->regmap)) {
-		ret = PTR_ERR(artpec6_pcie->regmap);
-		goto fail;
-	}
+	if (IS_ERR(artpec6_pcie->regmap))
+		return PTR_ERR(artpec6_pcie->regmap);
 
 	ret = artpec6_add_pcie_port(pp, pdev);
 	if (ret < 0)
-		goto fail;
+		return ret;
 
 	platform_set_drvdata(pdev, artpec6_pcie);
 	return 0;
-
-fail:
-	return ret;
 }
 
 static const struct of_device_id artpec6_pcie_of_match[] = {

Re: [PATCH v2 1/2] dt-bindings: pci: add DT binding for Axis ARTPEC-6 PCIe controller

[Niklas Cassel]

On 06/11/2016 09:10 PM, Bjorn Helgaas wrote:
> On Mon, May 09, 2016 at 01:48:27PM +0200, Niklas Cassel wrote:
>> From: Niklas Cassel <niklas.cassel@axis.com>
>>
>> This commit adds the Device Tree binding documentation that allows to
>> describe the PCIe controller found in the Axis ARTPEC-6 SoC.
>>
>> Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
> I applied both of these, with Rob's ack on the first, to
> pci/host-artpec for v4.8, thanks!
>
> I made the following minor edits; hopefully I didn't break anything:

Hello Bjorn,

Your changes look good.

Thank you for reviewing and applying :)

(By the way, I couldn't find pci/host-artpec on
https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/
but I suppose that you just haven't pushed your local branches yet.)

>
> diff --git a/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt b/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt
> index f91b916..330a45b 100644
> --- a/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt
> +++ b/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt
> @@ -1,11 +1,11 @@
>  * Axis ARTPEC-6 PCIe interface
>  
> -This PCIe host controller is based on the Synopsys Designware PCIe IP
> +This PCIe host controller is based on the Synopsys DesignWare PCIe IP
>  and thus inherits all the common properties defined in designware-pcie.txt.
>  
>  Required properties:
>  - compatible: "axis,artpec6-pcie", "snps,dw-pcie"
> -- reg: base addresses and lengths of the pcie controller (DBI),
> +- reg: base addresses and lengths of the PCIe controller (DBI),
>  	the phy controller, and configuration address space.
>  - reg-names: Must include the following entries:
>  	- "dbi"
> diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
> index 1a2de8f..033d9ad 100644
> --- a/drivers/pci/host/Kconfig
> +++ b/drivers/pci/host/Kconfig
> @@ -250,5 +250,8 @@ config PCIE_ARTPEC6
>  	depends on MACH_ARTPEC6
>  	select PCIE_DW
>  	select PCIEPORTBUS
> +	help
> +	  Say Y here to enable PCIe controller support on Axis ARTPEC-6
> +	  SoCs.  This PCIe controller uses the DesignWare core.
>  
>  endmenu
> diff --git a/drivers/pci/host/pcie-artpec6.c b/drivers/pci/host/pcie-artpec6.c
> index d53dbaf..19adc77 100644
> --- a/drivers/pci/host/pcie-artpec6.c
> +++ b/drivers/pci/host/pcie-artpec6.c
> @@ -61,7 +61,7 @@ struct artpec6_pcie {
>  #define PHY_STATUS			0x118
>  #define PHY_COSPLLLOCK			(1 << 0)
>  
> -#define ARTPEC6_CPU_TO_BUS_ADDR		0x0FFFFFFF
> +#define ARTPEC6_CPU_TO_BUS_ADDR		0x0fffffff
>  
>  static int artpec6_pcie_establish_link(struct pcie_port *pp)
>  {
> @@ -241,35 +241,26 @@ static int __init artpec6_pcie_probe(struct platform_device *pdev)
>  
>  	dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
>  	pp->dbi_base = devm_ioremap_resource(&pdev->dev, dbi_base);
> -	if (IS_ERR(pp->dbi_base)) {
> -		ret = PTR_ERR(pp->dbi_base);
> -		goto fail;
> -	}
> +	if (IS_ERR(pp->dbi_base))
> +		return PTR_ERR(pp->dbi_base);
>  
>  	phy_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
>  	artpec6_pcie->phy_base = devm_ioremap_resource(&pdev->dev, phy_base);
> -	if (IS_ERR(artpec6_pcie->phy_base)) {
> -		ret = PTR_ERR(artpec6_pcie->phy_base);
> -		goto fail;
> -	}
> +	if (IS_ERR(artpec6_pcie->phy_base))
> +		return PTR_ERR(artpec6_pcie->phy_base);
>  
>  	artpec6_pcie->regmap =
>  		syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
>  						"axis,syscon-pcie");
> -	if (IS_ERR(artpec6_pcie->regmap)) {
> -		ret = PTR_ERR(artpec6_pcie->regmap);
> -		goto fail;
> -	}
> +	if (IS_ERR(artpec6_pcie->regmap))
> +		return PTR_ERR(artpec6_pcie->regmap);
>  
>  	ret = artpec6_add_pcie_port(pp, pdev);
>  	if (ret < 0)
> -		goto fail;
> +		return ret;
>  
>  	platform_set_drvdata(pdev, artpec6_pcie);
>  	return 0;
> -
> -fail:
> -	return ret;
>  }
>  
>  static const struct of_device_id artpec6_pcie_of_match[] = {