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From: Mark Brown <broonie@kernel.org>
To: Rich Felker <dalias@libc.org>
Cc: linux-kernel@vger.kernel.org, linux-sh@vger.kernel.org,
	linux-spi@vger.kernel.org
Subject: Re: [PATCH v2 10/12] spi: add driver for J-Core SPI controller
Date: Mon, 23 May 2016 23:11:48 +0100	[thread overview]
Message-ID: <20160523221148.GF8206@sirena.org.uk> (raw)
In-Reply-To: <20160523202938.GD21636@brightrain.aerifal.cx>

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On Mon, May 23, 2016 at 04:29:38PM -0400, Rich Felker wrote:
> On Mon, May 23, 2016 at 04:30:37PM +0100, Mark Brown wrote:

> > One question here is why this is even part of a series - it's adding a
> > new controller driver which wouldn't normally have any sort of direct
> > build or other dependency on anything else or have other things
> > depending on it.  Unless there are dependencies it is generally best to
> > send separate changes separately as far as possible so that there is no
> > need to worry about issues with one part of the series slowing down
> > other parts of the series.

> I grouped the patches as a series because they make up support for a
> complete SoC. While some of the peripheral drivers may well be useful
> for non-J2 systems in the future (the cores are all open source, BSD
> licensed), there's no short-term benefit to having these drivers
> without the main J2 support.

That's what -next is for, merging everyone's trees together to give
something to test.  Practically speaking most maintainence is done at
the build level, it's how we do all the other SoCs so that people can
see what's going on at the subsystem level.

> > No, the reader has to be able to tell what the code is doing.  If this
> > made sense the thing to do would be to write out the logic operations
> > explicitly to make it clear that every step is deliberate.  However in
> > this case it sounds like the code is just plain buggy, though - the
> > driver is being asked to set a specific chip select to a specific value
> > but instead of just doing that it is also trying to also change some
> > other settings.

> It may be redundant, if the general SPI framework handles mutual
> exclusion of chipselects, but it's not buggy. Only a single chipselect
> can be active (low) at once; with multiple chips selected very bad
> things will happen. I don't see any documentation of the high-level
> SPI framework in Linux and what (if anything) it does to ensure that
> all other chipselects are disabled before enabling one, which I why I
> wrote the code so that the other chipselects are explicitly disabled.

There is no such guarantee because there are applications where it
makes sense to write to multiple chips simultaneously - this is one
common way of doing simultaneous updates over multiple audio audio
CODECs to ensure synchronization for example.  It's also just not
something that it makes any sense to worry about at the indivudal driver
level.

The generic code is responsible for ensuring that things work well,
writing bodges that silently try to work around the generic code is
always a recipie for fragility, especially if that code is hard to
understand.  Either the driver was making unwarranted assumptions that
break use cases it didn't think of or we end up having to find and fix
issues multiple times due to duplication.

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  reply	other threads:[~2016-05-23 22:12 UTC|newest]

Thread overview: 52+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-05-20  2:53 [PATCH v2 00/12] J-core J2 cpu and SoC peripherals support Rich Felker
2016-05-20  2:53 ` [PATCH v2 02/12] of: add J-Core cpu bindings Rich Felker
2016-05-23 20:48   ` Rob Herring
2016-05-23 21:03     ` Rich Felker
2016-05-23 23:29       ` Rob Herring
2016-05-24  2:39         ` Rich Felker
2016-05-24 21:30         ` Rob Landley
2016-05-25  1:13           ` Rob Herring
2016-05-25  2:33             ` Rich Felker
2016-05-25 13:13               ` Rob Herring
2016-05-20  2:53 ` [PATCH v2 01/12] of: add vendor prefix for J-Core Rich Felker
2016-05-23 20:49   ` Rob Herring
2016-05-20  2:53 ` [PATCH v2 08/12] irqchip: add J-Core AIC driver Rich Felker
2016-05-20  8:08   ` Geert Uytterhoeven
2016-05-20  8:15   ` Marc Zyngier
2016-05-25  4:29     ` Rich Felker
2016-05-20  2:53 ` [PATCH v2 03/12] of: add J-Core interrupt controller bindings Rich Felker
2016-05-20  8:04   ` Geert Uytterhoeven
2016-05-20 22:34     ` Rich Felker
2016-05-21 18:07       ` Geert Uytterhoeven
2016-05-21 19:17         ` Rich Felker
2016-05-23 20:53   ` Rob Herring
2016-05-23 21:13     ` Rich Felker
2016-05-24  8:09       ` Marc Zyngier
2016-05-25  2:25         ` Rich Felker
2016-05-20  2:53 ` [PATCH v2 06/12] sh: add support for J-Core J2 processor Rich Felker
2016-05-20  2:53 ` [PATCH v2 11/12] sh: add defconfig for J-Core J2 Rich Felker
2016-05-20  2:53 ` [PATCH v2 09/12] clocksource: add J-Core PIT/RTC driver Rich Felker
2016-05-20 14:01   ` Daniel Lezcano
2016-05-21  3:15     ` Rich Felker
2016-05-21 15:55       ` Rob Landley
2016-05-23 20:32       ` Daniel Lezcano
2016-05-24  2:25         ` Rich Felker
2016-05-20  2:53 ` [PATCH v2 04/12] of: add J-Core timer bindings Rich Felker
2016-05-20  8:03   ` Geert Uytterhoeven
2016-05-20  2:53 ` [PATCH v2 12/12] sh: add device tree source for J2 FPGA on Mimas v2 board Rich Felker
2016-05-20  8:17   ` Geert Uytterhoeven
2016-05-20 22:42     ` Rich Felker
2016-05-20  2:53 ` [PATCH v2 10/12] spi: add driver for J-Core SPI controller Rich Felker
2016-05-20  8:15   ` Geert Uytterhoeven
2016-05-20 22:50     ` Rich Felker
2016-05-20 10:23   ` Mark Brown
2016-05-20 23:24     ` Rich Felker
2016-05-23 15:30       ` Mark Brown
2016-05-23 20:29         ` Rich Felker
2016-05-23 22:11           ` Mark Brown [this message]
2016-05-20  2:53 ` [PATCH v2 07/12] sh: add AT_HWCAP flag for J-Core cas.l instruction Rich Felker
2016-05-20  2:53 ` [PATCH v2 05/12] of: add J-Core SPI master bindings Rich Felker
2016-05-20  8:05   ` Geert Uytterhoeven
2016-05-23 21:00   ` Rob Herring
2016-05-23 21:06     ` Rich Felker
2016-05-23 23:16       ` Rob Herring

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