From: Peter Zijlstra <peterz@infradead.org>
To: David Carrillo-Cisneros <davidcc@google.com>
Cc: linux-kernel@vger.kernel.org, "x86@kernel.org" <x86@kernel.org>,
Ingo Molnar <mingo@redhat.com>,
"Yan, Zheng" <zheng.z.yan@intel.com>,
Andi Kleen <ak@linux.intel.com>, Kan Liang <kan.liang@intel.com>,
Stephane Eranian <eranian@google.com>
Subject: Re: [PATCH 2/3] perf/x86/intel: fix for MSR_LAST_BRANCH_FROM_x quirk when no TSX
Date: Thu, 2 Jun 2016 10:55:05 +0200 [thread overview]
Message-ID: <20160602085505.GU3193@twins.programming.kicks-ass.net> (raw)
In-Reply-To: <1464835323-33872-3-git-send-email-davidcc@google.com>
On Wed, Jun 01, 2016 at 07:42:02PM -0700, David Carrillo-Cisneros wrote:
> Reviewed-by: Stephane Eranian <eranian@google.com>
Did you really? Don't just blanket issue these Stephane, look at the
bloody patches before they go out please!
next prev parent reply other threads:[~2016-06-02 8:55 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-02 2:42 [PATCH 0/3] fix MSR_LAST_BRANCH_FROM Haswell support David Carrillo-Cisneros
2016-06-02 2:42 ` [PATCH 1/3] perf/x86/intel: output LBR support statement after validation David Carrillo-Cisneros
2016-06-02 8:21 ` Peter Zijlstra
2016-06-02 16:04 ` Andi Kleen
2016-06-02 17:28 ` Stephane Eranian
2016-06-06 1:59 ` Andi Kleen
2016-06-08 7:27 ` Stephane Eranian
2016-06-08 9:08 ` Andi Kleen
2016-06-02 2:42 ` [PATCH 2/3] perf/x86/intel: fix for MSR_LAST_BRANCH_FROM_x quirk when no TSX David Carrillo-Cisneros
2016-06-02 8:23 ` Peter Zijlstra
2016-06-02 8:37 ` Peter Zijlstra
2016-06-02 8:53 ` Peter Zijlstra
[not found] ` <CALcN6mhMsNHgRVuYmYsE+O+Neq6PcaDy1-ARzBd=Vej=0rHr0Q@mail.gmail.com>
2016-06-03 9:21 ` Peter Zijlstra
2016-06-02 8:54 ` Peter Zijlstra
2016-06-02 8:55 ` Peter Zijlstra [this message]
2016-06-02 16:07 ` Andi Kleen
2016-06-02 2:42 ` [PATCH 3/3] perf, perf/tool: trigger lbr_from signext bug David Carrillo-Cisneros
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