[PATCH v2 0/2] Rework clk/vt8500 wm8650_find_pll_bits()

[PATCH v2 0/2] Rework clk/vt8500 wm8650_find_pll_bits()

[Roman Volkov]

From: Roman Volkov <rvolkov@v1ros.org>

Hi Arnd, Stephen,

This patch finally removes the warnings from GCC about possibly uninitialized
variables 'best_div2', 'best_div1', and 'best_mul'. Also one of the functions
is reworked, so that the algorithm is much easier. This is to continue the
work started in [1].

This code is tested on WM8650. Also the testing app was used in user-mode to
check possible values and performance [2].

Please schedule this for 4.8.

Changes in v2:
Apply WM8650 fix on top of changes by Arnd [3].

[1] https://lkml.org/lkml/2016/2/1/149
[2] https://github.com/v1ron/vt8500-clkrange
[3] https://lkml.org/lkml/2016/5/31/767

Thanks,
Roman

Arnd Bergmann (1):
  clk: vt8500: fix gcc-4.9 warnings

Roman Volkov (1):
  clk: vt8500: rework wm8650_find_pll_bits()

 drivers/clk/clk-vt8500.c | 99 +++++++++++++++++++++---------------------------
 1 file changed, 44 insertions(+), 55 deletions(-)

-- 
2.8.3

[PATCH v2 1/2] clk: vt8500: fix gcc-4.9 warnings

[Roman Volkov]

From: Arnd Bergmann <arnd@arndb.de>

This fixes some false positive warnings we get with older compiler
versions:

clk-vt8500.c: In function ‘wm8650_find_pll_bits’:
clk-vt8500.c:430:12: ‘best_div2’ may be used uninitialized in this function
clk-vt8500.c:429:12: ‘best_div1’ may be used uninitialized in this function
clk-vt8500.c:428:14: ‘best_mul’ may be used uninitialized in this function
clk-vt8500.c: In function ‘wm8750_find_pll_bits’:
clk-vt8500.c:509:12: ‘best_div2’ may be used uninitialized in this function
clk-vt8500.c:508:12: ‘best_div1’ may be used uninitialized in this function
clk-vt8500.c:507:14: ‘best_mul’ may be used uninitialized in this function
clk-vt8500.c: In function ‘wm8850_find_pll_bits’:
clk-vt8500.c:560:12: ‘best_div2’ may be used uninitialized in this function
clk-vt8500.c:559:12: ‘best_div1’ may be used uninitialized in this function
clk-vt8500.c:558:14: ‘best_mul’ may be used uninitialized in this function

As the local variables are only use for temporaries, we can just
as well assign the final values directly, which also makes the
code slightly shorter.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Roman Volkov <rvolkov@v1ros.org>
---
 drivers/clk/clk-vt8500.c | 34 ++++++++++------------------------
 1 file changed, 10 insertions(+), 24 deletions(-)

diff --git a/drivers/clk/clk-vt8500.c b/drivers/clk/clk-vt8500.c
index b0f76a84f1e9..d5a3453970d0 100644
--- a/drivers/clk/clk-vt8500.c
+++ b/drivers/clk/clk-vt8500.c
@@ -388,7 +388,6 @@ static int wm8650_find_pll_bits(unsigned long rate, unsigned long parent_rate,
 {
 	u32 mul, div1;
 	int div2;
-	u32 best_mul, best_div1, best_div2;
 	unsigned long tclk, rate_err, best_err;
 
 	best_err = (unsigned long)-1;
@@ -411,9 +410,9 @@ static int wm8650_find_pll_bits(unsigned long rate, unsigned long parent_rate,
 
 				if (rate_err < best_err) {
 					best_err = rate_err;
-					best_mul = mul;
-					best_div1 = div1;
-					best_div2 = div2;
+					*multiplier = mul;
+					*divisor1 = div1;
+					*divisor2 = div2;
 				}
 			}
 
@@ -425,10 +424,6 @@ static int wm8650_find_pll_bits(unsigned long rate, unsigned long parent_rate,
 	/* if we got here, it wasn't an exact match */
 	pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
 							rate - best_err);
-	*multiplier = best_mul;
-	*divisor1 = best_div1;
-	*divisor2 = best_div2;
-
 	return 0;
 }
 
@@ -464,7 +459,6 @@ static int wm8750_find_pll_bits(unsigned long rate, unsigned long parent_rate,
 {
 	u32 mul;
 	int div1, div2;
-	u32 best_mul, best_div1, best_div2;
 	unsigned long tclk, rate_err, best_err;
 
 	best_err = (unsigned long)-1;
@@ -488,9 +482,9 @@ static int wm8750_find_pll_bits(unsigned long rate, unsigned long parent_rate,
 
 				if (rate_err < best_err) {
 					best_err = rate_err;
-					best_mul = mul;
-					best_div1 = div1;
-					best_div2 = div2;
+					*multiplier = mul;
+					*divisor1 = div1;
+					*divisor2 = div2;
 				}
 			}
 
@@ -503,10 +497,7 @@ static int wm8750_find_pll_bits(unsigned long rate, unsigned long parent_rate,
 	pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
 							rate - best_err);
 
-	*filter = wm8750_get_filter(parent_rate, best_div1);
-	*multiplier = best_mul;
-	*divisor1 = best_div1;
-	*divisor2 = best_div2;
+	*filter = wm8750_get_filter(parent_rate, *divisor1);
 
 	return 0;
 }
@@ -516,7 +507,6 @@ static int wm8850_find_pll_bits(unsigned long rate, unsigned long parent_rate,
 {
 	u32 mul;
 	int div1, div2;
-	u32 best_mul, best_div1, best_div2;
 	unsigned long tclk, rate_err, best_err;
 
 	best_err = (unsigned long)-1;
@@ -540,9 +530,9 @@ static int wm8850_find_pll_bits(unsigned long rate, unsigned long parent_rate,
 
 				if (rate_err < best_err) {
 					best_err = rate_err;
-					best_mul = mul;
-					best_div1 = div1;
-					best_div2 = div2;
+					*multiplier = mul;
+					*divisor1 = div1;
+					*divisor2 = div2;
 				}
 			}
 
@@ -555,10 +545,6 @@ static int wm8850_find_pll_bits(unsigned long rate, unsigned long parent_rate,
 	pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
 							rate - best_err);
 
-	*multiplier = best_mul;
-	*divisor1 = best_div1;
-	*divisor2 = best_div2;
-
 	return 0;
 }
 
-- 
2.8.3

Re: [PATCH v2 1/2] clk: vt8500: fix gcc-4.9 warnings

[Stephen Boyd]

On 06/08, Roman Volkov wrote:
> From: Arnd Bergmann <arnd@arndb.de>
> 
> This fixes some false positive warnings we get with older compiler
> versions:
> 
> clk-vt8500.c: In function ‘wm8650_find_pll_bits’:
> clk-vt8500.c:430:12: ‘best_div2’ may be used uninitialized in this function
> clk-vt8500.c:429:12: ‘best_div1’ may be used uninitialized in this function
> clk-vt8500.c:428:14: ‘best_mul’ may be used uninitialized in this function
> clk-vt8500.c: In function ‘wm8750_find_pll_bits’:
> clk-vt8500.c:509:12: ‘best_div2’ may be used uninitialized in this function
> clk-vt8500.c:508:12: ‘best_div1’ may be used uninitialized in this function
> clk-vt8500.c:507:14: ‘best_mul’ may be used uninitialized in this function
> clk-vt8500.c: In function ‘wm8850_find_pll_bits’:
> clk-vt8500.c:560:12: ‘best_div2’ may be used uninitialized in this function
> clk-vt8500.c:559:12: ‘best_div1’ may be used uninitialized in this function
> clk-vt8500.c:558:14: ‘best_mul’ may be used uninitialized in this function
> 
> As the local variables are only use for temporaries, we can just
> as well assign the final values directly, which also makes the
> code slightly shorter.
> 
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> Signed-off-by: Roman Volkov <rvolkov@v1ros.org>
> ---

Applied to clk-next

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH v2 2/2] clk: vt8500: rework wm8650_find_pll_bits()

[Roman Volkov]

From: Roman Volkov <rvolkov@v1ros.org>

PLL clock on WM8650 is calculated in the following way:

M * parent [O1] => / P [O2] => / D [O3]

Where O2 is 600MHz >= (M * parent) / P >= 300MHz.

Current algorithm does not met this requirement, so that the
function may return rates which are not supported by the hardware.

This patch fixes the algorithm and simplifies the code, reducing
the calculation time by ~10000 times (according to usermode app) by
removing the nested loops.

Signed-off-by: Roman Volkov <rvolkov@v1ros.org>
---
 drivers/clk/clk-vt8500.c | 73 +++++++++++++++++++++++++-----------------------
 1 file changed, 38 insertions(+), 35 deletions(-)

diff --git a/drivers/clk/clk-vt8500.c b/drivers/clk/clk-vt8500.c
index d5a3453970d0..37368a399ff9 100644
--- a/drivers/clk/clk-vt8500.c
+++ b/drivers/clk/clk-vt8500.c
@@ -383,47 +383,50 @@ static int vt8500_find_pll_bits(unsigned long rate, unsigned long parent_rate,
 	return 0;
 }
 
-static int wm8650_find_pll_bits(unsigned long rate, unsigned long parent_rate,
-				u32 *multiplier, u32 *divisor1, u32 *divisor2)
+/*
+ * M * parent [O1] => / P [O2] => / D [O3]
+ * Where O1 is 900MHz...3GHz;
+ * O2 is 600MHz >= (M * parent) / P >= 300MHz;
+ * M is 36...120 [25MHz parent]; D is 1 or 2 or 4 or 8.
+ * Possible ranges (O3):
+ * D = 8: 37,5MHz...75MHz
+ * D = 4: 75MHz...150MHz
+ * D = 2: 150MHz...300MHz
+ * D = 1: 300MHz...600MHz
+ */
+static int wm8650_find_pll_bits(unsigned long rate,
+	unsigned long parent_rate, u32 *multiplier, u32 *divisor1,
+	u32 *divisor2)
 {
-	u32 mul, div1;
-	int div2;
-	unsigned long tclk, rate_err, best_err;
-
-	best_err = (unsigned long)-1;
+	unsigned long O1, min_err, rate_err;
 
-	/* Find the closest match (lower or equal to requested) */
-	for (div1 = 5; div1 >= 3; div1--)
-		for (div2 = 3; div2 >= 0; div2--)
-			for (mul = 3; mul <= 1023; mul++) {
-				tclk = parent_rate * mul / (div1 * (1 << div2));
-				if (tclk > rate)
-					continue;
-				/* error will always be +ve */
-				rate_err = rate - tclk;
-				if (rate_err == 0) {
-					*multiplier = mul;
-					*divisor1 = div1;
-					*divisor2 = div2;
-					return 0;
-				}
+	if (!parent_rate || (rate < 37500000) || (rate > 600000000))
+		return -EINVAL;
 
-				if (rate_err < best_err) {
-					best_err = rate_err;
-					*multiplier = mul;
-					*divisor1 = div1;
-					*divisor2 = div2;
-				}
-			}
+	*divisor2 = rate <= 75000000 ? 3 : rate <= 150000000 ? 2 :
+					   rate <= 300000000 ? 1 : 0;
+	/*
+	 * Divisor P cannot be calculated. Test all divisors and find where M
+	 * will be as close as possible to the requested rate.
+	 */
+	min_err = ULONG_MAX;
+	for (*divisor1 = 5; *divisor1 >= 3; (*divisor1)--) {
+		O1 = rate * *divisor1 * (1 << (*divisor2));
+		rate_err = O1 % parent_rate;
+		if (rate_err < min_err) {
+			*multiplier = O1 / parent_rate;
+			if (rate_err == 0)
+				return 0;
+
+			min_err = rate_err;
+		}
+	}
 
-	if (best_err == (unsigned long)-1) {
-		pr_warn("%s: impossible rate %lu\n", __func__, rate);
+	if ((*multiplier < 3) || (*multiplier > 1023))
 		return -EINVAL;
-	}
 
-	/* if we got here, it wasn't an exact match */
-	pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
-							rate - best_err);
+	pr_warn("%s: rate error is %lu\n", __func__, min_err);
+
 	return 0;
 }
 
-- 
2.8.3

Re: [PATCH v2 2/2] clk: vt8500: rework wm8650_find_pll_bits()

[Stephen Boyd]

On 06/08, Roman Volkov wrote:
> From: Roman Volkov <rvolkov@v1ros.org>
> 
> PLL clock on WM8650 is calculated in the following way:
> 
> M * parent [O1] => / P [O2] => / D [O3]
> 
> Where O2 is 600MHz >= (M * parent) / P >= 300MHz.
> 
> Current algorithm does not met this requirement, so that the
> function may return rates which are not supported by the hardware.
> 
> This patch fixes the algorithm and simplifies the code, reducing
> the calculation time by ~10000 times (according to usermode app) by
> removing the nested loops.
> 
> Signed-off-by: Roman Volkov <rvolkov@v1ros.org>
> ---

Applied to clk-next

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project