From: Carlo Caione <carlo@caione.org>
To: Marc Zyngier <marc.zyngier@arm.com>
Cc: "Daniel Lezcano" <daniel.lezcano@linaro.org>,
"Thomas Gleixner" <tglx@linutronix.de>,
"Rob Herring" <robh+dt@kernel.org>,
"Mark Rutland" <mark.rutland@arm.com>,
"Dinh Nguyen" <dinguyen@opensource.altera.com>,
"Kevin Hilman" <khilman@baylibre.com>,
"Duc Dang" <dhdang@apm.com>,
"Florian Fainelli" <f.fainelli@gmail.com>,
"Ray Jui" <rjui@broadcom.com>,
"Scott Branden" <sbranden@broadcom.com>,
"Kukjin Kim" <kgene@kernel.org>,
"Krzysztof Kozlowski" <k.kozlowski@samsung.com>,
"Jason Cooper" <jason@lakedaemon.net>,
"Andrew Lunn" <andrew@lunn.ch>,
"Gregory Clement" <gregory.clement@free-electrons.com>,
"Sebastian Hesselbarth" <sebastian.hesselbarth@gmail.com>,
"Masahiro Yamada" <yamada.masahiro@socionext.com>,
"Michal Simek" <michal.simek@xilinx.com>,
"Sören Brinkmann" <soren.brinkmann@xilinx.com>,
"Tirumalesh Chalamarla" <tchalamarla@cavium.com>,
"Jan Glauber" <jglauber@cavium.com>,
"Hou Zhiqiang" <B48286@freescale.com>,
"Wenbin Song" <Wenbin.Song@freescale.com>,
"Yuan Yao" <yao.yuan@nxp.com>, "Liu Gang" <Gang.Liu@nxp.com>,
"Mingkai Hu" <Mingkai.Hu@freescale.com>,
"Rajesh Bhagat" <rajesh.bhagat@freescale.com>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org,
bcm-kernel-feedback-list@broadcom.com,
linux-samsung-soc@vger.kernel.org
Subject: Re: [PATCH v3 2/2] arm64: dts: Fix broken architected timer interrupt trigger
Date: Thu, 9 Jun 2016 17:23:47 +0200 [thread overview]
Message-ID: <20160609152347.GA9477@mephisto> (raw)
In-Reply-To: <1465235791-7064-3-git-send-email-marc.zyngier@arm.com>
On 06/06/16 18:56, Marc Zyngier wrote:
> The ARM architected timer specification mandates that the interrupt
> associated with each timer is level triggered (which corresponds to
> the "counter >= comparator" condition).
>
> A number of DTs are being remarkably creative, declaring the interrupt
> to be edge triggered. A quick look at the TRM for the corresponding ARM
> CPUs clearly shows that this is wrong, and I've corrected those.
> For non-ARM designs (and in the absence of a publicly available TRM),
> I've made them active low as well, which can't be completely wrong
> as the GIC cannot disinguish between level low and level high.
>
> The respective maintainers are of course welcome to prove me wrong.
>
> While I was at it, I took the liberty to fix a couple of related issue,
> such as some spurious affinity bits on ThunderX, and their complete
> absence on ls1043a (both of which seem to be related to copy-pasting
> from other DTs).
>
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
For meson-gxbb.dtsi:
Acked-by: Carlo Caione <carlo@endlessm.com>
--
Carlo Caione
next prev parent reply other threads:[~2016-06-09 15:23 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-06 17:56 [PATCH v3 0/2] arm/arm64: Fix architected timer interrupt trigger Marc Zyngier
2016-06-06 17:56 ` [PATCH v3 1/2] clocksource/arm_arch_timer: Force per-CPU interrupt to be level-triggered Marc Zyngier
2016-06-09 21:10 ` David Daney
2016-06-10 7:29 ` Marc Zyngier
2016-06-10 17:39 ` David Daney
2016-06-11 9:41 ` Marc Zyngier
[not found] ` <CANe6Qb_sx8_rRHZG1PR=A+cgxqYTzreZ0rD01X-gtEDb=h1cVQ@mail.gmail.com>
2016-06-12 10:12 ` Marc Zyngier
2016-06-10 21:51 ` Duc Dang
2016-06-06 17:56 ` [PATCH v3 2/2] arm64: dts: Fix broken architected timer interrupt trigger Marc Zyngier
2016-06-07 7:08 ` Krzysztof Kozlowski
2016-06-07 7:19 ` Michal Simek
2016-06-09 15:05 ` Dinh Nguyen
2016-06-09 15:23 ` Carlo Caione [this message]
2016-06-09 18:11 ` David Daney
2016-06-09 21:06 ` David Daney
2016-06-10 7:23 ` Marc Zyngier
2016-06-10 16:50 ` David Daney
2016-06-10 16:56 ` Marc Zyngier
2016-06-10 17:32 ` David Daney
2016-06-11 10:04 ` Marc Zyngier
2016-06-10 21:48 ` Duc Dang
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