From: Marc Zyngier <marc.zyngier@arm.com>
To: David Daney <ddaney.cavm@gmail.com>
Cc: "David Daney" <ddaney@caviumnetworks.com>,
"Mark Rutland" <mark.rutland@arm.com>,
"Andrew Lunn" <andrew@lunn.ch>,
"Krzysztof Kozlowski" <k.kozlowski@samsung.com>,
"Hou Zhiqiang" <B48286@freescale.com>,
"Liu Gang" <Gang.Liu@nxp.com>,
"Masahiro Yamada" <yamada.masahiro@socionext.com>,
"Mingkai Hu" <Mingkai.Hu@freescale.com>,
"Florian Fainelli" <f.fainelli@gmail.com>,
"Kevin Hilman" <khilman@baylibre.com>,
"Daniel Lezcano" <daniel.lezcano@linaro.org>,
"Michal Simek" <michal.simek@xilinx.com>,
linux-samsung-soc@vger.kernel.org,
"Kukjin Kim" <kgene@kernel.org>,
bcm-kernel-feedback-list@broadcom.com,
"Sören Brinkmann" <soren.brinkmann@xilinx.com>,
"Sebastian Hesselbarth" <sebastian.hesselbarth@gmail.com>,
"Jason Cooper" <jason@lakedaemon.net>,
"Ray Jui" <rjui@broadcom.com>,
"Tirumalesh Chalamarla" <tchalamarla@cavium.com>,
"Rob Herring" <robh+dt@kernel.org>, "Yuan Yao" <yao.yuan@nxp.com>,
"Wenbin Song" <Wenbin.Song@freescale.com>,
"Jan Glauber" <jglauber@cavium.com>,
"Gregory Clement" <gregory.clement@free-electrons.com>,
linux-amlogic@lists.infradead.org,
"Thomas Gleixner" <tglx@linutronix.de>,
linux-arm-kernel@lists.infradead.org,
"Rajesh Bhagat" <rajesh.bhagat@freescale.com>,
"Scott Branden" <sbranden@broadcom.com>,
"Duc Dang" <dhdang@apm.com>,
linux-kernel@vger.kernel.org, "Carlo Caione" <carlo@caione.org>,
"Dinh Nguyen" <dinguyen@opensource.altera.com>
Subject: Re: [PATCH v3 2/2] arm64: dts: Fix broken architected timer interrupt trigger
Date: Fri, 10 Jun 2016 08:23:24 +0100 [thread overview]
Message-ID: <20160610082324.2a0967b0@arm.com> (raw)
In-Reply-To: <5759DA3A.4070905@gmail.com>
On Thu, 09 Jun 2016 14:06:02 -0700
David Daney <ddaney.cavm@gmail.com> wrote:
> I spoke too soon...
>
> On 06/09/2016 11:11 AM, David Daney wrote:
> > On 06/06/2016 10:56 AM, Marc Zyngier wrote:
> >> The ARM architected timer specification mandates that the interrupt
> >> associated with each timer is level triggered (which corresponds to
> >> the "counter >= comparator" condition).
> >>
> >> A number of DTs are being remarkably creative, declaring the interrupt
> >> to be edge triggered. A quick look at the TRM for the corresponding ARM
> >> CPUs clearly shows that this is wrong, and I've corrected those.
> >> For non-ARM designs (and in the absence of a publicly available TRM),
> >> I've made them active low as well, which can't be completely wrong
> >> as the GIC cannot disinguish between level low and level high.
> >>
> >> The respective maintainers are of course welcome to prove me wrong.
> >>
> >> While I was at it, I took the liberty to fix a couple of related issue,
> >> such as some spurious affinity bits on ThunderX, and their complete
> >> absence on ls1043a (both of which seem to be related to copy-pasting
> >> from other DTs).
> >>
> >> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
> >> ---
> >> arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 8 ++++----
> >> arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 8 ++++----
> >> arch/arm64/boot/dts/apm/apm-storm.dtsi | 8 ++++----
> >> arch/arm64/boot/dts/broadcom/ns2.dtsi | 8 ++++----
> >> arch/arm64/boot/dts/cavium/thunder-88xx.dtsi | 8 ++++----
> >> arch/arm64/boot/dts/exynos/exynos7.dtsi | 8 ++++----
> >> arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 8 ++++----
> >> arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 8 ++++----
> >> arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi | 8 ++++----
> >> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 8 ++++----
> >> 10 files changed, 40 insertions(+), 40 deletions(-)
> >>
> > [...]
> >> diff --git a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi
> >> b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi
> >> index 2eb9b22..382d86f 100644
> >> --- a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi
> >> +++ b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi
> >> @@ -354,10 +354,10 @@
> >>
> >> timer {
> >> compatible = "arm,armv8-timer";
> >> - interrupts = <1 13 0xff01>,
> >> - <1 14 0xff01>,
> >> - <1 11 0xff01>,
> >> - <1 10 0xff01>;
> >> + interrupts = <1 13 8>,
> >> + <1 14 8>,
> >> + <1 11 8>,
> >> + <1 10 8>;
>
>
> NAK!
>
> According to arm,gic-v3.txt the trigger value must be either 1 or 4:
>
> The 3rd cell is the flags, encoded as follows:
> bits[3:0] trigger type and level flags.
> 1 = edge triggered
> 4 = level triggered
Which is a bug in the binding description. PPIs can be any trigger
(just look at the TRM for CPUs that have devices connected to a PPI to
be convinced - most of them are level low).
This doesn't mean that you can distinguish level-high from level-low
in a programmatic way. But the HW definitely can handle it.
I'll update the GICv3 binding to reflect this.
Now, coming back to your NAK: is level-low the right or wrong trigger
for your implementation of the architected timers?
Thanks,
M.
--
Jazz is not dead. It just smells funny.
next prev parent reply other threads:[~2016-06-10 7:23 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-06 17:56 [PATCH v3 0/2] arm/arm64: Fix architected timer interrupt trigger Marc Zyngier
2016-06-06 17:56 ` [PATCH v3 1/2] clocksource/arm_arch_timer: Force per-CPU interrupt to be level-triggered Marc Zyngier
2016-06-09 21:10 ` David Daney
2016-06-10 7:29 ` Marc Zyngier
2016-06-10 17:39 ` David Daney
2016-06-11 9:41 ` Marc Zyngier
[not found] ` <CANe6Qb_sx8_rRHZG1PR=A+cgxqYTzreZ0rD01X-gtEDb=h1cVQ@mail.gmail.com>
2016-06-12 10:12 ` Marc Zyngier
2016-06-10 21:51 ` Duc Dang
2016-06-06 17:56 ` [PATCH v3 2/2] arm64: dts: Fix broken architected timer interrupt trigger Marc Zyngier
2016-06-07 7:08 ` Krzysztof Kozlowski
2016-06-07 7:19 ` Michal Simek
2016-06-09 15:05 ` Dinh Nguyen
2016-06-09 15:23 ` Carlo Caione
2016-06-09 18:11 ` David Daney
2016-06-09 21:06 ` David Daney
2016-06-10 7:23 ` Marc Zyngier [this message]
2016-06-10 16:50 ` David Daney
2016-06-10 16:56 ` Marc Zyngier
2016-06-10 17:32 ` David Daney
2016-06-11 10:04 ` Marc Zyngier
2016-06-10 21:48 ` Duc Dang
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