[PATCH 0/3] ARM: OMAP: DRA7: Update to latest TRM and cleanup

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* [PATCH 0/3] ARM: OMAP: DRA7: Update to latest TRM and cleanup
@ 2016-05-24 13:35 Nishanth Menon
  2016-05-24 13:35 ` [PATCH 1/3] ARM: OMAP: DRA7: powerdomain data: Set L3init and L4per to ON Nishanth Menon
                   ` (3 more replies)
  0 siblings, 4 replies; 7+ messages in thread
From: Nishanth Menon @ 2016-05-24 13:35 UTC (permalink / raw)
  To: Tony Lindgren; +Cc: linux-kernel, linux-arm-kernel, linux-omap, Nishanth Menon

Hi,

Here are the final(hopefully) pending patches for DRA7 based on recent
TRM updates. Updates include removing retention support on L3init and
L4per as per latest SoC updates.

Test Log: X15 (no modules): http://pastebin.ubuntu.com/16655027/

Latest TRM (rev F): http://www.ti.com/lit/pdf/spruhz6 (public on May 18)

Nishanth Menon (3):
  ARM: OMAP: DRA7: powerdomain data: Set L3init and L4per to ON
  ARM: OMAP: DRA7: powerdomain data: Remove unused pwrsts_logic_ret
  ARM: OMAP: DRA7: powerdomain data: Remove unused pwrsts_mem_ret

 arch/arm/mach-omap2/powerdomains7xx_data.c | 76 +-----------------------------
 1 file changed, 2 insertions(+), 74 deletions(-)

-- 
2.8.0

^ permalink raw reply	[flat|nested] 7+ messages in thread

* [PATCH 1/3] ARM: OMAP: DRA7: powerdomain data: Set L3init and L4per to ON
  2016-05-24 13:35 [PATCH 0/3] ARM: OMAP: DRA7: Update to latest TRM and cleanup Nishanth Menon
@ 2016-05-24 13:35 ` Nishanth Menon
  2016-05-24 13:35 ` [PATCH 2/3] ARM: OMAP: DRA7: powerdomain data: Remove unused pwrsts_logic_ret Nishanth Menon
                   ` (2 subsequent siblings)
  3 siblings, 0 replies; 7+ messages in thread
From: Nishanth Menon @ 2016-05-24 13:35 UTC (permalink / raw)
  To: Tony Lindgren; +Cc: linux-kernel, linux-arm-kernel, linux-omap, Nishanth Menon

As per the latest revision F of public TRM for DRA7/AM57xx SoCs
SPRUHZ6F[1] (April 2016), L4Per and L3init power domains now operate in
always "ON" mode due to asymmetric aging limitations. Update the same

[1] http://www.ti.com/lit/pdf/spruhz6

Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm/mach-omap2/powerdomains7xx_data.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/powerdomains7xx_data.c b/arch/arm/mach-omap2/powerdomains7xx_data.c
index 0ec2d00f4237..8ea447ed4dc4 100644
--- a/arch/arm/mach-omap2/powerdomains7xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains7xx_data.c
@@ -111,7 +111,7 @@ static struct powerdomain l4per_7xx_pwrdm = {
 	.name		  = "l4per_pwrdm",
 	.prcm_offs	  = DRA7XX_PRM_L4PER_INST,
 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
-	.pwrsts		  = PWRSTS_RET_ON,
+	.pwrsts		  = PWRSTS_ON,
 	.pwrsts_logic_ret = PWRSTS_RET,
 	.banks		  = 2,
 	.pwrsts_mem_ret	= {
@@ -260,7 +260,7 @@ static struct powerdomain l3init_7xx_pwrdm = {
 	.name		  = "l3init_pwrdm",
 	.prcm_offs	  = DRA7XX_PRM_L3INIT_INST,
 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
-	.pwrsts		  = PWRSTS_RET_ON,
+	.pwrsts		  = PWRSTS_ON,
 	.pwrsts_logic_ret = PWRSTS_RET,
 	.banks		  = 3,
 	.pwrsts_mem_ret	= {
-- 
2.8.0

^ permalink raw reply related	[flat|nested] 7+ messages in thread

* [PATCH 2/3] ARM: OMAP: DRA7: powerdomain data: Remove unused pwrsts_logic_ret
  2016-05-24 13:35 [PATCH 0/3] ARM: OMAP: DRA7: Update to latest TRM and cleanup Nishanth Menon
  2016-05-24 13:35 ` [PATCH 1/3] ARM: OMAP: DRA7: powerdomain data: Set L3init and L4per to ON Nishanth Menon
@ 2016-05-24 13:35 ` Nishanth Menon
  2016-05-24 13:35 ` [PATCH 3/3] ARM: OMAP: DRA7: powerdomain data: Remove unused pwrsts_mem_ret Nishanth Menon
  2016-06-10  9:34 ` [PATCH 0/3] ARM: OMAP: DRA7: Update to latest TRM and cleanup Tony Lindgren
  3 siblings, 0 replies; 7+ messages in thread
From: Nishanth Menon @ 2016-05-24 13:35 UTC (permalink / raw)
  To: Tony Lindgren; +Cc: linux-kernel, linux-arm-kernel, linux-omap, Nishanth Menon

As per the latest revision F of public TRM for DRA7/AM57xx SoCs
SPRUHZ6F[1] (April 2016), with the exception of MPU power domain (and
CPUx sub power domains), all other power domains can either operate
in "ON" mode OR in some cases, "OFF" mode. For these power states,
the logic retention state is basically ignored by PRCM and does not
require to be programmed.

[1] http://www.ti.com/lit/pdf/spruhz6

Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm/mach-omap2/powerdomains7xx_data.c | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/arch/arm/mach-omap2/powerdomains7xx_data.c b/arch/arm/mach-omap2/powerdomains7xx_data.c
index 8ea447ed4dc4..88107b449710 100644
--- a/arch/arm/mach-omap2/powerdomains7xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains7xx_data.c
@@ -36,7 +36,6 @@ static struct powerdomain iva_7xx_pwrdm = {
 	.prcm_offs	  = DRA7XX_PRM_IVA_INST,
 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
 	.pwrsts		  = PWRSTS_OFF_ON,
-	.pwrsts_logic_ret = PWRSTS_OFF,
 	.banks		  = 4,
 	.pwrsts_mem_ret	= {
 		[0] = PWRSTS_OFF_RET,	/* hwa_mem */
@@ -76,7 +75,6 @@ static struct powerdomain ipu_7xx_pwrdm = {
 	.prcm_offs	  = DRA7XX_PRM_IPU_INST,
 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
 	.pwrsts		  = PWRSTS_OFF_ON,
-	.pwrsts_logic_ret = PWRSTS_OFF,
 	.banks		  = 2,
 	.pwrsts_mem_ret	= {
 		[0] = PWRSTS_OFF_RET,	/* aessmem */
@@ -95,7 +93,6 @@ static struct powerdomain dss_7xx_pwrdm = {
 	.prcm_offs	  = DRA7XX_PRM_DSS_INST,
 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
 	.pwrsts		  = PWRSTS_OFF_ON,
-	.pwrsts_logic_ret = PWRSTS_OFF,
 	.banks		  = 1,
 	.pwrsts_mem_ret	= {
 		[0] = PWRSTS_OFF_RET,	/* dss_mem */
@@ -112,7 +109,6 @@ static struct powerdomain l4per_7xx_pwrdm = {
 	.prcm_offs	  = DRA7XX_PRM_L4PER_INST,
 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
 	.pwrsts		  = PWRSTS_ON,
-	.pwrsts_logic_ret = PWRSTS_RET,
 	.banks		  = 2,
 	.pwrsts_mem_ret	= {
 		[0] = PWRSTS_OFF_RET,	/* nonretained_bank */
@@ -161,7 +157,6 @@ static struct powerdomain core_7xx_pwrdm = {
 	.prcm_offs	  = DRA7XX_PRM_CORE_INST,
 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
 	.pwrsts		  = PWRSTS_ON,
-	.pwrsts_logic_ret = PWRSTS_RET,
 	.banks		  = 5,
 	.pwrsts_mem_ret	= {
 		[0] = PWRSTS_OFF_RET,	/* core_nret_bank */
@@ -226,7 +221,6 @@ static struct powerdomain vpe_7xx_pwrdm = {
 	.prcm_offs	  = DRA7XX_PRM_VPE_INST,
 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
 	.pwrsts		  = PWRSTS_OFF_ON,
-	.pwrsts_logic_ret = PWRSTS_OFF,
 	.banks		  = 1,
 	.pwrsts_mem_ret	= {
 		[0] = PWRSTS_OFF_RET,	/* vpe_bank */
@@ -261,7 +255,6 @@ static struct powerdomain l3init_7xx_pwrdm = {
 	.prcm_offs	  = DRA7XX_PRM_L3INIT_INST,
 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
 	.pwrsts		  = PWRSTS_ON,
-	.pwrsts_logic_ret = PWRSTS_RET,
 	.banks		  = 3,
 	.pwrsts_mem_ret	= {
 		[0] = PWRSTS_OFF_RET,	/* gmac_bank */
-- 
2.8.0

^ permalink raw reply related	[flat|nested] 7+ messages in thread

* [PATCH 3/3] ARM: OMAP: DRA7: powerdomain data: Remove unused pwrsts_mem_ret
  2016-05-24 13:35 [PATCH 0/3] ARM: OMAP: DRA7: Update to latest TRM and cleanup Nishanth Menon
  2016-05-24 13:35 ` [PATCH 1/3] ARM: OMAP: DRA7: powerdomain data: Set L3init and L4per to ON Nishanth Menon
  2016-05-24 13:35 ` [PATCH 2/3] ARM: OMAP: DRA7: powerdomain data: Remove unused pwrsts_logic_ret Nishanth Menon
@ 2016-05-24 13:35 ` Nishanth Menon
  2016-06-10  9:34 ` [PATCH 0/3] ARM: OMAP: DRA7: Update to latest TRM and cleanup Tony Lindgren
  3 siblings, 0 replies; 7+ messages in thread
From: Nishanth Menon @ 2016-05-24 13:35 UTC (permalink / raw)
  To: Tony Lindgren; +Cc: linux-kernel, linux-arm-kernel, linux-omap, Nishanth Menon

As per the latest revision F of public TRM for DRA7/AM57xx SoCs
SPRUHZ6F[1] (April 2016), with the exception of MPU power domain, all
other power domains do not have memories capable of retention since
they all operate in either "ON" or "OFF" mode. For these power states,
the retention state for memories are basically ignored by PRCM and does
not require to be programmed.

[1] http://www.ti.com/lit/pdf/spruhz6

Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm/mach-omap2/powerdomains7xx_data.c | 65 ------------------------------
 1 file changed, 65 deletions(-)

diff --git a/arch/arm/mach-omap2/powerdomains7xx_data.c b/arch/arm/mach-omap2/powerdomains7xx_data.c
index 88107b449710..eb350a673133 100644
--- a/arch/arm/mach-omap2/powerdomains7xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains7xx_data.c
@@ -37,12 +37,6 @@ static struct powerdomain iva_7xx_pwrdm = {
 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
 	.pwrsts		  = PWRSTS_OFF_ON,
 	.banks		  = 4,
-	.pwrsts_mem_ret	= {
-		[0] = PWRSTS_OFF_RET,	/* hwa_mem */
-		[1] = PWRSTS_OFF_RET,	/* sl2_mem */
-		[2] = PWRSTS_OFF_RET,	/* tcm1_mem */
-		[3] = PWRSTS_OFF_RET,	/* tcm2_mem */
-	},
 	.pwrsts_mem_on	= {
 		[0] = PWRSTS_ON,	/* hwa_mem */
 		[1] = PWRSTS_ON,	/* sl2_mem */
@@ -76,10 +70,6 @@ static struct powerdomain ipu_7xx_pwrdm = {
 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
 	.pwrsts		  = PWRSTS_OFF_ON,
 	.banks		  = 2,
-	.pwrsts_mem_ret	= {
-		[0] = PWRSTS_OFF_RET,	/* aessmem */
-		[1] = PWRSTS_OFF_RET,	/* periphmem */
-	},
 	.pwrsts_mem_on	= {
 		[0] = PWRSTS_ON,	/* aessmem */
 		[1] = PWRSTS_ON,	/* periphmem */
@@ -94,9 +84,6 @@ static struct powerdomain dss_7xx_pwrdm = {
 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
 	.pwrsts		  = PWRSTS_OFF_ON,
 	.banks		  = 1,
-	.pwrsts_mem_ret	= {
-		[0] = PWRSTS_OFF_RET,	/* dss_mem */
-	},
 	.pwrsts_mem_on	= {
 		[0] = PWRSTS_ON,	/* dss_mem */
 	},
@@ -110,10 +97,6 @@ static struct powerdomain l4per_7xx_pwrdm = {
 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
 	.pwrsts		  = PWRSTS_ON,
 	.banks		  = 2,
-	.pwrsts_mem_ret	= {
-		[0] = PWRSTS_OFF_RET,	/* nonretained_bank */
-		[1] = PWRSTS_OFF_RET,	/* retained_bank */
-	},
 	.pwrsts_mem_on	= {
 		[0] = PWRSTS_ON,	/* nonretained_bank */
 		[1] = PWRSTS_ON,	/* retained_bank */
@@ -128,9 +111,6 @@ static struct powerdomain gpu_7xx_pwrdm = {
 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
 	.pwrsts		  = PWRSTS_OFF_ON,
 	.banks		  = 1,
-	.pwrsts_mem_ret	= {
-		[0] = PWRSTS_OFF_RET,	/* gpu_mem */
-	},
 	.pwrsts_mem_on	= {
 		[0] = PWRSTS_ON,	/* gpu_mem */
 	},
@@ -144,8 +124,6 @@ static struct powerdomain wkupaon_7xx_pwrdm = {
 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
 	.pwrsts		  = PWRSTS_ON,
 	.banks		  = 1,
-	.pwrsts_mem_ret	= {
-	},
 	.pwrsts_mem_on	= {
 		[0] = PWRSTS_ON,	/* wkup_bank */
 	},
@@ -158,13 +136,6 @@ static struct powerdomain core_7xx_pwrdm = {
 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
 	.pwrsts		  = PWRSTS_ON,
 	.banks		  = 5,
-	.pwrsts_mem_ret	= {
-		[0] = PWRSTS_OFF_RET,	/* core_nret_bank */
-		[1] = PWRSTS_OFF_RET,	/* core_ocmram */
-		[2] = PWRSTS_OFF_RET,	/* core_other_bank */
-		[3] = PWRSTS_OFF_RET,	/* ipu_l2ram */
-		[4] = PWRSTS_OFF_RET,	/* ipu_unicache */
-	},
 	.pwrsts_mem_on	= {
 		[0] = PWRSTS_ON,	/* core_nret_bank */
 		[1] = PWRSTS_ON,	/* core_ocmram */
@@ -222,9 +193,6 @@ static struct powerdomain vpe_7xx_pwrdm = {
 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
 	.pwrsts		  = PWRSTS_OFF_ON,
 	.banks		  = 1,
-	.pwrsts_mem_ret	= {
-		[0] = PWRSTS_OFF_RET,	/* vpe_bank */
-	},
 	.pwrsts_mem_on	= {
 		[0] = PWRSTS_ON,	/* vpe_bank */
 	},
@@ -256,11 +224,6 @@ static struct powerdomain l3init_7xx_pwrdm = {
 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
 	.pwrsts		  = PWRSTS_ON,
 	.banks		  = 3,
-	.pwrsts_mem_ret	= {
-		[0] = PWRSTS_OFF_RET,	/* gmac_bank */
-		[1] = PWRSTS_OFF_RET,	/* l3init_bank1 */
-		[2] = PWRSTS_OFF_RET,	/* l3init_bank2 */
-	},
 	.pwrsts_mem_on	= {
 		[0] = PWRSTS_ON,	/* gmac_bank */
 		[1] = PWRSTS_ON,	/* l3init_bank1 */
@@ -276,9 +239,6 @@ static struct powerdomain eve3_7xx_pwrdm = {
 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
 	.pwrsts		  = PWRSTS_OFF_ON,
 	.banks		  = 1,
-	.pwrsts_mem_ret	= {
-		[0] = PWRSTS_OFF_RET,	/* eve3_bank */
-	},
 	.pwrsts_mem_on	= {
 		[0] = PWRSTS_ON,	/* eve3_bank */
 	},
@@ -292,9 +252,6 @@ static struct powerdomain emu_7xx_pwrdm = {
 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
 	.pwrsts		  = PWRSTS_OFF_ON,
 	.banks		  = 1,
-	.pwrsts_mem_ret	= {
-		[0] = PWRSTS_OFF_RET,	/* emu_bank */
-	},
 	.pwrsts_mem_on	= {
 		[0] = PWRSTS_ON,	/* emu_bank */
 	},
@@ -307,11 +264,6 @@ static struct powerdomain dsp2_7xx_pwrdm = {
 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
 	.pwrsts		  = PWRSTS_OFF_ON,
 	.banks		  = 3,
-	.pwrsts_mem_ret	= {
-		[0] = PWRSTS_OFF_RET,	/* dsp2_edma */
-		[1] = PWRSTS_OFF_RET,	/* dsp2_l1 */
-		[2] = PWRSTS_OFF_RET,	/* dsp2_l2 */
-	},
 	.pwrsts_mem_on	= {
 		[0] = PWRSTS_ON,	/* dsp2_edma */
 		[1] = PWRSTS_ON,	/* dsp2_l1 */
@@ -327,11 +279,6 @@ static struct powerdomain dsp1_7xx_pwrdm = {
 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
 	.pwrsts		  = PWRSTS_OFF_ON,
 	.banks		  = 3,
-	.pwrsts_mem_ret	= {
-		[0] = PWRSTS_OFF_RET,	/* dsp1_edma */
-		[1] = PWRSTS_OFF_RET,	/* dsp1_l1 */
-		[2] = PWRSTS_OFF_RET,	/* dsp1_l2 */
-	},
 	.pwrsts_mem_on	= {
 		[0] = PWRSTS_ON,	/* dsp1_edma */
 		[1] = PWRSTS_ON,	/* dsp1_l1 */
@@ -347,9 +294,6 @@ static struct powerdomain cam_7xx_pwrdm = {
 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
 	.pwrsts		  = PWRSTS_OFF_ON,
 	.banks		  = 1,
-	.pwrsts_mem_ret	= {
-		[0] = PWRSTS_OFF_RET,	/* vip_bank */
-	},
 	.pwrsts_mem_on	= {
 		[0] = PWRSTS_ON,	/* vip_bank */
 	},
@@ -363,9 +307,6 @@ static struct powerdomain eve4_7xx_pwrdm = {
 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
 	.pwrsts		  = PWRSTS_OFF_ON,
 	.banks		  = 1,
-	.pwrsts_mem_ret	= {
-		[0] = PWRSTS_OFF_RET,	/* eve4_bank */
-	},
 	.pwrsts_mem_on	= {
 		[0] = PWRSTS_ON,	/* eve4_bank */
 	},
@@ -379,9 +320,6 @@ static struct powerdomain eve2_7xx_pwrdm = {
 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
 	.pwrsts		  = PWRSTS_OFF_ON,
 	.banks		  = 1,
-	.pwrsts_mem_ret	= {
-		[0] = PWRSTS_OFF_RET,	/* eve2_bank */
-	},
 	.pwrsts_mem_on	= {
 		[0] = PWRSTS_ON,	/* eve2_bank */
 	},
@@ -395,9 +333,6 @@ static struct powerdomain eve1_7xx_pwrdm = {
 	.prcm_partition	  = DRA7XX_PRM_PARTITION,
 	.pwrsts		  = PWRSTS_OFF_ON,
 	.banks		  = 1,
-	.pwrsts_mem_ret	= {
-		[0] = PWRSTS_OFF_RET,	/* eve1_bank */
-	},
 	.pwrsts_mem_on	= {
 		[0] = PWRSTS_ON,	/* eve1_bank */
 	},
-- 
2.8.0

^ permalink raw reply related	[flat|nested] 7+ messages in thread

* Re: [PATCH 0/3] ARM: OMAP: DRA7: Update to latest TRM and cleanup
  2016-05-24 13:35 [PATCH 0/3] ARM: OMAP: DRA7: Update to latest TRM and cleanup Nishanth Menon
                   ` (2 preceding siblings ...)
  2016-05-24 13:35 ` [PATCH 3/3] ARM: OMAP: DRA7: powerdomain data: Remove unused pwrsts_mem_ret Nishanth Menon
@ 2016-06-10  9:34 ` Tony Lindgren
  2016-06-10 14:18   ` Nishanth Menon
  3 siblings, 1 reply; 7+ messages in thread
From: Tony Lindgren @ 2016-06-10  9:34 UTC (permalink / raw)
  To: Nishanth Menon; +Cc: linux-kernel, linux-arm-kernel, linux-omap

Hi,

* Nishanth Menon <nm@ti.com> [160524 06:37]:
> Hi,
> 
> Here are the final(hopefully) pending patches for DRA7 based on recent
> TRM updates. Updates include removing retention support on L3init and
> L4per as per latest SoC updates.
> 
> Test Log: X15 (no modules): http://pastebin.ubuntu.com/16655027/
> 
> Latest TRM (rev F): http://www.ti.com/lit/pdf/spruhz6 (public on May 18)
> 
> Nishanth Menon (3):
>   ARM: OMAP: DRA7: powerdomain data: Set L3init and L4per to ON
>   ARM: OMAP: DRA7: powerdomain data: Remove unused pwrsts_logic_ret
>   ARM: OMAP: DRA7: powerdomain data: Remove unused pwrsts_mem_ret
> 
>  arch/arm/mach-omap2/powerdomains7xx_data.c | 76 +-----------------------------
>  1 file changed, 2 insertions(+), 74 deletions(-)

Can these wait until v4.8 merge window, are this needed as fixes to
avoid hardware problems?

Regards,

Tony

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH 0/3] ARM: OMAP: DRA7: Update to latest TRM and cleanup
  2016-06-10  9:34 ` [PATCH 0/3] ARM: OMAP: DRA7: Update to latest TRM and cleanup Tony Lindgren
@ 2016-06-10 14:18   ` Nishanth Menon
  2016-06-13  8:42     ` Tony Lindgren
  0 siblings, 1 reply; 7+ messages in thread
From: Nishanth Menon @ 2016-06-10 14:18 UTC (permalink / raw)
  To: Tony Lindgren; +Cc: lkml, linux-arm-kernel, linux-omap

On Fri, Jun 10, 2016 at 4:34 AM, Tony Lindgren <tony@atomide.com> wrote:
> Hi,
>
> * Nishanth Menon <nm@ti.com> [160524 06:37]:
>> Hi,
>>
>> Here are the final(hopefully) pending patches for DRA7 based on recent
>> TRM updates. Updates include removing retention support on L3init and
>> L4per as per latest SoC updates.
>>
>> Test Log: X15 (no modules): http://pastebin.ubuntu.com/16655027/
>>
>> Latest TRM (rev F): http://www.ti.com/lit/pdf/spruhz6 (public on May 18)
>>
>> Nishanth Menon (3):
>>   ARM: OMAP: DRA7: powerdomain data: Set L3init and L4per to ON
>>   ARM: OMAP: DRA7: powerdomain data: Remove unused pwrsts_logic_ret
>>   ARM: OMAP: DRA7: powerdomain data: Remove unused pwrsts_mem_ret
>>
>>  arch/arm/mach-omap2/powerdomains7xx_data.c | 76 +-----------------------------
>>  1 file changed, 2 insertions(+), 74 deletions(-)
>
> Can these wait until v4.8 merge window, are this needed as fixes to
> avoid hardware problems?

Yes - at least patch #1 is a h/w "limitation" and can result in non
functional SoC after a duration of operation. the patches #2/3 are
code shrinkage to remove unused data.

-- 
---
Regards,
Nishanth Menon

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH 0/3] ARM: OMAP: DRA7: Update to latest TRM and cleanup
  2016-06-10 14:18   ` Nishanth Menon
@ 2016-06-13  8:42     ` Tony Lindgren
  0 siblings, 0 replies; 7+ messages in thread
From: Tony Lindgren @ 2016-06-13  8:42 UTC (permalink / raw)
  To: Nishanth Menon; +Cc: lkml, linux-arm-kernel, linux-omap

* Nishanth Menon <nm@ti.com> [160610 07:20]:
> On Fri, Jun 10, 2016 at 4:34 AM, Tony Lindgren <tony@atomide.com> wrote:
> > Hi,
> >
> > * Nishanth Menon <nm@ti.com> [160524 06:37]:
> >> Hi,
> >>
> >> Here are the final(hopefully) pending patches for DRA7 based on recent
> >> TRM updates. Updates include removing retention support on L3init and
> >> L4per as per latest SoC updates.
> >>
> >> Test Log: X15 (no modules): http://pastebin.ubuntu.com/16655027/
> >>
> >> Latest TRM (rev F): http://www.ti.com/lit/pdf/spruhz6 (public on May 18)
> >>
> >> Nishanth Menon (3):
> >>   ARM: OMAP: DRA7: powerdomain data: Set L3init and L4per to ON
> >>   ARM: OMAP: DRA7: powerdomain data: Remove unused pwrsts_logic_ret
> >>   ARM: OMAP: DRA7: powerdomain data: Remove unused pwrsts_mem_ret
> >>
> >>  arch/arm/mach-omap2/powerdomains7xx_data.c | 76 +-----------------------------
> >>  1 file changed, 2 insertions(+), 74 deletions(-)
> >
> > Can these wait until v4.8 merge window, are this needed as fixes to
> > avoid hardware problems?
> 
> Yes - at least patch #1 is a h/w "limitation" and can result in non
> functional SoC after a duration of operation. the patches #2/3 are
> code shrinkage to remove unused data.

OK thanks that's a good reason to have them merged for v4.7.
I've applied them into omap-for-v4.7/fixes and will send a pull
request later today.

Regards,

Tony

^ permalink raw reply	[flat|nested] 7+ messages in thread

end of thread, other threads:[~2016-06-13  8:42 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-05-24 13:35 [PATCH 0/3] ARM: OMAP: DRA7: Update to latest TRM and cleanup Nishanth Menon
2016-05-24 13:35 ` [PATCH 1/3] ARM: OMAP: DRA7: powerdomain data: Set L3init and L4per to ON Nishanth Menon
2016-05-24 13:35 ` [PATCH 2/3] ARM: OMAP: DRA7: powerdomain data: Remove unused pwrsts_logic_ret Nishanth Menon
2016-05-24 13:35 ` [PATCH 3/3] ARM: OMAP: DRA7: powerdomain data: Remove unused pwrsts_mem_ret Nishanth Menon
2016-06-10  9:34 ` [PATCH 0/3] ARM: OMAP: DRA7: Update to latest TRM and cleanup Tony Lindgren
2016-06-10 14:18   ` Nishanth Menon
2016-06-13  8:42     ` Tony Lindgren

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