[PATCH 1/2] clk: sunxi-ng: h3: Fix audio clock divider offset

[PATCH 1/2] clk: sunxi-ng: h3: Fix audio clock divider offset

[Maxime Ripard]

The code had a typo and got the wrong offset for the hardcoded divider, fix
that.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reported-by: Jean-Francois Moine <moinejf@free.fr>
Reported-by: Chen-Yu Tsai <wens@csie.org>
---
 drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index bcc0a95549d3..9af359544110 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -817,8 +817,8 @@ static void __init sun8i_h3_ccu_setup(struct device_node *node)
 
 	/* Force the PLL-Audio-1x divider to 4 */
 	val = readl(reg + SUN8I_H3_PLL_AUDIO_REG);
-	val &= ~GENMASK(4, 0);
-	writel(val | 3, reg + SUN8I_H3_PLL_AUDIO_REG);
+	val &= ~GENMASK(19, 16);
+	writel(val | (3 << 16), reg + SUN8I_H3_PLL_AUDIO_REG);
 
 	sunxi_ccu_probe(node, reg, &sun8i_h3_ccu_desc);
 }
-- 
2.9.0

[PATCH 2/2] clk: sunxi-ng: h3: Fix Kconfig symbol typo

[Maxime Ripard]

The Kconfig symbol for the sun8i SoC family was mistyped. Fix that.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
 drivers/clk/sunxi-ng/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index 41e53e8d4d41..2afcbd39e41e 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -60,6 +60,6 @@ config SUN8I_H3_CCU
 	select SUNXI_CCU_NM
 	select SUNXI_CCU_MP
 	select SUNXI_CCU_PHASE
-	default ARCH_SUN8I
+	default MACH_SUN8I
 
 endif
-- 
2.9.0

Re: [PATCH 2/2] clk: sunxi-ng: h3: Fix Kconfig symbol typo

[Michael Turquette]

Quoting Maxime Ripard (2016-07-11 13:34:48)
> The Kconfig symbol for the sun8i SoC family was mistyped. Fix that.
> 
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Applied.

Regards,
Mike

> ---
>  drivers/clk/sunxi-ng/Kconfig | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
> index 41e53e8d4d41..2afcbd39e41e 100644
> --- a/drivers/clk/sunxi-ng/Kconfig
> +++ b/drivers/clk/sunxi-ng/Kconfig
> @@ -60,6 +60,6 @@ config SUN8I_H3_CCU
>         select SUNXI_CCU_NM
>         select SUNXI_CCU_MP
>         select SUNXI_CCU_PHASE
> -       default ARCH_SUN8I
> +       default MACH_SUN8I
>  
>  endif
> -- 
> 2.9.0
> 

Re: [PATCH 1/2] clk: sunxi-ng: h3: Fix audio clock divider offset

[Michael Turquette]

Quoting Maxime Ripard (2016-07-11 13:34:47)
> The code had a typo and got the wrong offset for the hardcoded divider, fix
> that.
> 
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> Reported-by: Jean-Francois Moine <moinejf@free.fr>
> Reported-by: Chen-Yu Tsai <wens@csie.org>

Applied.

Regards,
Mike

> ---
>  drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
> index bcc0a95549d3..9af359544110 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
> @@ -817,8 +817,8 @@ static void __init sun8i_h3_ccu_setup(struct device_node *node)
>  
>         /* Force the PLL-Audio-1x divider to 4 */
>         val = readl(reg + SUN8I_H3_PLL_AUDIO_REG);
> -       val &= ~GENMASK(4, 0);
> -       writel(val | 3, reg + SUN8I_H3_PLL_AUDIO_REG);
> +       val &= ~GENMASK(19, 16);
> +       writel(val | (3 << 16), reg + SUN8I_H3_PLL_AUDIO_REG);
>  
>         sunxi_ccu_probe(node, reg, &sun8i_h3_ccu_desc);
>  }
> -- 
> 2.9.0
>