From: Maxime Ripard <maxime.ripard@free-electrons.com>
To: Chen-Yu Tsai <wens@csie.org>
Cc: LABBE Corentin <clabbe.montjoie@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Russell King <linux@armlinux.org.uk>,
David Miller <davem@davemloft.net>,
netdev <netdev@vger.kernel.org>,
devicetree <devicetree@vger.kernel.org>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
linux-kernel <linux-kernel@vger.kernel.org>,
linux-sunxi <linux-sunxi@googlegroups.com>
Subject: Re: [PATCH v2 1/5] ethernet: add sun8i-emac driver
Date: Sat, 30 Jul 2016 09:34:12 +0200 [thread overview]
Message-ID: <20160730073412.GL6215@lukather> (raw)
In-Reply-To: <CAGb2v678MidsiV=QJjk1bvAPL-hRFyNzZy636aObEG+HC908xw@mail.gmail.com>
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On Sat, Jul 30, 2016 at 09:30:01AM +0800, Chen-Yu Tsai wrote:
> >> > > +static void sun8i_emac_unset_syscon(struct net_device *ndev)
> >> > > +{
> >> > > + struct sun8i_emac_priv *priv = netdev_priv(ndev);
> >> > > + u32 reg = 0;
> >> > > +
> >> > > + if (priv->variant == H3_EMAC)
> >> > > + reg = H3_EPHY_DEFAULT_VALUE;
> >> >
> >> > Why do you need that?
> >> >
> >> For resetting the syscon to the factory default.
> >
> > Yes, but does it matter? Does it have any side effect? Is that
> > register shared with another device?
> >
> > Otherwise, either it won't be used anymore, and you don't care, or you
> > will reload the driver later, and the driver should work whatever
> > state is programmed in there. In both cases, you don't need to reset
> > that value.
>
> The "default" setting also disables and powers down the internal PHY.
> I think that's a good thing? The naming could be better.
Ah, it might, and that would obviously be the right thing to do. Using
a define for those enable and power down bits would be better though.
> >> > > +static irqreturn_t sun8i_emac_dma_interrupt(int irq, void *dev_id)
> >> > > +{
> >> > > + struct net_device *ndev = dev_id;
> >> > > + struct sun8i_emac_priv *priv = netdev_priv(ndev);
> >> > > + u32 v, u;
> >> > > +
> >> > > + v = readl(priv->base + SUN8I_EMAC_INT_STA);
> >> > > +
> >> > > + /* When this bit is asserted, a frame transmission is completed. */
> >> > > + if (v & BIT(0)) {
> >> > > + priv->estats.tx_int++;
> >> > > + writel(0, priv->base + SUN8I_EMAC_INT_EN);
> >> > > + napi_schedule(&priv->napi);
> >> > > + }
> >> > > +
> >> > > + /* When this bit is asserted, the TX DMA FSM is stopped. */
> >> > > + if (v & BIT(1))
> >> > > + priv->estats.tx_dma_stop++;
> >> > > +
> >> > > + /* When this asserted, the TX DMA can not acquire next TX descriptor
> >> > > + * and TX DMA FSM is suspended.
> >> > > + */
> >> > > + if (v & BIT(2))
> >> > > + priv->estats.tx_dma_ua++;
> >> > > +
> >> > > + if (v & BIT(3))
> >> > > + netif_dbg(priv, intr, ndev, "Unhandled interrupt TX TIMEOUT\n");
> >> >
> >> > Why do you enable that interrupt if you can't handle it?
> >>
> >> Some interrupt fire even when not enabled (like RX_BUF_UA_INT/TX_BUF_UA_INT)
> >
> > So the bits 9 and 2, respectively, in the interrupt enable register
> > are useless?
>
> Does it actually fire, i.e. pull the interrupt line on the GIC? Or is it just
> the interrupt state showing an event? IIRC some other hardware blocks have this
> behavior, such as the timer.
That's quite easy to implement, you can do a bitwise and on the status
and enable registers.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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next prev parent reply other threads:[~2016-07-30 7:34 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-07-20 8:03 [PATCH v2 0/5] net-next: ethernet: add sun8i-emac driver LABBE Corentin
2016-07-20 8:03 ` [PATCH v2 1/5] " LABBE Corentin
2016-07-20 9:56 ` Arnd Bergmann
2016-07-28 13:18 ` LABBE Corentin
2016-07-29 9:26 ` Arnd Bergmann
2016-07-25 19:54 ` Maxime Ripard
2016-07-28 14:57 ` LABBE Corentin
2016-07-29 17:25 ` Maxime Ripard
2016-07-30 1:30 ` Chen-Yu Tsai
2016-07-30 7:34 ` Maxime Ripard [this message]
2016-07-29 10:12 ` Andre Przywara
2016-08-24 12:02 ` LABBE Corentin
2016-08-26 20:49 ` Maxime Ripard
2016-07-20 8:03 ` [PATCH v2 2/5] MAINTAINERS: Add myself as maintainers of sun8i-emac LABBE Corentin
2016-07-20 8:03 ` [PATCH v2 3/5] ARM: sun8i: dt: Add DT bindings documentation for Allwinner sun8i-emac LABBE Corentin
2016-07-20 19:15 ` Rob Herring
2016-07-28 13:21 ` LABBE Corentin
2016-07-21 7:55 ` Maxime Ripard
2016-07-28 13:40 ` LABBE Corentin
2016-07-28 18:49 ` Maxime Ripard
2016-07-29 8:15 ` LABBE Corentin
2016-07-29 18:12 ` Maxime Ripard
2016-07-20 8:03 ` [PATCH v2 4/5] ARM: dts: sun8i-h3: add sun8i-emac ethernet driver LABBE Corentin
2016-07-20 8:03 ` [PATCH v2 5/5] ARM: dts: sun8i: Enable sun8i-emac on the Orange PI PC LABBE Corentin
2016-07-25 13:16 ` [PATCH v2 0/5] net-next: ethernet: add sun8i-emac driver paulo
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