* [PATCH 0/6] Introduce NextThing GR8 support
@ 2016-08-31 8:18 Maxime Ripard
2016-08-31 8:18 ` [PATCH 1/6] backlight: pwm_bl: Handle gpio that can sleep Maxime Ripard
` (5 more replies)
0 siblings, 6 replies; 20+ messages in thread
From: Maxime Ripard @ 2016-08-31 8:18 UTC (permalink / raw)
To: Linus Walleij, Chen-Yu Tsai, Maxime Ripard, Jingoo Han,
Lee Jones, Tomi Valkeinen, Daniel Vetter, David Airlie,
Thierry Reding
Cc: linux-arm-kernel, linux-kernel, linux-gpio, dri-devel,
linux-fbdev, Mylene Josserand, Thomas Petazzoni,
Alexander Kaplan
Hi,
This serie introduces the support for the NextThing GR8.
This SoC is loosely based on the SoCs of the Allwinner sun5i family,
hence we can use most of the support already there. Compared to the
already existing A10s and A13/R8, the pin layout completely changed,
meaning that also the set of available controllers is changed.
There's some new controllers (SPDIF) and some are gone
(Ethernet). This also introduces the support for the GR8 Evaluation
Board.
Even though it's not been tested yet, the SPDIF and I2S-related
components have been listed but we do not create a card from them, so
they won't be usable.
Let me know if you have any questions,
Maxime
Maxime Ripard (3):
backlight: pwm_bl: Handle gpio that can sleep
drm/panel: simple: Add A10 EVB 5 inch panel support
ARM: sunxi: Support the Nextthing GR8
Mylène Josserand (3):
pinctrl: sunxi: Add GR8 controller support
ARM: dts: Add NextThing GR8 dtsi
ARM: dts: gr8: Add support for the GR8 evaluation board
Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
MAINTAINERS | 1 +
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/gr8-evb.dts | 378 +++++++
arch/arm/boot/dts/gr8.dtsi | 1080 ++++++++++++++++++++
arch/arm/mach-sunxi/sunxi.c | 1 +
drivers/gpu/drm/panel/panel-simple.c | 26 +
drivers/pinctrl/sunxi/Kconfig | 4 +
drivers/pinctrl/sunxi/Makefile | 1 +
drivers/pinctrl/sunxi/pinctrl-gr8.c | 541 ++++++++++
drivers/video/backlight/pwm_bl.c | 4 +-
12 files changed, 2038 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/boot/dts/gr8-evb.dts
create mode 100644 arch/arm/boot/dts/gr8.dtsi
create mode 100644 drivers/pinctrl/sunxi/pinctrl-gr8.c
--
2.9.2
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 1/6] backlight: pwm_bl: Handle gpio that can sleep
2016-08-31 8:18 [PATCH 0/6] Introduce NextThing GR8 support Maxime Ripard
@ 2016-08-31 8:18 ` Maxime Ripard
2016-08-31 12:25 ` Lee Jones
2016-08-31 8:18 ` [PATCH 2/6] pinctrl: sunxi: Add GR8 controller support Maxime Ripard
` (4 subsequent siblings)
5 siblings, 1 reply; 20+ messages in thread
From: Maxime Ripard @ 2016-08-31 8:18 UTC (permalink / raw)
To: Linus Walleij, Chen-Yu Tsai, Maxime Ripard, Jingoo Han,
Lee Jones, Tomi Valkeinen, Daniel Vetter, David Airlie,
Thierry Reding
Cc: linux-arm-kernel, linux-kernel, linux-gpio, dri-devel,
linux-fbdev, Mylene Josserand, Thomas Petazzoni,
Alexander Kaplan
Some backlight GPIOs might be connected to some i2c based expanders whose
access might sleep.
Since it's not in any critical path, use the cansleep variant of the GPIO
API.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
drivers/video/backlight/pwm_bl.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/video/backlight/pwm_bl.c b/drivers/video/backlight/pwm_bl.c
index b2b366bb0f97..12614006211e 100644
--- a/drivers/video/backlight/pwm_bl.c
+++ b/drivers/video/backlight/pwm_bl.c
@@ -55,7 +55,7 @@ static void pwm_backlight_power_on(struct pwm_bl_data *pb, int brightness)
dev_err(pb->dev, "failed to enable power supply\n");
if (pb->enable_gpio)
- gpiod_set_value(pb->enable_gpio, 1);
+ gpiod_set_value_cansleep(pb->enable_gpio, 1);
pwm_enable(pb->pwm);
pb->enabled = true;
@@ -70,7 +70,7 @@ static void pwm_backlight_power_off(struct pwm_bl_data *pb)
pwm_disable(pb->pwm);
if (pb->enable_gpio)
- gpiod_set_value(pb->enable_gpio, 0);
+ gpiod_set_value_cansleep(pb->enable_gpio, 0);
regulator_disable(pb->power_supply);
pb->enabled = false;
--
2.9.2
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 2/6] pinctrl: sunxi: Add GR8 controller support
2016-08-31 8:18 [PATCH 0/6] Introduce NextThing GR8 support Maxime Ripard
2016-08-31 8:18 ` [PATCH 1/6] backlight: pwm_bl: Handle gpio that can sleep Maxime Ripard
@ 2016-08-31 8:18 ` Maxime Ripard
2016-09-05 12:49 ` Chen-Yu Tsai
2016-08-31 8:18 ` [PATCH 3/6] drm/panel: simple: Add A10 EVB 5 inch panel support Maxime Ripard
` (3 subsequent siblings)
5 siblings, 1 reply; 20+ messages in thread
From: Maxime Ripard @ 2016-08-31 8:18 UTC (permalink / raw)
To: Linus Walleij, Chen-Yu Tsai, Maxime Ripard, Jingoo Han,
Lee Jones, Tomi Valkeinen, Daniel Vetter, David Airlie,
Thierry Reding
Cc: linux-arm-kernel, linux-kernel, linux-gpio, dri-devel,
linux-fbdev, Mylene Josserand, Thomas Petazzoni,
Alexander Kaplan
From: Mylène Josserand <mylene.josserand@free-electrons.com>
Just like the other member of the sunxi family, let's add a pinctrl table
for the muxing options.
Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
drivers/pinctrl/sunxi/Kconfig | 4 +
drivers/pinctrl/sunxi/Makefile | 1 +
drivers/pinctrl/sunxi/pinctrl-gr8.c | 541 +++++++++++++++++++++
4 files changed, 547 insertions(+)
create mode 100644 drivers/pinctrl/sunxi/pinctrl-gr8.c
diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index 69617220c5d6..1685821eea41 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -23,6 +23,7 @@ Required properties:
"allwinner,sun8i-h3-pinctrl"
"allwinner,sun8i-h3-r-pinctrl"
"allwinner,sun50i-a64-pinctrl"
+ "nextthing,gr8-pinctrl"
- reg: Should contain the register physical address and length for the
pin controller.
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index aaf075b972f5..bff1ffc6f01e 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -17,6 +17,10 @@ config PINCTRL_SUN5I_A13
def_bool MACH_SUN5I
select PINCTRL_SUNXI
+config PINCTRL_GR8
+ def_bool MACH_SUN5I
+ select PINCTRL_SUNXI_COMMON
+
config PINCTRL_SUN6I_A31
def_bool MACH_SUN6I
select PINCTRL_SUNXI
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index 2d8b64e222e0..95f93d0561fc 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -5,6 +5,7 @@ obj-y += pinctrl-sunxi.o
obj-$(CONFIG_PINCTRL_SUN4I_A10) += pinctrl-sun4i-a10.o
obj-$(CONFIG_PINCTRL_SUN5I_A10S) += pinctrl-sun5i-a10s.o
obj-$(CONFIG_PINCTRL_SUN5I_A13) += pinctrl-sun5i-a13.o
+obj-$(CONFIG_PINCTRL_GR8) += pinctrl-gr8.o
obj-$(CONFIG_PINCTRL_SUN6I_A31) += pinctrl-sun6i-a31.o
obj-$(CONFIG_PINCTRL_SUN6I_A31S) += pinctrl-sun6i-a31s.o
obj-$(CONFIG_PINCTRL_SUN6I_A31_R) += pinctrl-sun6i-a31-r.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-gr8.c b/drivers/pinctrl/sunxi/pinctrl-gr8.c
new file mode 100644
index 000000000000..2904d2b7378b
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-gr8.c
@@ -0,0 +1,541 @@
+/*
+ * NextThing GR8 SoCs pinctrl driver.
+ *
+ * Copyright (C) 2016 Mylene Josserand
+ *
+ * Based on pinctrl-sun5i-a13.c
+ *
+ * Mylene Josserand <mylene.josserand@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin sun5i_gr8_pins[] = {
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "pwm0"),
+ SUNXI_FUNCTION(0x3, "spdif"), /* DO */
+ SUNXI_FUNCTION_IRQ(0x6, 16)), /* EINT16 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "ir0"), /* TX */
+ SUNXI_FUNCTION_IRQ(0x6, 17)), /* EINT17 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "ir0"), /* RX */
+ SUNXI_FUNCTION_IRQ(0x6, 18)), /* EINT18 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */
+ SUNXI_FUNCTION_IRQ(0x6, 19)), /* EINT19 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */
+ SUNXI_FUNCTION_IRQ(0x6, 20)), /* EINT20 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */
+ SUNXI_FUNCTION_IRQ(0x6, 21)), /* EINT21 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s0"), /* DO */
+ SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s0"), /* DI */
+ SUNXI_FUNCTION(0x3, "spdif"), /* DI */
+ SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */
+ SUNXI_FUNCTION(0x3, "spdif"), /* DO */
+ SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
+ SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */
+ SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
+ SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */
+ SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
+ SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */
+ SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
+ SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */
+ SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
+ SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
+ SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
+ SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */
+ SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0")), /* NRE */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NDQS */
+ SUNXI_FUNCTION(0x3, "uart2"), /* RX */
+ SUNXI_FUNCTION(0x4, "uart3")), /* RTS */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
+ SUNXI_FUNCTION(0x3, "uart2")), /* TX */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
+ SUNXI_FUNCTION(0x3, "uart2")), /* RX */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
+ SUNXI_FUNCTION(0x3, "uart2")), /* CTS */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
+ SUNXI_FUNCTION(0x3, "uart2")), /* RTS */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
+ SUNXI_FUNCTION(0x3, "emac")), /* ECRS */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
+ SUNXI_FUNCTION(0x3, "emac")), /* ECOL */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
+ SUNXI_FUNCTION(0x3, "emac")), /* ERXD0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
+ SUNXI_FUNCTION(0x3, "emac")), /* ERXD1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
+ SUNXI_FUNCTION(0x3, "emac")), /* ERXD2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
+ SUNXI_FUNCTION(0x3, "emac")), /* ERXD3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
+ SUNXI_FUNCTION(0x3, "emac")), /* ERXCK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
+ SUNXI_FUNCTION(0x3, "emac")), /* ERXERR */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
+ SUNXI_FUNCTION(0x3, "emac")), /* ERXDV */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
+ SUNXI_FUNCTION(0x3, "emac")), /* ETXD0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
+ SUNXI_FUNCTION(0x3, "emac")), /* ETXD1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
+ SUNXI_FUNCTION(0x3, "emac")), /* ETXD2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
+ SUNXI_FUNCTION(0x3, "emac")), /* ETXD3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
+ SUNXI_FUNCTION(0x3, "emac")), /* ETXEN */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
+ SUNXI_FUNCTION(0x3, "emac")), /* ETXCK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
+ SUNXI_FUNCTION(0x3, "emac")), /* ETXERR*/
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
+ SUNXI_FUNCTION(0x3, "emac")), /* EMDC */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
+ SUNXI_FUNCTION(0x3, "emac")), /* EMDIO */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x2, "ts0"), /* CLK */
+ SUNXI_FUNCTION(0x3, "csi0"), /* PCLK */
+ SUNXI_FUNCTION(0x4, "spi2"), /* CS0 */
+ SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x2, "ts0"), /* ERR */
+ SUNXI_FUNCTION(0x3, "csi0"), /* MCLK */
+ SUNXI_FUNCTION(0x4, "spi2"), /* CLK */
+ SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */
+ SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */
+ SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */
+ SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */
+ SUNXI_FUNCTION(0x4, "spi2")), /* MISO */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "ts0"), /* D0 */
+ SUNXI_FUNCTION(0x3, "csi0"), /* D0 */
+ SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "ts0"), /* D1 */
+ SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
+ SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "ts0"), /* D2 */
+ SUNXI_FUNCTION(0x3, "csi0"), /* D2 */
+ SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "ts0"), /* D3 */
+ SUNXI_FUNCTION(0x3, "csi0"), /* D3 */
+ SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "ts0"), /* D4 */
+ SUNXI_FUNCTION(0x3, "csi0"), /* D4 */
+ SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "ts0"), /* D5 */
+ SUNXI_FUNCTION(0x3, "csi0"), /* D5 */
+ SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "ts0"), /* D6 */
+ SUNXI_FUNCTION(0x3, "csi0"), /* D6 */
+ SUNXI_FUNCTION(0x4, "uart1")), /* TX */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "ts0"), /* D7 */
+ SUNXI_FUNCTION(0x3, "csi0"), /* D7 */
+ SUNXI_FUNCTION(0x4, "uart1")), /* RX */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
+ SUNXI_FUNCTION(0x4, "jtag")), /* MS1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
+ SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
+ SUNXI_FUNCTION(0x4, "uart0")), /* TX */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
+ SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
+ SUNXI_FUNCTION(0x4, "uart0")), /* RX */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
+ SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x2, "gps"), /* CLK */
+ SUNXI_FUNCTION_IRQ(0x6, 0)), /* EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x2, "gps"), /* SIGN */
+ SUNXI_FUNCTION_IRQ(0x6, 1)), /* EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x2, "gps"), /* MAG */
+ SUNXI_FUNCTION_IRQ(0x6, 2)), /* EINT2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
+ SUNXI_FUNCTION(0x3, "ms"), /* BS */
+ SUNXI_FUNCTION(0x4, "uart1"), /* TX */
+ SUNXI_FUNCTION_IRQ(0x6, 3)), /* EINT3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
+ SUNXI_FUNCTION(0x3, "ms"), /* CLK */
+ SUNXI_FUNCTION(0x4, "uart1"), /* RX */
+ SUNXI_FUNCTION_IRQ(0x6, 4)), /* EINT4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
+ SUNXI_FUNCTION(0x3, "ms"), /* D0 */
+ SUNXI_FUNCTION(0x4, "uart1"), /* CTS */
+ SUNXI_FUNCTION_IRQ(0x6, 5)), /* EINT5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
+ SUNXI_FUNCTION(0x3, "ms"), /* D1 */
+ SUNXI_FUNCTION(0x4, "uart1"), /* RTS */
+ SUNXI_FUNCTION(0x5, "uart2"), /* RTS */
+ SUNXI_FUNCTION_IRQ(0x6, 6)), /* EINT6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
+ SUNXI_FUNCTION(0x3, "ms"), /* D2 */
+ SUNXI_FUNCTION(0x5, "uart2"), /* TX */
+ SUNXI_FUNCTION_IRQ(0x6, 7)), /* EINT7 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
+ SUNXI_FUNCTION(0x3, "ms"), /* D3 */
+ SUNXI_FUNCTION(0x5, "uart2"), /* RX */
+ SUNXI_FUNCTION_IRQ(0x6, 8)), /* EINT8 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
+ SUNXI_FUNCTION(0x3, "uart3"), /* TX */
+ SUNXI_FUNCTION_IRQ(0x6, 9)), /* EINT9 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
+ SUNXI_FUNCTION(0x3, "uart3"), /* RX */
+ SUNXI_FUNCTION_IRQ(0x6, 10)), /* EINT10 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
+ SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
+ SUNXI_FUNCTION_IRQ(0x6, 11)), /* EINT11 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
+ SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
+ SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
+ SUNXI_FUNCTION(0x3, "pwm1"),
+ SUNXI_FUNCTION(0x5, "uart2"), /* CTS */
+ SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */
+};
+
+static const struct sunxi_pinctrl_desc sun5i_gr8_pinctrl_data = {
+ .pins = sun5i_gr8_pins,
+ .npins = ARRAY_SIZE(sun5i_gr8_pins),
+ .irq_banks = 1,
+};
+
+static int sun5i_gr8_pinctrl_probe(struct platform_device *pdev)
+{
+ return sunxi_pinctrl_init(pdev,
+ &sun5i_gr8_pinctrl_data);
+}
+
+static const struct of_device_id sun5i_gr8_pinctrl_match[] = {
+ { .compatible = "nextthing,gr8-pinctrl", },
+ {}
+};
+MODULE_DEVICE_TABLE(of, sun5i_gr8_pinctrl_match);
+
+static struct platform_driver sun5i_gr8_pinctrl_driver = {
+ .probe = sun5i_gr8_pinctrl_probe,
+ .driver = {
+ .name = "gr8-pinctrl",
+ .of_match_table = sun5i_gr8_pinctrl_match,
+ },
+};
+module_platform_driver(sun5i_gr8_pinctrl_driver);
+
+MODULE_AUTHOR("Mylene Josserand <mylene.josserand@free-electrons.com");
+MODULE_DESCRIPTION("NextThing GR8 pinctrl driver");
+MODULE_LICENSE("GPL");
--
2.9.2
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 3/6] drm/panel: simple: Add A10 EVB 5 inch panel support
2016-08-31 8:18 [PATCH 0/6] Introduce NextThing GR8 support Maxime Ripard
2016-08-31 8:18 ` [PATCH 1/6] backlight: pwm_bl: Handle gpio that can sleep Maxime Ripard
2016-08-31 8:18 ` [PATCH 2/6] pinctrl: sunxi: Add GR8 controller support Maxime Ripard
@ 2016-08-31 8:18 ` Maxime Ripard
2016-09-05 14:00 ` Chen-Yu Tsai
2016-08-31 8:18 ` [PATCH 4/6] ARM: sunxi: Support the Nextthing GR8 Maxime Ripard
` (2 subsequent siblings)
5 siblings, 1 reply; 20+ messages in thread
From: Maxime Ripard @ 2016-08-31 8:18 UTC (permalink / raw)
To: Linus Walleij, Chen-Yu Tsai, Maxime Ripard, Jingoo Han,
Lee Jones, Tomi Valkeinen, Daniel Vetter, David Airlie,
Thierry Reding
Cc: linux-arm-kernel, linux-kernel, linux-gpio, dri-devel,
linux-fbdev, Mylene Josserand, Thomas Petazzoni,
Alexander Kaplan
The A10-EVB from Allwinner comes with an unidentified panel, with the only
mark on the PCB being A10-SUB-EVB-5LCD.
Add timings to simple panel to handle it.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
drivers/gpu/drm/panel/panel-simple.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
index 85143d1b9b31..be371b053aab 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -386,6 +386,29 @@ static void panel_simple_shutdown(struct device *dev)
panel_simple_disable(&panel->base);
}
+static const struct drm_display_mode allwinner_a10_sub_evb_5lcd_mode = {
+ .clock = 33000,
+ .hdisplay = 800,
+ .hsync_start = 800 + 209,
+ .hsync_end = 800 + 209 + 1,
+ .htotal = 800 + 209 + 1 + 45,
+ .vdisplay = 480,
+ .vsync_start = 480 + 22,
+ .vsync_end = 480 + 22 + 1,
+ .vtotal = 480 + 22 + 1 + 22,
+ .vrefresh = 60,
+};
+
+static const struct panel_desc allwinner_a10_sub_evb_5lcd = {
+ .modes = &allwinner_a10_sub_evb_5lcd_mode,
+ .num_modes = 1,
+ .size = {
+ .width = 110,
+ .height = 67,
+ },
+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
+};
+
static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
.clock = 33333,
.hdisplay = 800,
@@ -1515,6 +1538,9 @@ static const struct panel_desc urt_umsh_8596md_parallel = {
static const struct of_device_id platform_of_match[] = {
{
+ .compatible = "allwinner,sun4i-a10-sub-evb-5-lcd",
+ .data = &allwinner_a10_sub_evb_5lcd,
+ }, {
.compatible = "ampire,am800480r3tmqwa1h",
.data = &ire_am800480r3tmqwa1h,
}, {
--
2.9.2
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 4/6] ARM: sunxi: Support the Nextthing GR8
2016-08-31 8:18 [PATCH 0/6] Introduce NextThing GR8 support Maxime Ripard
` (2 preceding siblings ...)
2016-08-31 8:18 ` [PATCH 3/6] drm/panel: simple: Add A10 EVB 5 inch panel support Maxime Ripard
@ 2016-08-31 8:18 ` Maxime Ripard
2016-08-31 8:25 ` Chen-Yu Tsai
2016-08-31 8:18 ` [PATCH 5/6] ARM: dts: Add NextThing GR8 dtsi Maxime Ripard
2016-08-31 8:18 ` [PATCH 6/6] ARM: dts: gr8: Add support for the GR8 evaluation board Maxime Ripard
5 siblings, 1 reply; 20+ messages in thread
From: Maxime Ripard @ 2016-08-31 8:18 UTC (permalink / raw)
To: Linus Walleij, Chen-Yu Tsai, Maxime Ripard, Jingoo Han,
Lee Jones, Tomi Valkeinen, Daniel Vetter, David Airlie,
Thierry Reding
Cc: linux-arm-kernel, linux-kernel, linux-gpio, dri-devel,
linux-fbdev, Mylene Josserand, Thomas Petazzoni,
Alexander Kaplan
The GR8 is an SoC made by Nextthing Co, loosely based on the sun5i family.
It has a number of new controllers compared to the A10s and A13 (SPDIF, I2S),
but some controllers missing too (Ethernet, less I2C, less UARTs).
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
MAINTAINERS | 1 +
arch/arm/mach-sunxi/sunxi.c | 1 +
3 files changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
index 7e79fcc36b0d..3975d0a0e4c2 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.txt
+++ b/Documentation/devicetree/bindings/arm/sunxi.txt
@@ -14,3 +14,4 @@ using one of the following compatible strings:
allwinner,sun8i-a83t
allwinner,sun8i-h3
allwinner,sun9i-a80
+ nextthing,gr8
diff --git a/MAINTAINERS b/MAINTAINERS
index 20bb1d00098c..c6a9e6fda1d0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -982,6 +982,7 @@ M: Chen-Yu Tsai <wens@csie.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
N: sun[x456789]i
+F: arch/arm/boot/dts/gr8*
ARM/Allwinner SoC Clock Support
M: Emilio López <emilio@elopez.com.ar>
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 95dca8c2c9ed..2e2bde271205 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -22,6 +22,7 @@ static const char * const sunxi_board_dt_compat[] = {
"allwinner,sun5i-a10s",
"allwinner,sun5i-a13",
"allwinner,sun5i-r8",
+ "nextthing,gr8",
NULL,
};
--
2.9.2
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 5/6] ARM: dts: Add NextThing GR8 dtsi
2016-08-31 8:18 [PATCH 0/6] Introduce NextThing GR8 support Maxime Ripard
` (3 preceding siblings ...)
2016-08-31 8:18 ` [PATCH 4/6] ARM: sunxi: Support the Nextthing GR8 Maxime Ripard
@ 2016-08-31 8:18 ` Maxime Ripard
2016-09-05 12:47 ` Chen-Yu Tsai
` (2 more replies)
2016-08-31 8:18 ` [PATCH 6/6] ARM: dts: gr8: Add support for the GR8 evaluation board Maxime Ripard
5 siblings, 3 replies; 20+ messages in thread
From: Maxime Ripard @ 2016-08-31 8:18 UTC (permalink / raw)
To: Linus Walleij, Chen-Yu Tsai, Maxime Ripard, Jingoo Han,
Lee Jones, Tomi Valkeinen, Daniel Vetter, David Airlie,
Thierry Reding
Cc: linux-arm-kernel, linux-kernel, linux-gpio, dri-devel,
linux-fbdev, Mylene Josserand, Thomas Petazzoni,
Alexander Kaplan
From: Mylène Josserand <mylene.josserand@free-electrons.com>
The GR8 is an SoC made by Nextthing loosely based on the sun5i family.
Since it's not clear yet what we can factor out and merge with the A10s and
A13 support, let's keep it out of the sun5i.dtsi include tree. We will
figure out what can be shared when things settle down.
Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/gr8.dtsi | 1080 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 1080 insertions(+)
create mode 100644 arch/arm/boot/dts/gr8.dtsi
diff --git a/arch/arm/boot/dts/gr8.dtsi b/arch/arm/boot/dts/gr8.dtsi
new file mode 100644
index 000000000000..d21cfa3f3c14
--- /dev/null
+++ b/arch/arm/boot/dts/gr8.dtsi
@@ -0,0 +1,1080 @@
+/*
+ * Copyright 2016 Mylène Josserand
+ *
+ * Mylène Josserand <mylene.josserand@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "skeleton.dtsi"
+
+#include <dt-bindings/clock/sun4i-a10-pll2.h>
+#include <dt-bindings/dma/sun4i-a10.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ interrupt-parent = <&intc>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a8";
+ reg = <0x0>;
+ clocks = <&cpu>;
+ };
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ /*
+ * This is a dummy clock, to be used as placeholder on
+ * other mux clocks when a specific parent clock is not
+ * yet implemented. It should be dropped when the driver
+ * is complete.
+ */
+ dummy: dummy {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ osc24M: clk@01c20050 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-osc-clk";
+ reg = <0x01c20050 0x4>;
+ clock-frequency = <24000000>;
+ clock-output-names = "osc24M";
+ };
+
+ osc3M: osc3M_clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clock-div = <8>;
+ clock-mult = <1>;
+ clocks = <&osc24M>;
+ clock-output-names = "osc3M";
+ };
+
+ osc32k: clk@0 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "osc32k";
+ };
+
+ pll1: clk@01c20000 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-pll1-clk";
+ reg = <0x01c20000 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll1";
+ };
+
+ pll2: clk@01c20008 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun5i-a13-pll2-clk";
+ reg = <0x01c20008 0x8>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll2-1x", "pll2-2x",
+ "pll2-4x", "pll2-8x";
+ };
+
+ pll3: clk@01c20010 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-pll3-clk";
+ reg = <0x01c20010 0x4>;
+ clocks = <&osc3M>;
+ clock-output-names = "pll3";
+ };
+
+ pll3x2: pll3x2_clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <2>;
+ clocks = <&pll3>;
+ clock-output-names = "pll3-2x";
+ };
+
+ pll4: clk@01c20018 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-pll1-clk";
+ reg = <0x01c20018 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll4";
+ };
+
+ pll5: clk@01c20020 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-pll5-clk";
+ reg = <0x01c20020 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll5_ddr", "pll5_other";
+ };
+
+ pll6: clk@01c20028 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-pll6-clk";
+ reg = <0x01c20028 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll6_sata", "pll6_other", "pll6";
+ };
+
+ pll7: clk@01c20030 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-pll3-clk";
+ reg = <0x01c20030 0x4>;
+ clocks = <&osc3M>;
+ clock-output-names = "pll7";
+ };
+
+ pll7x2: pll7x2_clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <2>;
+ clocks = <&pll7>;
+ clock-output-names = "pll7-2x";
+ };
+
+ /* dummy is 200M */
+ cpu: cpu@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-cpu-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
+ clock-output-names = "cpu";
+ };
+
+ axi: axi@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-axi-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&cpu>;
+ clock-output-names = "axi";
+ };
+
+ ahb: ahb@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun5i-a13-ahb-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&axi>, <&cpu>, <&pll6 1>;
+ clock-output-names = "ahb";
+ /*
+ * Use PLL6 as parent, instead of CPU/AXI
+ * which has rate changes due to cpufreq
+ */
+ assigned-clocks = <&ahb>;
+ assigned-clock-parents = <&pll6 1>;
+ };
+
+ apb0: apb0@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-apb0-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&ahb>;
+ clock-output-names = "apb0";
+ };
+
+ apb1: clk@01c20058 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-apb1-clk";
+ reg = <0x01c20058 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
+ clock-output-names = "apb1";
+ };
+
+ axi_gates: clk@01c2005c {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-axi-gates-clk";
+ reg = <0x01c2005c 0x4>;
+ clocks = <&axi>;
+ clock-indices = <0>;
+ clock-output-names = "axi_dram";
+ };
+
+ ahb_gates: clk@01c20060 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun5i-a13-ahb-gates-clk";
+ reg = <0x01c20060 0x8>;
+ clocks = <&ahb>;
+ clock-indices = <0>, <1>,
+ <2>, <5>, <6>,
+ <7>, <8>, <9>,
+ <10>, <13>,
+ <14>, <20>,
+ <21>, <22>,
+ <28>, <32>, <34>,
+ <36>, <40>, <44>,
+ <46>, <51>,
+ <52>;
+ clock-output-names = "ahb_usbotg", "ahb_ehci",
+ "ahb_ohci", "ahb_ss", "ahb_dma",
+ "ahb_bist", "ahb_mmc0", "ahb_mmc1",
+ "ahb_mmc2", "ahb_nand",
+ "ahb_sdram", "ahb_spi0",
+ "ahb_spi1", "ahb_spi2",
+ "ahb_stimer", "ahb_ve", "ahb_tve",
+ "ahb_lcd", "ahb_csi", "ahb_de_be",
+ "ahb_de_fe", "ahb_iep",
+ "ahb_mali400";
+ };
+
+ apb0_gates: clk@01c20068 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun5i-a13-apb0-gates-clk";
+ reg = <0x01c20068 0x4>;
+ clocks = <&apb0>;
+ clock-indices = <0>, <3>,
+ <5>, <6>;
+ clock-output-names = "apb0_codec", "apb0_i2s0",
+ "apb0_pio", "apb0_ir";
+ };
+
+ apb1_gates: clk@01c2006c {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun5i-a13-apb1-gates-clk";
+ reg = <0x01c2006c 0x4>;
+ clocks = <&apb1>;
+ clock-indices = <0>, <1>,
+ <2>, <17>,
+ <18>;
+ clock-output-names = "apb1_i2c0", "apb1_i2c1",
+ "apb1_i2c2", "apb1_uart1",
+ "apb1_uart2";
+ };
+
+ nand_clk: clk@01c20080 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c20080 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "nand";
+ };
+
+ ms_clk: clk@01c20084 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c20084 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "ms";
+ };
+
+ mmc0_clk: clk@01c20088 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-mmc-clk";
+ reg = <0x01c20088 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "mmc0",
+ "mmc0_output",
+ "mmc0_sample";
+ };
+
+ mmc1_clk: clk@01c2008c {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-mmc-clk";
+ reg = <0x01c2008c 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "mmc1",
+ "mmc1_output",
+ "mmc1_sample";
+ };
+
+ mmc2_clk: clk@01c20090 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-mmc-clk";
+ reg = <0x01c20090 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "mmc2",
+ "mmc2_output",
+ "mmc2_sample";
+ };
+
+ ts_clk: clk@01c20098 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c20098 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "ts";
+ };
+
+ ss_clk: clk@01c2009c {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c2009c 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "ss";
+ };
+
+ spi0_clk: clk@01c200a0 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200a0 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "spi0";
+ };
+
+ spi1_clk: clk@01c200a4 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200a4 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "spi1";
+ };
+
+ spi2_clk: clk@01c200a8 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200a8 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "spi2";
+ };
+
+ ir0_clk: clk@01c200b0 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200b0 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "ir0";
+ };
+
+ i2s0_clk: clk@01c200b8 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod1-clk";
+ reg = <0x01c200b8 0x4>;
+ clocks = <&pll2 SUN4I_A10_PLL2_8X>,
+ <&pll2 SUN4I_A10_PLL2_4X>,
+ <&pll2 SUN4I_A10_PLL2_2X>,
+ <&pll2 SUN4I_A10_PLL2_1X>;
+ clock-output-names = "i2s0";
+ };
+
+ spdif_clk: clk@01c200c0 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod1-clk";
+ reg = <0x01c200c0 0x4>;
+ clocks = <&pll2 SUN4I_A10_PLL2_8X>,
+ <&pll2 SUN4I_A10_PLL2_4X>,
+ <&pll2 SUN4I_A10_PLL2_2X>,
+ <&pll2 SUN4I_A10_PLL2_1X>;
+ clock-output-names = "spdif";
+ };
+
+ usb_clk: clk@01c200cc {
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ compatible = "allwinner,sun5i-a13-usb-clk";
+ reg = <0x01c200cc 0x4>;
+ clocks = <&pll6 1>;
+ clock-output-names = "usb_ohci0", "usb_phy";
+ };
+
+ dram_gates: clk@01c20100 {
+ #clock-cells = <1>;
+ compatible = "nextthing,gr8-dram-gates-clk",
+ "allwinner,sun4i-a10-gates-clk";
+ reg = <0x01c20100 0x4>;
+ clocks = <&pll5 0>;
+ clock-indices = <0>,
+ <1>,
+ <25>,
+ <26>,
+ <29>,
+ <31>;
+ clock-output-names = "dram_ve",
+ "dram_csi",
+ "dram_de_fe",
+ "dram_de_be",
+ "dram_ace",
+ "dram_iep";
+ };
+
+ de_be_clk: clk@01c20104 {
+ #clock-cells = <0>;
+ #reset-cells = <0>;
+ compatible = "allwinner,sun4i-a10-display-clk";
+ reg = <0x01c20104 0x4>;
+ clocks = <&pll3>, <&pll7>, <&pll5 1>;
+ clock-output-names = "de-be";
+ };
+
+ de_fe_clk: clk@01c2010c {
+ #clock-cells = <0>;
+ #reset-cells = <0>;
+ compatible = "allwinner,sun4i-a10-display-clk";
+ reg = <0x01c2010c 0x4>;
+ clocks = <&pll3>, <&pll7>, <&pll5 1>;
+ clock-output-names = "de-fe";
+ };
+
+ tcon_ch0_clk: clk@01c20118 {
+ #clock-cells = <0>;
+ #reset-cells = <1>;
+ compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
+ reg = <0x01c20118 0x4>;
+ clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
+ clock-output-names = "tcon-ch0-sclk";
+ };
+
+ tcon_ch1_clk: clk@01c2012c {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
+ reg = <0x01c2012c 0x4>;
+ clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
+ clock-output-names = "tcon-ch1-sclk";
+ };
+
+ codec_clk: clk@01c20140 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-codec-clk";
+ reg = <0x01c20140 0x4>;
+ clocks = <&pll2 SUN4I_A10_PLL2_1X>;
+ clock-output-names = "codec";
+ };
+
+ mbus_clk: clk@01c2015c {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun5i-a13-mbus-clk";
+ reg = <0x01c2015c 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "mbus";
+ };
+ };
+
+ display-engine {
+ compatible = "allwinner,sun5i-a13-display-engine";
+ allwinner,pipelines = <&fe0>;
+ };
+
+ soc@01c00000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ sram-controller@01c00000 {
+ compatible = "allwinner,sun4i-a10-sram-controller";
+ reg = <0x01c00000 0x30>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ sram_a: sram@00000000 {
+ compatible = "mmio-sram";
+ reg = <0x00000000 0xc000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x00000000 0xc000>;
+ };
+
+ sram_d: sram@00010000 {
+ compatible = "mmio-sram";
+ reg = <0x00010000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x00010000 0x1000>;
+
+ otg_sram: sram-section@0000 {
+ compatible = "allwinner,sun4i-a10-sram-d";
+ reg = <0x0000 0x1000>;
+ status = "disabled";
+ };
+ };
+ };
+
+ dma: dma-controller@01c02000 {
+ compatible = "allwinner,sun4i-a10-dma";
+ reg = <0x01c02000 0x1000>;
+ interrupts = <27>;
+ clocks = <&ahb_gates 6>;
+ #dma-cells = <2>;
+ };
+
+ nfc: nand@01c03000 {
+ compatible = "allwinner,sun4i-a10-nand";
+ reg = <0x01c03000 0x1000>;
+ interrupts = <37>;
+ clocks = <&ahb_gates 13>, <&nand_clk>;
+ clock-names = "ahb", "mod";
+ dmas = <&dma SUN4I_DMA_DEDICATED 3>;
+ dma-names = "rxtx";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi0: spi@01c05000 {
+ compatible = "allwinner,sun4i-a10-spi";
+ reg = <0x01c05000 0x1000>;
+ interrupts = <10>;
+ clocks = <&ahb_gates 20>, <&spi0_clk>;
+ clock-names = "ahb", "mod";
+ dmas = <&dma SUN4I_DMA_DEDICATED 27>,
+ <&dma SUN4I_DMA_DEDICATED 26>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi1: spi@01c06000 {
+ compatible = "allwinner,sun4i-a10-spi";
+ reg = <0x01c06000 0x1000>;
+ interrupts = <11>;
+ clocks = <&ahb_gates 21>, <&spi1_clk>;
+ clock-names = "ahb", "mod";
+ dmas = <&dma SUN4I_DMA_DEDICATED 9>,
+ <&dma SUN4I_DMA_DEDICATED 8>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ tve0: tv-encoder@01c0a000 {
+ compatible = "allwinner,sun4i-a10-tv-encoder";
+ reg = <0x01c0a000 0x1000>;
+ clocks = <&ahb_gates 34>;
+ resets = <&tcon_ch0_clk 0>;
+ status = "disabled";
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tve0_in_tcon0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon0_out_tve0>;
+ };
+ };
+ };
+
+ tcon0: lcd-controller@01c0c000 {
+ compatible = "allwinner,sun5i-a13-tcon";
+ reg = <0x01c0c000 0x1000>;
+ interrupts = <44>;
+ resets = <&tcon_ch0_clk 1>;
+ reset-names = "lcd";
+ clocks = <&ahb_gates 36>,
+ <&tcon_ch0_clk>,
+ <&tcon_ch1_clk>;
+ clock-names = "ahb",
+ "tcon-ch0",
+ "tcon-ch1";
+ clock-output-names = "tcon-pixel-clock";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tcon0_in_be0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&be0_out_tcon0>;
+ };
+ };
+
+ tcon0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ tcon0_out_tve0: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&tve0_in_tcon0>;
+ };
+ };
+ };
+ };
+
+ mmc0: mmc@01c0f000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c0f000 0x1000>;
+ clocks = <&ahb_gates 8>,
+ <&mmc0_clk 0>,
+ <&mmc0_clk 1>,
+ <&mmc0_clk 2>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ interrupts = <32>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc1: mmc@01c10000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c10000 0x1000>;
+ clocks = <&ahb_gates 9>,
+ <&mmc1_clk 0>,
+ <&mmc1_clk 1>,
+ <&mmc1_clk 2>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ interrupts = <33>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc2: mmc@01c11000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c11000 0x1000>;
+ clocks = <&ahb_gates 10>,
+ <&mmc2_clk 0>,
+ <&mmc2_clk 1>,
+ <&mmc2_clk 2>;
+ clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+ interrupts = <34>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ usb_otg: usb@01c13000 {
+ compatible = "allwinner,sun4i-a10-musb";
+ reg = <0x01c13000 0x0400>;
+ clocks = <&ahb_gates 0>;
+ interrupts = <38>;
+ interrupt-names = "mc";
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ extcon = <&usbphy 0>;
+ allwinner,sram = <&otg_sram 1>;
+ status = "disabled";
+
+ dr_mode = "otg";
+ };
+
+ usbphy: phy@01c13400 {
+ #phy-cells = <1>;
+ compatible = "allwinner,sun5i-a13-usb-phy";
+ reg = <0x01c13400 0x10 0x01c14800 0x4>;
+ reg-names = "phy_ctrl", "pmu1";
+ clocks = <&usb_clk 8>;
+ clock-names = "usb_phy";
+ resets = <&usb_clk 0>, <&usb_clk 1>;
+ reset-names = "usb0_reset", "usb1_reset";
+ status = "disabled";
+ };
+
+ ehci0: usb@01c14000 {
+ compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
+ reg = <0x01c14000 0x100>;
+ interrupts = <39>;
+ clocks = <&ahb_gates 1>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci0: usb@01c14400 {
+ compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
+ reg = <0x01c14400 0x100>;
+ interrupts = <40>;
+ clocks = <&usb_clk 6>, <&ahb_gates 2>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ spi2: spi@01c17000 {
+ compatible = "allwinner,sun4i-a10-spi";
+ reg = <0x01c17000 0x1000>;
+ interrupts = <12>;
+ clocks = <&ahb_gates 22>, <&spi2_clk>;
+ clock-names = "ahb", "mod";
+ dmas = <&dma SUN4I_DMA_DEDICATED 29>,
+ <&dma SUN4I_DMA_DEDICATED 28>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ intc: interrupt-controller@01c20400 {
+ compatible = "allwinner,sun4i-a10-ic";
+ reg = <0x01c20400 0x400>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ pio: pinctrl@01c20800 {
+ compatible = "nextthing,gr8-pinctrl";
+ reg = <0x01c20800 0x400>;
+ interrupts = <28>;
+ clocks = <&apb0_gates 5>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #gpio-cells = <3>;
+
+ i2c0_pins_a: i2c0@0 {
+ allwinner,pins = "PB0", "PB1";
+ allwinner,function = "i2c0";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ i2c1_pins_a: i2c1@0 {
+ allwinner,pins = "PB15", "PB16";
+ allwinner,function = "i2c1";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ i2c2_pins_a: i2c2@0 {
+ allwinner,pins = "PB17", "PB18";
+ allwinner,function = "i2c2";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ i2s0_pins_a: i2s0@0 {
+ allwinner,pins = "PB5", "PB6", "PB7", "PB8", "PB9";
+ allwinner,function = "i2s0";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ ir0_rx_pins_a: ir0@0 {
+ allwinner,pins = "PB4";
+ allwinner,function = "ir0";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ lcd_rgb666_pins: lcd_rgb666@0 {
+ allwinner,pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
+ "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
+ "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
+ "PD24", "PD25", "PD26", "PD27";
+ allwinner,function = "lcd0";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ mmc0_pins_a: mmc0@0 {
+ allwinner,pins = "PF0", "PF1", "PF2", "PF3",
+ "PF4", "PF5";
+ allwinner,function = "mmc0";
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ nand_pins_a: nand_base0@0 {
+ allwinner,pins = "PC0", "PC1", "PC2",
+ "PC5", "PC8", "PC9", "PC10",
+ "PC11", "PC12", "PC13", "PC14",
+ "PC15";
+ allwinner,function = "nand0";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ nand_cs0_pins_a: nand_cs@0 {
+ allwinner,pins = "PC4";
+ allwinner,function = "nand0";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ nand_rb0_pins_a: nand_rb@0 {
+ allwinner,pins = "PC6";
+ allwinner,function = "nand0";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ uart1_pins_a: uart1@1 {
+ allwinner,pins = "PG3", "PG4";
+ allwinner,function = "uart1";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ uart1_cts_rts_pins_a: uart1-cts-rts@0 {
+ allwinner,pins = "PG5", "PG6";
+ allwinner,function = "uart1";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ pwm0_pins_a: pwm0@0 {
+ allwinner,pins = "PB2";
+ allwinner,function = "pwm0";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ spdif_tx_pins_a: spdif@0 {
+ allwinner,pins = "PB10";
+ allwinner,function = "spdif";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+ };
+
+ pwm: pwm@01c20e00 {
+ compatible = "allwinner,sun5i-a10s-pwm";
+ reg = <0x01c20e00 0xc>;
+ clocks = <&osc24M>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ timer@01c20c00 {
+ compatible = "allwinner,sun4i-a10-timer";
+ reg = <0x01c20c00 0x90>;
+ interrupts = <22>;
+ clocks = <&osc24M>;
+ };
+
+ wdt: watchdog@01c20c90 {
+ compatible = "allwinner,sun4i-a10-wdt";
+ reg = <0x01c20c90 0x10>;
+ };
+
+ spdif: spdif@01c21000 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun4i-a10-spdif";
+ reg = <0x01c21000 0x400>;
+ interrupts = <13>;
+ clocks = <&apb0_gates 1>, <&spdif_clk>;
+ clock-names = "apb", "spdif";
+ dmas = <&dma SUN4I_DMA_NORMAL 2>,
+ <&dma SUN4I_DMA_NORMAL 2>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ ir0: ir@01c21800 {
+ compatible = "allwinner,sun4i-a10-ir";
+ clocks = <&apb0_gates 6>, <&ir0_clk>;
+ clock-names = "apb", "ir";
+ interrupts = <5>;
+ reg = <0x01c21800 0x40>;
+ status = "disabled";
+ };
+
+ i2s0: i2s@01c22400 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun4i-a10-i2s";
+ reg = <0x01c22400 0x400>;
+ interrupts = <16>;
+ clocks = <&apb0_gates 3>, <&i2s0_clk>;
+ clock-names = "apb", "mod";
+ dmas = <&dma SUN4I_DMA_NORMAL 3>,
+ <&dma SUN4I_DMA_NORMAL 3>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ lradc: lradc@01c22800 {
+ compatible = "allwinner,sun4i-a10-lradc-keys";
+ reg = <0x01c22800 0x100>;
+ interrupts = <31>;
+ status = "disabled";
+ };
+
+ codec: codec@01c22c00 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun4i-a10-codec";
+ reg = <0x01c22c00 0x40>;
+ interrupts = <30>;
+ clocks = <&apb0_gates 0>, <&codec_clk>;
+ clock-names = "apb", "codec";
+ dmas = <&dma SUN4I_DMA_NORMAL 19>,
+ <&dma SUN4I_DMA_NORMAL 19>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ rtp: rtp@01c25000 {
+ compatible = "allwinner,sun5i-a13-ts";
+ reg = <0x01c25000 0x100>;
+ interrupts = <29>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ uart1: serial@01c28400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28400 0x400>;
+ interrupts = <2>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb1_gates 17>;
+ status = "disabled";
+ };
+
+ uart2: serial@01c28800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28800 0x400>;
+ interrupts = <3>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb1_gates 18>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@01c2ac00 {
+ compatible = "allwinner,sun4i-a10-i2c";
+ reg = <0x01c2ac00 0x400>;
+ interrupts = <7>;
+ clocks = <&apb1_gates 0>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1: i2c@01c2b000 {
+ compatible = "allwinner,sun4i-a10-i2c";
+ reg = <0x01c2b000 0x400>;
+ interrupts = <8>;
+ clocks = <&apb1_gates 1>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c2: i2c@01c2b400 {
+ compatible = "allwinner,sun4i-a10-i2c";
+ reg = <0x01c2b400 0x400>;
+ interrupts = <9>;
+ clocks = <&apb1_gates 2>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ timer@01c60000 {
+ compatible = "allwinner,sun5i-a13-hstimer";
+ reg = <0x01c60000 0x1000>;
+ interrupts = <82>, <83>;
+ clocks = <&ahb_gates 28>;
+ };
+
+ fe0: display-frontend@01e00000 {
+ compatible = "allwinner,sun5i-a13-display-frontend";
+ reg = <0x01e00000 0x20000>;
+ interrupts = <47>;
+ clocks = <&ahb_gates 46>, <&de_fe_clk>,
+ <&dram_gates 25>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = <&de_fe_clk>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fe0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ fe0_out_be0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&be0_in_fe0>;
+ };
+ };
+ };
+ };
+
+ be0: display-backend@01e60000 {
+ compatible = "allwinner,sun5i-a13-display-backend";
+ reg = <0x01e60000 0x10000>;
+ clocks = <&ahb_gates 44>, <&de_be_clk>,
+ <&dram_gates 26>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = <&de_be_clk>;
+ status = "disabled";
+
+ assigned-clocks = <&de_be_clk>;
+ assigned-clock-rates = <300000000>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ be0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ be0_in_fe0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&fe0_out_be0>;
+ };
+ };
+
+ be0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ be0_out_tcon0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon0_in_be0>;
+ };
+ };
+ };
+ };
+ };
+};
--
2.9.2
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 6/6] ARM: dts: gr8: Add support for the GR8 evaluation board
2016-08-31 8:18 [PATCH 0/6] Introduce NextThing GR8 support Maxime Ripard
` (4 preceding siblings ...)
2016-08-31 8:18 ` [PATCH 5/6] ARM: dts: Add NextThing GR8 dtsi Maxime Ripard
@ 2016-08-31 8:18 ` Maxime Ripard
2016-09-05 12:42 ` Chen-Yu Tsai
5 siblings, 1 reply; 20+ messages in thread
From: Maxime Ripard @ 2016-08-31 8:18 UTC (permalink / raw)
To: Linus Walleij, Chen-Yu Tsai, Maxime Ripard, Jingoo Han,
Lee Jones, Tomi Valkeinen, Daniel Vetter, David Airlie,
Thierry Reding
Cc: linux-arm-kernel, linux-kernel, linux-gpio, dri-devel,
linux-fbdev, Mylene Josserand, Thomas Petazzoni,
Alexander Kaplan
From: Mylène Josserand <mylene.josserand@free-electrons.com>
The GR8-EVB is a small board with an NextThing GR8, an Hynix MLC NAND,
an AXP209 PMIC, USB host and OTG, an SPDIF output and a connectors for CSI,
I2S and LCD.
Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/gr8-evb.dts | 378 ++++++++++++++++++++++++++++++++++++++++++
2 files changed, 380 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/gr8-evb.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7dd4a07c4784..8226b0a2e178 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -734,7 +734,8 @@ dtb-$(CONFIG_MACH_SUN5I) += \
sun5i-a13-olinuxino-micro.dtb \
sun5i-a13-q8-tablet.dtb \
sun5i-a13-utoo-p66.dtb \
- sun5i-r8-chip.dtb
+ sun5i-r8-chip.dtb \
+ gr8-evb.dtb
dtb-$(CONFIG_MACH_SUN6I) += \
sun6i-a31-app4-evb1.dtb \
sun6i-a31-colombus.dtb \
diff --git a/arch/arm/boot/dts/gr8-evb.dts b/arch/arm/boot/dts/gr8-evb.dts
new file mode 100644
index 000000000000..e334d18d7bf0
--- /dev/null
+++ b/arch/arm/boot/dts/gr8-evb.dts
@@ -0,0 +1,378 @@
+/*
+ * Copyright 2016 Free Electrons
+ * Copyright 2016 NextThing Co
+ *
+ * Mylène Josserand <mylene.josserand@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "gr8.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ model = "NextThing GR8-EVB";
+ compatible = "nextthing,gr8-evb", "nextthing,gr8";
+
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ serial0 = &uart1;
+ serial1 = &uart2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm 0 10000 0>;
+ enable-gpios = <&axp_gpio 1 GPIO_ACTIVE_HIGH>;
+
+ brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
+ default-brightness-level = <8>;
+ };
+
+ panel {
+ compatible = "allwinner,sun4i-a10-sub-evb-5-lcd";
+ enable-gpios = <&axp_gpio 0 GPIO_ACTIVE_HIGH>;
+ backlight = <&backlight>;
+ power-supply = <®_vcc3v0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ panel_input: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon0_out_panel>;
+ };
+ };
+ };
+};
+
+&be0 {
+ status = "okay";
+};
+
+&codec {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ reg = <0x34>;
+
+ /*
+ * The interrupt is routed through the "External Fast
+ * Interrupt Request" pin (ball G13 of the module)
+ * directly to the main interrupt controller, without
+ * any other controller interfering.
+ */
+ interrupts = <0>;
+ };
+};
+
+#include "axp209.dtsi"
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+
+ pcf8563: rtc@51 {
+ compatible = "phg,pcf8563";
+ reg = <0x51>;
+ };
+
+ wm8978: codec@1a {
+ #sound-dai-cells = <0>;
+ compatible = "wlf,wm8978";
+ reg = <0x1a>;
+ };
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ status = "okay";
+};
+
+&i2s0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s0_pins_a>;
+ status = "okay";
+};
+
+&ir0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir0_rx_pins_a>;
+ status = "okay";
+};
+
+&lradc {
+ vref-supply = <®_ldo2>;
+ status = "okay";
+
+ button@190 {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ channel = <0>;
+ voltage = <190000>;
+ };
+
+ button@390 {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ channel = <0>;
+ voltage = <390000>;
+ };
+
+ button@600 {
+ label = "Menu";
+ linux,code = <KEY_MENU>;
+ channel = <0>;
+ voltage = <600000>;
+ };
+
+ button@800 {
+ label = "Search";
+ linux,code = <KEY_SEARCH>;
+ channel = <0>;
+ voltage = <800000>;
+ };
+
+ button@980 {
+ label = "Home";
+ linux,code = <KEY_HOMEPAGE>;
+ channel = <0>;
+ voltage = <980000>;
+ };
+
+ button@1180 {
+ label = "Esc";
+ linux,code = <KEY_ESC>;
+ channel = <0>;
+ voltage = <1180000>;
+ };
+
+ button@1400 {
+ label = "Enter";
+ linux,code = <KEY_ENTER>;
+ channel = <0>;
+ voltage = <1400000>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_gr8_evb>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
+ cd-inverted;
+ status = "okay";
+};
+
+&nfc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&nand_pins_a &nand_cs0_pins_a &nand_rb0_pins_a>;
+
+ /* MLC Support sucks for now */
+ status = "disabled";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&otg_sram {
+ status = "okay";
+};
+
+&pio {
+ mmc0_cd_pin_gr8_evb: mmc0-cd-pin@0 {
+ allwinner,pins = "PG0";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ usb0_id_pin_gr8_evb: usb0-id-pin@0 {
+ allwinner,pins = "PG2";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ usb0_vbus_det_pin_gr8_evb: usb0-vbus-det-pin@0 {
+ allwinner,pins = "PG1";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ usb1_vbus_pin_gr8_evb: usb1-vbus-pin@0 {
+ allwinner,pins = "PG13";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_pins_a>;
+ status = "okay";
+};
+
+®_dcdc2 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpu";
+ regulator-always-on;
+};
+
+®_dcdc3 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-name = "vdd-sys";
+ regulator-always-on;
+};
+
+®_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+®_ldo2 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "avcc";
+ regulator-always-on;
+};
+
+®_usb1_vbus {
+ pinctrl-0 = <&usb1_vbus_pin_gr8_evb>;
+ gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&rtp {
+ allwinner,ts-attached;
+};
+
+&spdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spdif_tx_pins_a>;
+ status = "okay";
+};
+
+&tcon0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_rgb666_pins>;
+ status = "okay";
+};
+
+&tcon0_out {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon0_out_panel: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&panel_input>;
+ };
+};
+
+&tve0 {
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins_a>, <&uart1_cts_rts_pins_a>;
+ status = "okay";
+};
+
+&usb_otg {
+ /*
+ * The GR8-EVB has a somewhat interesting design. There's a
+ * pin supposed to control VBUS, an ID pin, a VBUS detect pin,
+ * so everything should work just fine.
+ *
+ * Except that the pin supposed to control VBUS is not
+ * connected to any controllable output, neither to the SoC
+ * through a GPIO or to the PMIC, and it is pulled down,
+ * meaning that we will never be able to enable VBUS on this
+ * board.
+ */
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usb_power_supply {
+ status = "okay";
+};
+
+&usbphy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_id_pin_gr8_evb>, <&usb0_vbus_det_pin_gr8_evb>;
+ usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
+ usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
+ usb0_vbus_power-supply = <&usb_power_supply>;
+ usb1_vbus-supply = <®_usb1_vbus>;
+ status = "okay";
+};
--
2.9.2
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH 4/6] ARM: sunxi: Support the Nextthing GR8
2016-08-31 8:18 ` [PATCH 4/6] ARM: sunxi: Support the Nextthing GR8 Maxime Ripard
@ 2016-08-31 8:25 ` Chen-Yu Tsai
2016-09-02 6:28 ` Maxime Ripard
0 siblings, 1 reply; 20+ messages in thread
From: Chen-Yu Tsai @ 2016-08-31 8:25 UTC (permalink / raw)
To: Maxime Ripard
Cc: Linus Walleij, Chen-Yu Tsai, Jingoo Han, Lee Jones,
Tomi Valkeinen, Daniel Vetter, David Airlie, Thierry Reding,
linux-arm-kernel, linux-kernel, linux-gpio, dri-devel,
linux-fbdev, Mylene Josserand, Thomas Petazzoni,
Alexander Kaplan
On Wed, Aug 31, 2016 at 4:18 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> The GR8 is an SoC made by Nextthing Co, loosely based on the sun5i family.
>
> It has a number of new controllers compared to the A10s and A13 (SPDIF, I2S),
> but some controllers missing too (Ethernet, less I2C, less UARTs).
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
> Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
> MAINTAINERS | 1 +
> arch/arm/mach-sunxi/sunxi.c | 1 +
Please update Documentation/arm/sunxi/README as well. I don't suppose
there's a datasheet available?
ChenYu
> 3 files changed, 3 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
> index 7e79fcc36b0d..3975d0a0e4c2 100644
> --- a/Documentation/devicetree/bindings/arm/sunxi.txt
> +++ b/Documentation/devicetree/bindings/arm/sunxi.txt
> @@ -14,3 +14,4 @@ using one of the following compatible strings:
> allwinner,sun8i-a83t
> allwinner,sun8i-h3
> allwinner,sun9i-a80
> + nextthing,gr8
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 20bb1d00098c..c6a9e6fda1d0 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -982,6 +982,7 @@ M: Chen-Yu Tsai <wens@csie.org>
> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
> S: Maintained
> N: sun[x456789]i
> +F: arch/arm/boot/dts/gr8*
>
> ARM/Allwinner SoC Clock Support
> M: Emilio López <emilio@elopez.com.ar>
> diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
> index 95dca8c2c9ed..2e2bde271205 100644
> --- a/arch/arm/mach-sunxi/sunxi.c
> +++ b/arch/arm/mach-sunxi/sunxi.c
> @@ -22,6 +22,7 @@ static const char * const sunxi_board_dt_compat[] = {
> "allwinner,sun5i-a10s",
> "allwinner,sun5i-a13",
> "allwinner,sun5i-r8",
> + "nextthing,gr8",
> NULL,
> };
>
> --
> 2.9.2
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 1/6] backlight: pwm_bl: Handle gpio that can sleep
2016-08-31 8:18 ` [PATCH 1/6] backlight: pwm_bl: Handle gpio that can sleep Maxime Ripard
@ 2016-08-31 12:25 ` Lee Jones
0 siblings, 0 replies; 20+ messages in thread
From: Lee Jones @ 2016-08-31 12:25 UTC (permalink / raw)
To: Maxime Ripard
Cc: Linus Walleij, Chen-Yu Tsai, Jingoo Han, Tomi Valkeinen,
Daniel Vetter, David Airlie, Thierry Reding, linux-arm-kernel,
linux-kernel, linux-gpio, dri-devel, linux-fbdev,
Mylene Josserand, Thomas Petazzoni, Alexander Kaplan
On Wed, 31 Aug 2016, Maxime Ripard wrote:
> Some backlight GPIOs might be connected to some i2c based expanders whose
> access might sleep.
>
> Since it's not in any critical path, use the cansleep variant of the GPIO
> API.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
> drivers/video/backlight/pwm_bl.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Applied, thanks.
> diff --git a/drivers/video/backlight/pwm_bl.c b/drivers/video/backlight/pwm_bl.c
> index b2b366bb0f97..12614006211e 100644
> --- a/drivers/video/backlight/pwm_bl.c
> +++ b/drivers/video/backlight/pwm_bl.c
> @@ -55,7 +55,7 @@ static void pwm_backlight_power_on(struct pwm_bl_data *pb, int brightness)
> dev_err(pb->dev, "failed to enable power supply\n");
>
> if (pb->enable_gpio)
> - gpiod_set_value(pb->enable_gpio, 1);
> + gpiod_set_value_cansleep(pb->enable_gpio, 1);
>
> pwm_enable(pb->pwm);
> pb->enabled = true;
> @@ -70,7 +70,7 @@ static void pwm_backlight_power_off(struct pwm_bl_data *pb)
> pwm_disable(pb->pwm);
>
> if (pb->enable_gpio)
> - gpiod_set_value(pb->enable_gpio, 0);
> + gpiod_set_value_cansleep(pb->enable_gpio, 0);
>
> regulator_disable(pb->power_supply);
> pb->enabled = false;
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 4/6] ARM: sunxi: Support the Nextthing GR8
2016-08-31 8:25 ` Chen-Yu Tsai
@ 2016-09-02 6:28 ` Maxime Ripard
0 siblings, 0 replies; 20+ messages in thread
From: Maxime Ripard @ 2016-09-02 6:28 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: Linus Walleij, Jingoo Han, Lee Jones, Tomi Valkeinen,
Daniel Vetter, David Airlie, Thierry Reding, linux-arm-kernel,
linux-kernel, linux-gpio, dri-devel, linux-fbdev,
Mylene Josserand, Thomas Petazzoni, Alexander Kaplan
[-- Attachment #1: Type: text/plain, Size: 951 bytes --]
Hi Chen-Yu,
On Wed, Aug 31, 2016 at 04:25:27PM +0800, Chen-Yu Tsai wrote:
> On Wed, Aug 31, 2016 at 4:18 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > The GR8 is an SoC made by Nextthing Co, loosely based on the sun5i family.
> >
> > It has a number of new controllers compared to the A10s and A13 (SPDIF, I2S),
> > but some controllers missing too (Ethernet, less I2C, less UARTs).
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> > ---
> > Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
> > MAINTAINERS | 1 +
> > arch/arm/mach-sunxi/sunxi.c | 1 +
>
> Please update Documentation/arm/sunxi/README as well.
I will.
> I don't suppose there's a datasheet available?
Not at the moment, unfortunately.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 6/6] ARM: dts: gr8: Add support for the GR8 evaluation board
2016-08-31 8:18 ` [PATCH 6/6] ARM: dts: gr8: Add support for the GR8 evaluation board Maxime Ripard
@ 2016-09-05 12:42 ` Chen-Yu Tsai
0 siblings, 0 replies; 20+ messages in thread
From: Chen-Yu Tsai @ 2016-09-05 12:42 UTC (permalink / raw)
To: Maxime Ripard
Cc: Linus Walleij, Chen-Yu Tsai, Jingoo Han, Lee Jones,
Tomi Valkeinen, Daniel Vetter, David Airlie, Thierry Reding,
linux-arm-kernel, linux-kernel, linux-gpio, dri-devel,
linux-fbdev, Mylene Josserand, Thomas Petazzoni,
Alexander Kaplan
Hi,
On Wed, Aug 31, 2016 at 4:18 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> From: Mylène Josserand <mylene.josserand@free-electrons.com>
>
> The GR8-EVB is a small board with an NextThing GR8, an Hynix MLC NAND,
> an AXP209 PMIC, USB host and OTG, an SPDIF output and a connectors for CSI,
> I2S and LCD.
>
> Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
> arch/arm/boot/dts/Makefile | 3 +-
> arch/arm/boot/dts/gr8-evb.dts | 378 ++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 380 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/boot/dts/gr8-evb.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 7dd4a07c4784..8226b0a2e178 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -734,7 +734,8 @@ dtb-$(CONFIG_MACH_SUN5I) += \
> sun5i-a13-olinuxino-micro.dtb \
> sun5i-a13-q8-tablet.dtb \
> sun5i-a13-utoo-p66.dtb \
> - sun5i-r8-chip.dtb
> + sun5i-r8-chip.dtb \
> + gr8-evb.dtb
> dtb-$(CONFIG_MACH_SUN6I) += \
> sun6i-a31-app4-evb1.dtb \
> sun6i-a31-colombus.dtb \
> diff --git a/arch/arm/boot/dts/gr8-evb.dts b/arch/arm/boot/dts/gr8-evb.dts
> new file mode 100644
> index 000000000000..e334d18d7bf0
> --- /dev/null
> +++ b/arch/arm/boot/dts/gr8-evb.dts
> @@ -0,0 +1,378 @@
> +/*
> + * Copyright 2016 Free Electrons
> + * Copyright 2016 NextThing Co
> + *
> + * Mylène Josserand <mylene.josserand@free-electrons.com>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/dts-v1/;
> +#include "gr8.dtsi"
> +#include "sunxi-common-regulators.dtsi"
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> + model = "NextThing GR8-EVB";
> + compatible = "nextthing,gr8-evb", "nextthing,gr8";
> +
> + aliases {
> + i2c0 = &i2c0;
> + i2c1 = &i2c1;
> + i2c2 = &i2c2;
> + serial0 = &uart1;
> + serial1 = &uart2;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + backlight: backlight {
> + compatible = "pwm-backlight";
> + pwms = <&pwm 0 10000 0>;
> + enable-gpios = <&axp_gpio 1 GPIO_ACTIVE_HIGH>;
> +
> + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
> + default-brightness-level = <8>;
> + };
> +
> + panel {
> + compatible = "allwinner,sun4i-a10-sub-evb-5-lcd";
> + enable-gpios = <&axp_gpio 0 GPIO_ACTIVE_HIGH>;
> + backlight = <&backlight>;
> + power-supply = <®_vcc3v0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + panel_input: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&tcon0_out_panel>;
> + };
> + };
> + };
> +};
> +
> +&be0 {
> + status = "okay";
> +};
> +
> +&codec {
> + status = "okay";
> +};
> +
> +&ehci0 {
> + status = "okay";
> +};
> +
> +&i2c0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c0_pins_a>;
> + status = "okay";
> +
> + axp209: pmic@34 {
> + reg = <0x34>;
> +
> + /*
> + * The interrupt is routed through the "External Fast
> + * Interrupt Request" pin (ball G13 of the module)
> + * directly to the main interrupt controller, without
> + * any other controller interfering.
> + */
> + interrupts = <0>;
> + };
> +};
> +
> +#include "axp209.dtsi"
> +
> +&i2c1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c1_pins_a>;
> + status = "okay";
> +
> + pcf8563: rtc@51 {
> + compatible = "phg,pcf8563";
> + reg = <0x51>;
> + };
> +
> + wm8978: codec@1a {
> + #sound-dai-cells = <0>;
> + compatible = "wlf,wm8978";
> + reg = <0x1a>;
> + };
> +};
> +
> +&i2c2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c2_pins_a>;
> + status = "okay";
> +};
> +
> +&i2s0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2s0_pins_a>;
> + status = "okay";
> +};
> +
> +&ir0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&ir0_rx_pins_a>;
> + status = "okay";
> +};
> +
> +&lradc {
> + vref-supply = <®_ldo2>;
> + status = "okay";
> +
> + button@190 {
> + label = "Volume Up";
> + linux,code = <KEY_VOLUMEUP>;
> + channel = <0>;
> + voltage = <190000>;
> + };
> +
> + button@390 {
> + label = "Volume Down";
> + linux,code = <KEY_VOLUMEDOWN>;
> + channel = <0>;
> + voltage = <390000>;
> + };
> +
> + button@600 {
> + label = "Menu";
> + linux,code = <KEY_MENU>;
> + channel = <0>;
> + voltage = <600000>;
> + };
> +
> + button@800 {
> + label = "Search";
> + linux,code = <KEY_SEARCH>;
> + channel = <0>;
> + voltage = <800000>;
> + };
> +
> + button@980 {
> + label = "Home";
> + linux,code = <KEY_HOMEPAGE>;
> + channel = <0>;
> + voltage = <980000>;
> + };
> +
> + button@1180 {
> + label = "Esc";
> + linux,code = <KEY_ESC>;
> + channel = <0>;
> + voltage = <1180000>;
> + };
> +
> + button@1400 {
> + label = "Enter";
> + linux,code = <KEY_ENTER>;
> + channel = <0>;
> + voltage = <1400000>;
> + };
> +};
> +
> +&mmc0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_gr8_evb>;
> + vmmc-supply = <®_vcc3v3>;
> + bus-width = <4>;
> + cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
> + cd-inverted;
> + status = "okay";
> +};
> +
> +&nfc {
> + pinctrl-names = "default";
> + pinctrl-0 = <&nand_pins_a &nand_cs0_pins_a &nand_rb0_pins_a>;
> +
> + /* MLC Support sucks for now */
> + status = "disabled";
> +};
> +
> +&ohci0 {
> + status = "okay";
> +};
> +
> +&otg_sram {
> + status = "okay";
> +};
> +
> +&pio {
> + mmc0_cd_pin_gr8_evb: mmc0-cd-pin@0 {
> + allwinner,pins = "PG0";
> + allwinner,function = "gpio_in";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> + usb0_id_pin_gr8_evb: usb0-id-pin@0 {
> + allwinner,pins = "PG2";
> + allwinner,function = "gpio_in";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> + usb0_vbus_det_pin_gr8_evb: usb0-vbus-det-pin@0 {
> + allwinner,pins = "PG1";
> + allwinner,function = "gpio_in";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> + usb1_vbus_pin_gr8_evb: usb1-vbus-pin@0 {
> + allwinner,pins = "PG13";
> + allwinner,function = "gpio_out";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +};
> +
> +&pwm {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm0_pins_a>;
> + status = "okay";
> +};
> +
> +®_dcdc2 {
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1400000>;
> + regulator-name = "vdd-cpu";
> + regulator-always-on;
> +};
> +
> +®_dcdc3 {
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1300000>;
> + regulator-name = "vdd-sys";
> + regulator-always-on;
> +};
> +
> +®_ldo1 {
> + regulator-name = "vdd-rtc";
> +};
> +
> +®_ldo2 {
> + regulator-min-microvolt = <2700000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "avcc";
> + regulator-always-on;
> +};
> +
> +®_usb1_vbus {
> + pinctrl-0 = <&usb1_vbus_pin_gr8_evb>;
> + gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>;
> + status = "okay";
> +};
> +
> +&rtp {
> + allwinner,ts-attached;
> +};
> +
> +&spdif {
> + pinctrl-names = "default";
> + pinctrl-0 = <&spdif_tx_pins_a>;
> + status = "okay";
> +};
> +
> +&tcon0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&lcd_rgb666_pins>;
> + status = "okay";
> +};
> +
> +&tcon0_out {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + tcon0_out_panel: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&panel_input>;
> + };
> +};
> +
> +&tve0 {
> + status = "okay";
> +};
> +
> +&uart1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart1_pins_a>, <&uart1_cts_rts_pins_a>;
> + status = "okay";
> +};
> +
> +&usb_otg {
> + /*
> + * The GR8-EVB has a somewhat interesting design. There's a
> + * pin supposed to control VBUS, an ID pin, a VBUS detect pin,
> + * so everything should work just fine.
> + *
> + * Except that the pin supposed to control VBUS is not
> + * connected to any controllable output, neither to the SoC
> + * through a GPIO or to the PMIC, and it is pulled down,
> + * meaning that we will never be able to enable VBUS on this
> + * board.
> + */
IIRC, Hans made OTG work with boards that don't have VBUS control.
All you need is a powered hub. And since there's no chance of VBUS
going back through the connection to hurt the host on the other end
when in peripheral mode, I think it's ok to put it in OTG mode here.
The rest looks fine.
ChenYu
> + dr_mode = "peripheral";
> + status = "okay";
> +};
> +
> +&usb_power_supply {
> + status = "okay";
> +};
> +
> +&usbphy {
> + pinctrl-names = "default";
> + pinctrl-0 = <&usb0_id_pin_gr8_evb>, <&usb0_vbus_det_pin_gr8_evb>;
> + usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
> + usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
> + usb0_vbus_power-supply = <&usb_power_supply>;
> + usb1_vbus-supply = <®_usb1_vbus>;
> + status = "okay";
> +};
> --
> 2.9.2
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 5/6] ARM: dts: Add NextThing GR8 dtsi
2016-08-31 8:18 ` [PATCH 5/6] ARM: dts: Add NextThing GR8 dtsi Maxime Ripard
@ 2016-09-05 12:47 ` Chen-Yu Tsai
2016-09-07 14:51 ` Javier Martinez Canillas
2016-09-07 17:51 ` Rask Ingemann Lambertsen
2 siblings, 0 replies; 20+ messages in thread
From: Chen-Yu Tsai @ 2016-09-05 12:47 UTC (permalink / raw)
To: Maxime Ripard
Cc: Linus Walleij, Chen-Yu Tsai, Jingoo Han, Lee Jones,
Tomi Valkeinen, Daniel Vetter, David Airlie, Thierry Reding,
linux-arm-kernel, linux-kernel, linux-gpio, dri-devel,
linux-fbdev, Mylene Josserand, Thomas Petazzoni,
Alexander Kaplan
On Wed, Aug 31, 2016 at 4:18 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> From: Mylène Josserand <mylene.josserand@free-electrons.com>
>
> The GR8 is an SoC made by Nextthing loosely based on the sun5i family.
>
> Since it's not clear yet what we can factor out and merge with the A10s and
> A13 support, let's keep it out of the sun5i.dtsi include tree. We will
> figure out what can be shared when things settle down.
>
> Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
> arch/arm/boot/dts/gr8.dtsi | 1080 ++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 1080 insertions(+)
> create mode 100644 arch/arm/boot/dts/gr8.dtsi
>
> diff --git a/arch/arm/boot/dts/gr8.dtsi b/arch/arm/boot/dts/gr8.dtsi
> new file mode 100644
> index 000000000000..d21cfa3f3c14
> --- /dev/null
> +++ b/arch/arm/boot/dts/gr8.dtsi
> @@ -0,0 +1,1080 @@
> +/*
> + * Copyright 2016 Mylène Josserand
> + *
> + * Mylène Josserand <mylene.josserand@free-electrons.com>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +#include "skeleton.dtsi"
> +
> +#include <dt-bindings/clock/sun4i-a10-pll2.h>
> +#include <dt-bindings/dma/sun4i-a10.h>
> +#include <dt-bindings/pinctrl/sun4i-a10.h>
> +
> +/ {
> + interrupt-parent = <&intc>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a8";
> + reg = <0x0>;
> + clocks = <&cpu>;
> + };
> + };
> +
> + clocks {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + /*
> + * This is a dummy clock, to be used as placeholder on
> + * other mux clocks when a specific parent clock is not
> + * yet implemented. It should be dropped when the driver
> + * is complete.
> + */
> + dummy: dummy {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <0>;
> + };
> +
> + osc24M: clk@01c20050 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-osc-clk";
> + reg = <0x01c20050 0x4>;
> + clock-frequency = <24000000>;
> + clock-output-names = "osc24M";
> + };
> +
> + osc3M: osc3M_clk {
> + compatible = "fixed-factor-clock";
> + #clock-cells = <0>;
> + clock-div = <8>;
> + clock-mult = <1>;
> + clocks = <&osc24M>;
> + clock-output-names = "osc3M";
> + };
> +
> + osc32k: clk@0 {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <32768>;
> + clock-output-names = "osc32k";
> + };
> +
> + pll1: clk@01c20000 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-pll1-clk";
> + reg = <0x01c20000 0x4>;
> + clocks = <&osc24M>;
> + clock-output-names = "pll1";
> + };
> +
> + pll2: clk@01c20008 {
> + #clock-cells = <1>;
> + compatible = "allwinner,sun5i-a13-pll2-clk";
> + reg = <0x01c20008 0x8>;
> + clocks = <&osc24M>;
> + clock-output-names = "pll2-1x", "pll2-2x",
> + "pll2-4x", "pll2-8x";
> + };
> +
> + pll3: clk@01c20010 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-pll3-clk";
> + reg = <0x01c20010 0x4>;
> + clocks = <&osc3M>;
> + clock-output-names = "pll3";
> + };
> +
> + pll3x2: pll3x2_clk {
> + compatible = "fixed-factor-clock";
> + #clock-cells = <0>;
> + clock-div = <1>;
> + clock-mult = <2>;
> + clocks = <&pll3>;
> + clock-output-names = "pll3-2x";
> + };
> +
> + pll4: clk@01c20018 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-pll1-clk";
> + reg = <0x01c20018 0x4>;
> + clocks = <&osc24M>;
> + clock-output-names = "pll4";
> + };
> +
> + pll5: clk@01c20020 {
> + #clock-cells = <1>;
> + compatible = "allwinner,sun4i-a10-pll5-clk";
> + reg = <0x01c20020 0x4>;
> + clocks = <&osc24M>;
> + clock-output-names = "pll5_ddr", "pll5_other";
> + };
> +
> + pll6: clk@01c20028 {
> + #clock-cells = <1>;
> + compatible = "allwinner,sun4i-a10-pll6-clk";
> + reg = <0x01c20028 0x4>;
> + clocks = <&osc24M>;
> + clock-output-names = "pll6_sata", "pll6_other", "pll6";
> + };
> +
> + pll7: clk@01c20030 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-pll3-clk";
> + reg = <0x01c20030 0x4>;
> + clocks = <&osc3M>;
> + clock-output-names = "pll7";
> + };
> +
> + pll7x2: pll7x2_clk {
> + compatible = "fixed-factor-clock";
> + #clock-cells = <0>;
> + clock-div = <1>;
> + clock-mult = <2>;
> + clocks = <&pll7>;
> + clock-output-names = "pll7-2x";
> + };
> +
> + /* dummy is 200M */
> + cpu: cpu@01c20054 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-cpu-clk";
> + reg = <0x01c20054 0x4>;
> + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
> + clock-output-names = "cpu";
> + };
> +
> + axi: axi@01c20054 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-axi-clk";
> + reg = <0x01c20054 0x4>;
> + clocks = <&cpu>;
> + clock-output-names = "axi";
> + };
> +
> + ahb: ahb@01c20054 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun5i-a13-ahb-clk";
> + reg = <0x01c20054 0x4>;
> + clocks = <&axi>, <&cpu>, <&pll6 1>;
> + clock-output-names = "ahb";
> + /*
> + * Use PLL6 as parent, instead of CPU/AXI
> + * which has rate changes due to cpufreq
> + */
> + assigned-clocks = <&ahb>;
> + assigned-clock-parents = <&pll6 1>;
> + };
> +
> + apb0: apb0@01c20054 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-apb0-clk";
> + reg = <0x01c20054 0x4>;
> + clocks = <&ahb>;
> + clock-output-names = "apb0";
> + };
> +
> + apb1: clk@01c20058 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-apb1-clk";
> + reg = <0x01c20058 0x4>;
> + clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
> + clock-output-names = "apb1";
> + };
> +
> + axi_gates: clk@01c2005c {
> + #clock-cells = <1>;
> + compatible = "allwinner,sun4i-a10-axi-gates-clk";
> + reg = <0x01c2005c 0x4>;
> + clocks = <&axi>;
> + clock-indices = <0>;
> + clock-output-names = "axi_dram";
> + };
> +
> + ahb_gates: clk@01c20060 {
> + #clock-cells = <1>;
> + compatible = "allwinner,sun5i-a13-ahb-gates-clk";
> + reg = <0x01c20060 0x8>;
> + clocks = <&ahb>;
> + clock-indices = <0>, <1>,
> + <2>, <5>, <6>,
> + <7>, <8>, <9>,
> + <10>, <13>,
> + <14>, <20>,
> + <21>, <22>,
> + <28>, <32>, <34>,
> + <36>, <40>, <44>,
> + <46>, <51>,
> + <52>;
> + clock-output-names = "ahb_usbotg", "ahb_ehci",
> + "ahb_ohci", "ahb_ss", "ahb_dma",
> + "ahb_bist", "ahb_mmc0", "ahb_mmc1",
> + "ahb_mmc2", "ahb_nand",
> + "ahb_sdram", "ahb_spi0",
> + "ahb_spi1", "ahb_spi2",
> + "ahb_stimer", "ahb_ve", "ahb_tve",
> + "ahb_lcd", "ahb_csi", "ahb_de_be",
> + "ahb_de_fe", "ahb_iep",
> + "ahb_mali400";
> + };
> +
> + apb0_gates: clk@01c20068 {
> + #clock-cells = <1>;
> + compatible = "allwinner,sun5i-a13-apb0-gates-clk";
> + reg = <0x01c20068 0x4>;
> + clocks = <&apb0>;
> + clock-indices = <0>, <3>,
> + <5>, <6>;
> + clock-output-names = "apb0_codec", "apb0_i2s0",
> + "apb0_pio", "apb0_ir";
> + };
I assume the ahb and apb0 gates would be different? In the cover letter
you mentioned that ethernet is gone, but i2s was added?
Otherwise,
Acked-by: Chen-Yu Tsai <wens@csie.org>
> +
> + apb1_gates: clk@01c2006c {
> + #clock-cells = <1>;
> + compatible = "allwinner,sun5i-a13-apb1-gates-clk";
> + reg = <0x01c2006c 0x4>;
> + clocks = <&apb1>;
> + clock-indices = <0>, <1>,
> + <2>, <17>,
> + <18>;
> + clock-output-names = "apb1_i2c0", "apb1_i2c1",
> + "apb1_i2c2", "apb1_uart1",
> + "apb1_uart2";
> + };
> +
> + nand_clk: clk@01c20080 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-mod0-clk";
> + reg = <0x01c20080 0x4>;
> + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
> + clock-output-names = "nand";
> + };
> +
> + ms_clk: clk@01c20084 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-mod0-clk";
> + reg = <0x01c20084 0x4>;
> + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
> + clock-output-names = "ms";
> + };
> +
> + mmc0_clk: clk@01c20088 {
> + #clock-cells = <1>;
> + compatible = "allwinner,sun4i-a10-mmc-clk";
> + reg = <0x01c20088 0x4>;
> + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
> + clock-output-names = "mmc0",
> + "mmc0_output",
> + "mmc0_sample";
> + };
> +
> + mmc1_clk: clk@01c2008c {
> + #clock-cells = <1>;
> + compatible = "allwinner,sun4i-a10-mmc-clk";
> + reg = <0x01c2008c 0x4>;
> + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
> + clock-output-names = "mmc1",
> + "mmc1_output",
> + "mmc1_sample";
> + };
> +
> + mmc2_clk: clk@01c20090 {
> + #clock-cells = <1>;
> + compatible = "allwinner,sun4i-a10-mmc-clk";
> + reg = <0x01c20090 0x4>;
> + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
> + clock-output-names = "mmc2",
> + "mmc2_output",
> + "mmc2_sample";
> + };
> +
> + ts_clk: clk@01c20098 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-mod0-clk";
> + reg = <0x01c20098 0x4>;
> + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
> + clock-output-names = "ts";
> + };
> +
> + ss_clk: clk@01c2009c {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-mod0-clk";
> + reg = <0x01c2009c 0x4>;
> + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
> + clock-output-names = "ss";
> + };
> +
> + spi0_clk: clk@01c200a0 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-mod0-clk";
> + reg = <0x01c200a0 0x4>;
> + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
> + clock-output-names = "spi0";
> + };
> +
> + spi1_clk: clk@01c200a4 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-mod0-clk";
> + reg = <0x01c200a4 0x4>;
> + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
> + clock-output-names = "spi1";
> + };
> +
> + spi2_clk: clk@01c200a8 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-mod0-clk";
> + reg = <0x01c200a8 0x4>;
> + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
> + clock-output-names = "spi2";
> + };
> +
> + ir0_clk: clk@01c200b0 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-mod0-clk";
> + reg = <0x01c200b0 0x4>;
> + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
> + clock-output-names = "ir0";
> + };
> +
> + i2s0_clk: clk@01c200b8 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-mod1-clk";
> + reg = <0x01c200b8 0x4>;
> + clocks = <&pll2 SUN4I_A10_PLL2_8X>,
> + <&pll2 SUN4I_A10_PLL2_4X>,
> + <&pll2 SUN4I_A10_PLL2_2X>,
> + <&pll2 SUN4I_A10_PLL2_1X>;
> + clock-output-names = "i2s0";
> + };
> +
> + spdif_clk: clk@01c200c0 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-mod1-clk";
> + reg = <0x01c200c0 0x4>;
> + clocks = <&pll2 SUN4I_A10_PLL2_8X>,
> + <&pll2 SUN4I_A10_PLL2_4X>,
> + <&pll2 SUN4I_A10_PLL2_2X>,
> + <&pll2 SUN4I_A10_PLL2_1X>;
> + clock-output-names = "spdif";
> + };
> +
> + usb_clk: clk@01c200cc {
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + compatible = "allwinner,sun5i-a13-usb-clk";
> + reg = <0x01c200cc 0x4>;
> + clocks = <&pll6 1>;
> + clock-output-names = "usb_ohci0", "usb_phy";
> + };
> +
> + dram_gates: clk@01c20100 {
> + #clock-cells = <1>;
> + compatible = "nextthing,gr8-dram-gates-clk",
> + "allwinner,sun4i-a10-gates-clk";
> + reg = <0x01c20100 0x4>;
> + clocks = <&pll5 0>;
> + clock-indices = <0>,
> + <1>,
> + <25>,
> + <26>,
> + <29>,
> + <31>;
> + clock-output-names = "dram_ve",
> + "dram_csi",
> + "dram_de_fe",
> + "dram_de_be",
> + "dram_ace",
> + "dram_iep";
> + };
> +
> + de_be_clk: clk@01c20104 {
> + #clock-cells = <0>;
> + #reset-cells = <0>;
> + compatible = "allwinner,sun4i-a10-display-clk";
> + reg = <0x01c20104 0x4>;
> + clocks = <&pll3>, <&pll7>, <&pll5 1>;
> + clock-output-names = "de-be";
> + };
> +
> + de_fe_clk: clk@01c2010c {
> + #clock-cells = <0>;
> + #reset-cells = <0>;
> + compatible = "allwinner,sun4i-a10-display-clk";
> + reg = <0x01c2010c 0x4>;
> + clocks = <&pll3>, <&pll7>, <&pll5 1>;
> + clock-output-names = "de-fe";
> + };
> +
> + tcon_ch0_clk: clk@01c20118 {
> + #clock-cells = <0>;
> + #reset-cells = <1>;
> + compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
> + reg = <0x01c20118 0x4>;
> + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
> + clock-output-names = "tcon-ch0-sclk";
> + };
> +
> + tcon_ch1_clk: clk@01c2012c {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
> + reg = <0x01c2012c 0x4>;
> + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
> + clock-output-names = "tcon-ch1-sclk";
> + };
> +
> + codec_clk: clk@01c20140 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-codec-clk";
> + reg = <0x01c20140 0x4>;
> + clocks = <&pll2 SUN4I_A10_PLL2_1X>;
> + clock-output-names = "codec";
> + };
> +
> + mbus_clk: clk@01c2015c {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun5i-a13-mbus-clk";
> + reg = <0x01c2015c 0x4>;
> + clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
> + clock-output-names = "mbus";
> + };
> + };
> +
> + display-engine {
> + compatible = "allwinner,sun5i-a13-display-engine";
> + allwinner,pipelines = <&fe0>;
> + };
> +
> + soc@01c00000 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + sram-controller@01c00000 {
> + compatible = "allwinner,sun4i-a10-sram-controller";
> + reg = <0x01c00000 0x30>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + sram_a: sram@00000000 {
> + compatible = "mmio-sram";
> + reg = <0x00000000 0xc000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x00000000 0xc000>;
> + };
> +
> + sram_d: sram@00010000 {
> + compatible = "mmio-sram";
> + reg = <0x00010000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x00010000 0x1000>;
> +
> + otg_sram: sram-section@0000 {
> + compatible = "allwinner,sun4i-a10-sram-d";
> + reg = <0x0000 0x1000>;
> + status = "disabled";
> + };
> + };
> + };
> +
> + dma: dma-controller@01c02000 {
> + compatible = "allwinner,sun4i-a10-dma";
> + reg = <0x01c02000 0x1000>;
> + interrupts = <27>;
> + clocks = <&ahb_gates 6>;
> + #dma-cells = <2>;
> + };
> +
> + nfc: nand@01c03000 {
> + compatible = "allwinner,sun4i-a10-nand";
> + reg = <0x01c03000 0x1000>;
> + interrupts = <37>;
> + clocks = <&ahb_gates 13>, <&nand_clk>;
> + clock-names = "ahb", "mod";
> + dmas = <&dma SUN4I_DMA_DEDICATED 3>;
> + dma-names = "rxtx";
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + spi0: spi@01c05000 {
> + compatible = "allwinner,sun4i-a10-spi";
> + reg = <0x01c05000 0x1000>;
> + interrupts = <10>;
> + clocks = <&ahb_gates 20>, <&spi0_clk>;
> + clock-names = "ahb", "mod";
> + dmas = <&dma SUN4I_DMA_DEDICATED 27>,
> + <&dma SUN4I_DMA_DEDICATED 26>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + spi1: spi@01c06000 {
> + compatible = "allwinner,sun4i-a10-spi";
> + reg = <0x01c06000 0x1000>;
> + interrupts = <11>;
> + clocks = <&ahb_gates 21>, <&spi1_clk>;
> + clock-names = "ahb", "mod";
> + dmas = <&dma SUN4I_DMA_DEDICATED 9>,
> + <&dma SUN4I_DMA_DEDICATED 8>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + tve0: tv-encoder@01c0a000 {
> + compatible = "allwinner,sun4i-a10-tv-encoder";
> + reg = <0x01c0a000 0x1000>;
> + clocks = <&ahb_gates 34>;
> + resets = <&tcon_ch0_clk 0>;
> + status = "disabled";
> +
> + port {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + tve0_in_tcon0: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&tcon0_out_tve0>;
> + };
> + };
> + };
> +
> + tcon0: lcd-controller@01c0c000 {
> + compatible = "allwinner,sun5i-a13-tcon";
> + reg = <0x01c0c000 0x1000>;
> + interrupts = <44>;
> + resets = <&tcon_ch0_clk 1>;
> + reset-names = "lcd";
> + clocks = <&ahb_gates 36>,
> + <&tcon_ch0_clk>,
> + <&tcon_ch1_clk>;
> + clock-names = "ahb",
> + "tcon-ch0",
> + "tcon-ch1";
> + clock-output-names = "tcon-pixel-clock";
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + tcon0_in: port@0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0>;
> +
> + tcon0_in_be0: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&be0_out_tcon0>;
> + };
> + };
> +
> + tcon0_out: port@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> +
> + tcon0_out_tve0: endpoint@1 {
> + reg = <1>;
> + remote-endpoint = <&tve0_in_tcon0>;
> + };
> + };
> + };
> + };
> +
> + mmc0: mmc@01c0f000 {
> + compatible = "allwinner,sun5i-a13-mmc";
> + reg = <0x01c0f000 0x1000>;
> + clocks = <&ahb_gates 8>,
> + <&mmc0_clk 0>,
> + <&mmc0_clk 1>,
> + <&mmc0_clk 2>;
> + clock-names = "ahb",
> + "mmc",
> + "output",
> + "sample";
> + interrupts = <32>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + mmc1: mmc@01c10000 {
> + compatible = "allwinner,sun5i-a13-mmc";
> + reg = <0x01c10000 0x1000>;
> + clocks = <&ahb_gates 9>,
> + <&mmc1_clk 0>,
> + <&mmc1_clk 1>,
> + <&mmc1_clk 2>;
> + clock-names = "ahb",
> + "mmc",
> + "output",
> + "sample";
> + interrupts = <33>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + mmc2: mmc@01c11000 {
> + compatible = "allwinner,sun5i-a13-mmc";
> + reg = <0x01c11000 0x1000>;
> + clocks = <&ahb_gates 10>,
> + <&mmc2_clk 0>,
> + <&mmc2_clk 1>,
> + <&mmc2_clk 2>;
> + clock-names = "ahb",
> + "mmc",
> + "output",
> + "sample";
> + interrupts = <34>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + usb_otg: usb@01c13000 {
> + compatible = "allwinner,sun4i-a10-musb";
> + reg = <0x01c13000 0x0400>;
> + clocks = <&ahb_gates 0>;
> + interrupts = <38>;
> + interrupt-names = "mc";
> + phys = <&usbphy 0>;
> + phy-names = "usb";
> + extcon = <&usbphy 0>;
> + allwinner,sram = <&otg_sram 1>;
> + status = "disabled";
> +
> + dr_mode = "otg";
> + };
> +
> + usbphy: phy@01c13400 {
> + #phy-cells = <1>;
> + compatible = "allwinner,sun5i-a13-usb-phy";
> + reg = <0x01c13400 0x10 0x01c14800 0x4>;
> + reg-names = "phy_ctrl", "pmu1";
> + clocks = <&usb_clk 8>;
> + clock-names = "usb_phy";
> + resets = <&usb_clk 0>, <&usb_clk 1>;
> + reset-names = "usb0_reset", "usb1_reset";
> + status = "disabled";
> + };
> +
> + ehci0: usb@01c14000 {
> + compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
> + reg = <0x01c14000 0x100>;
> + interrupts = <39>;
> + clocks = <&ahb_gates 1>;
> + phys = <&usbphy 1>;
> + phy-names = "usb";
> + status = "disabled";
> + };
> +
> + ohci0: usb@01c14400 {
> + compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
> + reg = <0x01c14400 0x100>;
> + interrupts = <40>;
> + clocks = <&usb_clk 6>, <&ahb_gates 2>;
> + phys = <&usbphy 1>;
> + phy-names = "usb";
> + status = "disabled";
> + };
> +
> + spi2: spi@01c17000 {
> + compatible = "allwinner,sun4i-a10-spi";
> + reg = <0x01c17000 0x1000>;
> + interrupts = <12>;
> + clocks = <&ahb_gates 22>, <&spi2_clk>;
> + clock-names = "ahb", "mod";
> + dmas = <&dma SUN4I_DMA_DEDICATED 29>,
> + <&dma SUN4I_DMA_DEDICATED 28>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + intc: interrupt-controller@01c20400 {
> + compatible = "allwinner,sun4i-a10-ic";
> + reg = <0x01c20400 0x400>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> +
> + pio: pinctrl@01c20800 {
> + compatible = "nextthing,gr8-pinctrl";
> + reg = <0x01c20800 0x400>;
> + interrupts = <28>;
> + clocks = <&apb0_gates 5>;
> + gpio-controller;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + #gpio-cells = <3>;
> +
> + i2c0_pins_a: i2c0@0 {
> + allwinner,pins = "PB0", "PB1";
> + allwinner,function = "i2c0";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> + i2c1_pins_a: i2c1@0 {
> + allwinner,pins = "PB15", "PB16";
> + allwinner,function = "i2c1";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> + i2c2_pins_a: i2c2@0 {
> + allwinner,pins = "PB17", "PB18";
> + allwinner,function = "i2c2";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> + i2s0_pins_a: i2s0@0 {
> + allwinner,pins = "PB5", "PB6", "PB7", "PB8", "PB9";
> + allwinner,function = "i2s0";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> + ir0_rx_pins_a: ir0@0 {
> + allwinner,pins = "PB4";
> + allwinner,function = "ir0";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> + lcd_rgb666_pins: lcd_rgb666@0 {
> + allwinner,pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
> + "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
> + "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
> + "PD24", "PD25", "PD26", "PD27";
> + allwinner,function = "lcd0";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> + mmc0_pins_a: mmc0@0 {
> + allwinner,pins = "PF0", "PF1", "PF2", "PF3",
> + "PF4", "PF5";
> + allwinner,function = "mmc0";
> + allwinner,drive = <SUN4I_PINCTRL_30_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> + nand_pins_a: nand_base0@0 {
> + allwinner,pins = "PC0", "PC1", "PC2",
> + "PC5", "PC8", "PC9", "PC10",
> + "PC11", "PC12", "PC13", "PC14",
> + "PC15";
> + allwinner,function = "nand0";
> + allwinner,drive = <0>;
> + allwinner,pull = <0>;
> + };
> +
> + nand_cs0_pins_a: nand_cs@0 {
> + allwinner,pins = "PC4";
> + allwinner,function = "nand0";
> + allwinner,drive = <0>;
> + allwinner,pull = <0>;
> + };
> +
> + nand_rb0_pins_a: nand_rb@0 {
> + allwinner,pins = "PC6";
> + allwinner,function = "nand0";
> + allwinner,drive = <0>;
> + allwinner,pull = <0>;
> + };
> +
> + uart1_pins_a: uart1@1 {
> + allwinner,pins = "PG3", "PG4";
> + allwinner,function = "uart1";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> + uart1_cts_rts_pins_a: uart1-cts-rts@0 {
> + allwinner,pins = "PG5", "PG6";
> + allwinner,function = "uart1";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> + pwm0_pins_a: pwm0@0 {
> + allwinner,pins = "PB2";
> + allwinner,function = "pwm0";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> + };
> +
> + spdif_tx_pins_a: spdif@0 {
> + allwinner,pins = "PB10";
> + allwinner,function = "spdif";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
> + };
> + };
> +
> + pwm: pwm@01c20e00 {
> + compatible = "allwinner,sun5i-a10s-pwm";
> + reg = <0x01c20e00 0xc>;
> + clocks = <&osc24M>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + timer@01c20c00 {
> + compatible = "allwinner,sun4i-a10-timer";
> + reg = <0x01c20c00 0x90>;
> + interrupts = <22>;
> + clocks = <&osc24M>;
> + };
> +
> + wdt: watchdog@01c20c90 {
> + compatible = "allwinner,sun4i-a10-wdt";
> + reg = <0x01c20c90 0x10>;
> + };
> +
> + spdif: spdif@01c21000 {
> + #sound-dai-cells = <0>;
> + compatible = "allwinner,sun4i-a10-spdif";
> + reg = <0x01c21000 0x400>;
> + interrupts = <13>;
> + clocks = <&apb0_gates 1>, <&spdif_clk>;
> + clock-names = "apb", "spdif";
> + dmas = <&dma SUN4I_DMA_NORMAL 2>,
> + <&dma SUN4I_DMA_NORMAL 2>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + ir0: ir@01c21800 {
> + compatible = "allwinner,sun4i-a10-ir";
> + clocks = <&apb0_gates 6>, <&ir0_clk>;
> + clock-names = "apb", "ir";
> + interrupts = <5>;
> + reg = <0x01c21800 0x40>;
> + status = "disabled";
> + };
> +
> + i2s0: i2s@01c22400 {
> + #sound-dai-cells = <0>;
> + compatible = "allwinner,sun4i-a10-i2s";
> + reg = <0x01c22400 0x400>;
> + interrupts = <16>;
> + clocks = <&apb0_gates 3>, <&i2s0_clk>;
> + clock-names = "apb", "mod";
> + dmas = <&dma SUN4I_DMA_NORMAL 3>,
> + <&dma SUN4I_DMA_NORMAL 3>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + lradc: lradc@01c22800 {
> + compatible = "allwinner,sun4i-a10-lradc-keys";
> + reg = <0x01c22800 0x100>;
> + interrupts = <31>;
> + status = "disabled";
> + };
> +
> + codec: codec@01c22c00 {
> + #sound-dai-cells = <0>;
> + compatible = "allwinner,sun4i-a10-codec";
> + reg = <0x01c22c00 0x40>;
> + interrupts = <30>;
> + clocks = <&apb0_gates 0>, <&codec_clk>;
> + clock-names = "apb", "codec";
> + dmas = <&dma SUN4I_DMA_NORMAL 19>,
> + <&dma SUN4I_DMA_NORMAL 19>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + rtp: rtp@01c25000 {
> + compatible = "allwinner,sun5i-a13-ts";
> + reg = <0x01c25000 0x100>;
> + interrupts = <29>;
> + #thermal-sensor-cells = <0>;
> + };
> +
> + uart1: serial@01c28400 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c28400 0x400>;
> + interrupts = <2>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&apb1_gates 17>;
> + status = "disabled";
> + };
> +
> + uart2: serial@01c28800 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c28800 0x400>;
> + interrupts = <3>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&apb1_gates 18>;
> + status = "disabled";
> + };
> +
> + i2c0: i2c@01c2ac00 {
> + compatible = "allwinner,sun4i-a10-i2c";
> + reg = <0x01c2ac00 0x400>;
> + interrupts = <7>;
> + clocks = <&apb1_gates 0>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c1: i2c@01c2b000 {
> + compatible = "allwinner,sun4i-a10-i2c";
> + reg = <0x01c2b000 0x400>;
> + interrupts = <8>;
> + clocks = <&apb1_gates 1>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c2: i2c@01c2b400 {
> + compatible = "allwinner,sun4i-a10-i2c";
> + reg = <0x01c2b400 0x400>;
> + interrupts = <9>;
> + clocks = <&apb1_gates 2>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + timer@01c60000 {
> + compatible = "allwinner,sun5i-a13-hstimer";
> + reg = <0x01c60000 0x1000>;
> + interrupts = <82>, <83>;
> + clocks = <&ahb_gates 28>;
> + };
> +
> + fe0: display-frontend@01e00000 {
> + compatible = "allwinner,sun5i-a13-display-frontend";
> + reg = <0x01e00000 0x20000>;
> + interrupts = <47>;
> + clocks = <&ahb_gates 46>, <&de_fe_clk>,
> + <&dram_gates 25>;
> + clock-names = "ahb", "mod",
> + "ram";
> + resets = <&de_fe_clk>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + fe0_out: port@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> +
> + fe0_out_be0: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&be0_in_fe0>;
> + };
> + };
> + };
> + };
> +
> + be0: display-backend@01e60000 {
> + compatible = "allwinner,sun5i-a13-display-backend";
> + reg = <0x01e60000 0x10000>;
> + clocks = <&ahb_gates 44>, <&de_be_clk>,
> + <&dram_gates 26>;
> + clock-names = "ahb", "mod",
> + "ram";
> + resets = <&de_be_clk>;
> + status = "disabled";
> +
> + assigned-clocks = <&de_be_clk>;
> + assigned-clock-rates = <300000000>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + be0_in: port@0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0>;
> +
> + be0_in_fe0: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&fe0_out_be0>;
> + };
> + };
> +
> + be0_out: port@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> +
> + be0_out_tcon0: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&tcon0_in_be0>;
> + };
> + };
> + };
> + };
> + };
> +};
> --
> 2.9.2
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 2/6] pinctrl: sunxi: Add GR8 controller support
2016-08-31 8:18 ` [PATCH 2/6] pinctrl: sunxi: Add GR8 controller support Maxime Ripard
@ 2016-09-05 12:49 ` Chen-Yu Tsai
2016-09-07 14:04 ` Maxime Ripard
0 siblings, 1 reply; 20+ messages in thread
From: Chen-Yu Tsai @ 2016-09-05 12:49 UTC (permalink / raw)
To: Maxime Ripard
Cc: Linus Walleij, Chen-Yu Tsai, Jingoo Han, Lee Jones,
Tomi Valkeinen, Daniel Vetter, David Airlie, Thierry Reding,
linux-arm-kernel, linux-kernel, linux-gpio, dri-devel,
linux-fbdev, Mylene Josserand, Thomas Petazzoni,
Alexander Kaplan
On Wed, Aug 31, 2016 at 4:18 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> From: Mylène Josserand <mylene.josserand@free-electrons.com>
>
> Just like the other member of the sunxi family, let's add a pinctrl table
> for the muxing options.
>
> Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
> .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
> drivers/pinctrl/sunxi/Kconfig | 4 +
> drivers/pinctrl/sunxi/Makefile | 1 +
> drivers/pinctrl/sunxi/pinctrl-gr8.c | 541 +++++++++++++++++++++
> 4 files changed, 547 insertions(+)
> create mode 100644 drivers/pinctrl/sunxi/pinctrl-gr8.c
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> index 69617220c5d6..1685821eea41 100644
> --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> @@ -23,6 +23,7 @@ Required properties:
> "allwinner,sun8i-h3-pinctrl"
> "allwinner,sun8i-h3-r-pinctrl"
> "allwinner,sun50i-a64-pinctrl"
> + "nextthing,gr8-pinctrl"
>
> - reg: Should contain the register physical address and length for the
> pin controller.
> diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
> index aaf075b972f5..bff1ffc6f01e 100644
> --- a/drivers/pinctrl/sunxi/Kconfig
> +++ b/drivers/pinctrl/sunxi/Kconfig
> @@ -17,6 +17,10 @@ config PINCTRL_SUN5I_A13
> def_bool MACH_SUN5I
> select PINCTRL_SUNXI
>
> +config PINCTRL_GR8
> + def_bool MACH_SUN5I
> + select PINCTRL_SUNXI_COMMON
> +
> config PINCTRL_SUN6I_A31
> def_bool MACH_SUN6I
> select PINCTRL_SUNXI
> diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
> index 2d8b64e222e0..95f93d0561fc 100644
> --- a/drivers/pinctrl/sunxi/Makefile
> +++ b/drivers/pinctrl/sunxi/Makefile
> @@ -5,6 +5,7 @@ obj-y += pinctrl-sunxi.o
> obj-$(CONFIG_PINCTRL_SUN4I_A10) += pinctrl-sun4i-a10.o
> obj-$(CONFIG_PINCTRL_SUN5I_A10S) += pinctrl-sun5i-a10s.o
> obj-$(CONFIG_PINCTRL_SUN5I_A13) += pinctrl-sun5i-a13.o
> +obj-$(CONFIG_PINCTRL_GR8) += pinctrl-gr8.o
> obj-$(CONFIG_PINCTRL_SUN6I_A31) += pinctrl-sun6i-a31.o
> obj-$(CONFIG_PINCTRL_SUN6I_A31S) += pinctrl-sun6i-a31s.o
> obj-$(CONFIG_PINCTRL_SUN6I_A31_R) += pinctrl-sun6i-a31-r.o
> diff --git a/drivers/pinctrl/sunxi/pinctrl-gr8.c b/drivers/pinctrl/sunxi/pinctrl-gr8.c
> new file mode 100644
> index 000000000000..2904d2b7378b
> --- /dev/null
> +++ b/drivers/pinctrl/sunxi/pinctrl-gr8.c
> @@ -0,0 +1,541 @@
> +/*
> + * NextThing GR8 SoCs pinctrl driver.
> + *
> + * Copyright (C) 2016 Mylene Josserand
> + *
> + * Based on pinctrl-sun5i-a13.c
> + *
> + * Mylene Josserand <mylene.josserand@free-electrons.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/pinctrl/pinctrl.h>
> +
> +#include "pinctrl-sunxi.h"
> +
> +static const struct sunxi_desc_pin sun5i_gr8_pins[] = {
> + /* Hole */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "pwm0"),
> + SUNXI_FUNCTION(0x3, "spdif"), /* DO */
> + SUNXI_FUNCTION_IRQ(0x6, 16)), /* EINT16 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "ir0"), /* TX */
> + SUNXI_FUNCTION_IRQ(0x6, 17)), /* EINT17 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "ir0"), /* RX */
> + SUNXI_FUNCTION_IRQ(0x6, 18)), /* EINT18 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */
> + SUNXI_FUNCTION_IRQ(0x6, 19)), /* EINT19 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */
> + SUNXI_FUNCTION_IRQ(0x6, 20)), /* EINT20 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */
> + SUNXI_FUNCTION_IRQ(0x6, 21)), /* EINT21 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2s0"), /* DO */
> + SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2s0"), /* DI */
> + SUNXI_FUNCTION(0x3, "spdif"), /* DI */
> + SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */
> + SUNXI_FUNCTION(0x3, "spdif"), /* DO */
> + SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
> + SUNXI_FUNCTION(0x3, "jtag"), /* MS0 */
> + SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
> + SUNXI_FUNCTION(0x3, "jtag"), /* CK0 */
> + SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
> + SUNXI_FUNCTION(0x3, "jtag"), /* DO0 */
> + SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
> + SUNXI_FUNCTION(0x3, "jtag"), /* DI0 */
> + SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
> + /* Hole */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
> + SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
> + SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
> + SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */
> + SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0")), /* NRE */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
> + SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
> + SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
> + SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
> + SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
> + SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
> + SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */
> + SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */
> + SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */
> + SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */
> + SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
> + /* Hole */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "nand0"), /* NDQS */
> + SUNXI_FUNCTION(0x3, "uart2"), /* RX */
> + SUNXI_FUNCTION(0x4, "uart3")), /* RTS */
> + /* Hole */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
> + SUNXI_FUNCTION(0x3, "uart2")), /* TX */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
> + SUNXI_FUNCTION(0x3, "uart2")), /* RX */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
> + SUNXI_FUNCTION(0x3, "uart2")), /* CTS */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
> + SUNXI_FUNCTION(0x3, "uart2")), /* RTS */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
> + SUNXI_FUNCTION(0x3, "emac")), /* ECRS */
The cover letter said ethernet was gone?
Otherwise,
Acked-by: Chen-Yu Tsai <wens@csie.org>
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
> + SUNXI_FUNCTION(0x3, "emac")), /* ECOL */
> + /* Hole */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
> + SUNXI_FUNCTION(0x3, "emac")), /* ERXD0 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
> + SUNXI_FUNCTION(0x3, "emac")), /* ERXD1 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
> + SUNXI_FUNCTION(0x3, "emac")), /* ERXD2 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
> + SUNXI_FUNCTION(0x3, "emac")), /* ERXD3 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
> + SUNXI_FUNCTION(0x3, "emac")), /* ERXCK */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
> + SUNXI_FUNCTION(0x3, "emac")), /* ERXERR */
> + /* Hole */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
> + SUNXI_FUNCTION(0x3, "emac")), /* ERXDV */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
> + SUNXI_FUNCTION(0x3, "emac")), /* ETXD0 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
> + SUNXI_FUNCTION(0x3, "emac")), /* ETXD1 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
> + SUNXI_FUNCTION(0x3, "emac")), /* ETXD2 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
> + SUNXI_FUNCTION(0x3, "emac")), /* ETXD3 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
> + SUNXI_FUNCTION(0x3, "emac")), /* ETXEN */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
> + SUNXI_FUNCTION(0x3, "emac")), /* ETXCK */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
> + SUNXI_FUNCTION(0x3, "emac")), /* ETXERR*/
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
> + SUNXI_FUNCTION(0x3, "emac")), /* EMDC */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
> + SUNXI_FUNCTION(0x3, "emac")), /* EMDIO */
> + /* Hole */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x2, "ts0"), /* CLK */
> + SUNXI_FUNCTION(0x3, "csi0"), /* PCLK */
> + SUNXI_FUNCTION(0x4, "spi2"), /* CS0 */
> + SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x2, "ts0"), /* ERR */
> + SUNXI_FUNCTION(0x3, "csi0"), /* MCLK */
> + SUNXI_FUNCTION(0x4, "spi2"), /* CLK */
> + SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */
> + SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */
> + SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */
> + SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */
> + SUNXI_FUNCTION(0x4, "spi2")), /* MISO */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "ts0"), /* D0 */
> + SUNXI_FUNCTION(0x3, "csi0"), /* D0 */
> + SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "ts0"), /* D1 */
> + SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
> + SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "ts0"), /* D2 */
> + SUNXI_FUNCTION(0x3, "csi0"), /* D2 */
> + SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "ts0"), /* D3 */
> + SUNXI_FUNCTION(0x3, "csi0"), /* D3 */
> + SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "ts0"), /* D4 */
> + SUNXI_FUNCTION(0x3, "csi0"), /* D4 */
> + SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "ts0"), /* D5 */
> + SUNXI_FUNCTION(0x3, "csi0"), /* D5 */
> + SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "ts0"), /* D6 */
> + SUNXI_FUNCTION(0x3, "csi0"), /* D6 */
> + SUNXI_FUNCTION(0x4, "uart1")), /* TX */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "ts0"), /* D7 */
> + SUNXI_FUNCTION(0x3, "csi0"), /* D7 */
> + SUNXI_FUNCTION(0x4, "uart1")), /* RX */
> + /* Hole */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
> + SUNXI_FUNCTION(0x4, "jtag")), /* MS1 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
> + SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
> + SUNXI_FUNCTION(0x4, "uart0")), /* TX */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
> + SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
> + SUNXI_FUNCTION(0x4, "uart0")), /* RX */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
> + SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
> + /* Hole */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x2, "gps"), /* CLK */
> + SUNXI_FUNCTION_IRQ(0x6, 0)), /* EINT0 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x2, "gps"), /* SIGN */
> + SUNXI_FUNCTION_IRQ(0x6, 1)), /* EINT1 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x2, "gps"), /* MAG */
> + SUNXI_FUNCTION_IRQ(0x6, 2)), /* EINT2 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
> + SUNXI_FUNCTION(0x3, "ms"), /* BS */
> + SUNXI_FUNCTION(0x4, "uart1"), /* TX */
> + SUNXI_FUNCTION_IRQ(0x6, 3)), /* EINT3 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
> + SUNXI_FUNCTION(0x3, "ms"), /* CLK */
> + SUNXI_FUNCTION(0x4, "uart1"), /* RX */
> + SUNXI_FUNCTION_IRQ(0x6, 4)), /* EINT4 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
> + SUNXI_FUNCTION(0x3, "ms"), /* D0 */
> + SUNXI_FUNCTION(0x4, "uart1"), /* CTS */
> + SUNXI_FUNCTION_IRQ(0x6, 5)), /* EINT5 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
> + SUNXI_FUNCTION(0x3, "ms"), /* D1 */
> + SUNXI_FUNCTION(0x4, "uart1"), /* RTS */
> + SUNXI_FUNCTION(0x5, "uart2"), /* RTS */
> + SUNXI_FUNCTION_IRQ(0x6, 6)), /* EINT6 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
> + SUNXI_FUNCTION(0x3, "ms"), /* D2 */
> + SUNXI_FUNCTION(0x5, "uart2"), /* TX */
> + SUNXI_FUNCTION_IRQ(0x6, 7)), /* EINT7 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
> + SUNXI_FUNCTION(0x3, "ms"), /* D3 */
> + SUNXI_FUNCTION(0x5, "uart2"), /* RX */
> + SUNXI_FUNCTION_IRQ(0x6, 8)), /* EINT8 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
> + SUNXI_FUNCTION(0x3, "uart3"), /* TX */
> + SUNXI_FUNCTION_IRQ(0x6, 9)), /* EINT9 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
> + SUNXI_FUNCTION(0x3, "uart3"), /* RX */
> + SUNXI_FUNCTION_IRQ(0x6, 10)), /* EINT10 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
> + SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
> + SUNXI_FUNCTION_IRQ(0x6, 11)), /* EINT11 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
> + SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
> + SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
> + SUNXI_FUNCTION(0x3, "pwm1"),
> + SUNXI_FUNCTION(0x5, "uart2"), /* CTS */
> + SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */
> +};
> +
> +static const struct sunxi_pinctrl_desc sun5i_gr8_pinctrl_data = {
> + .pins = sun5i_gr8_pins,
> + .npins = ARRAY_SIZE(sun5i_gr8_pins),
> + .irq_banks = 1,
> +};
> +
> +static int sun5i_gr8_pinctrl_probe(struct platform_device *pdev)
> +{
> + return sunxi_pinctrl_init(pdev,
> + &sun5i_gr8_pinctrl_data);
> +}
> +
> +static const struct of_device_id sun5i_gr8_pinctrl_match[] = {
> + { .compatible = "nextthing,gr8-pinctrl", },
> + {}
> +};
> +MODULE_DEVICE_TABLE(of, sun5i_gr8_pinctrl_match);
> +
> +static struct platform_driver sun5i_gr8_pinctrl_driver = {
> + .probe = sun5i_gr8_pinctrl_probe,
> + .driver = {
> + .name = "gr8-pinctrl",
> + .of_match_table = sun5i_gr8_pinctrl_match,
> + },
> +};
> +module_platform_driver(sun5i_gr8_pinctrl_driver);
> +
> +MODULE_AUTHOR("Mylene Josserand <mylene.josserand@free-electrons.com");
> +MODULE_DESCRIPTION("NextThing GR8 pinctrl driver");
> +MODULE_LICENSE("GPL");
> --
> 2.9.2
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 3/6] drm/panel: simple: Add A10 EVB 5 inch panel support
2016-08-31 8:18 ` [PATCH 3/6] drm/panel: simple: Add A10 EVB 5 inch panel support Maxime Ripard
@ 2016-09-05 14:00 ` Chen-Yu Tsai
2016-09-09 14:34 ` Maxime Ripard
0 siblings, 1 reply; 20+ messages in thread
From: Chen-Yu Tsai @ 2016-09-05 14:00 UTC (permalink / raw)
To: Maxime Ripard
Cc: Linus Walleij, Chen-Yu Tsai, Jingoo Han, Lee Jones,
Tomi Valkeinen, Daniel Vetter, David Airlie, Thierry Reding,
linux-arm-kernel, linux-kernel, linux-gpio, dri-devel,
linux-fbdev, Mylene Josserand, Thomas Petazzoni,
Alexander Kaplan
On Wed, Aug 31, 2016 at 4:18 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> The A10-EVB from Allwinner comes with an unidentified panel, with the only
> mark on the PCB being A10-SUB-EVB-5LCD.
>
> Add timings to simple panel to handle it.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
> drivers/gpu/drm/panel/panel-simple.c | 26 ++++++++++++++++++++++++++
> 1 file changed, 26 insertions(+)
>
> diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
> index 85143d1b9b31..be371b053aab 100644
> --- a/drivers/gpu/drm/panel/panel-simple.c
> +++ b/drivers/gpu/drm/panel/panel-simple.c
> @@ -386,6 +386,29 @@ static void panel_simple_shutdown(struct device *dev)
> panel_simple_disable(&panel->base);
> }
>
> +static const struct drm_display_mode allwinner_a10_sub_evb_5lcd_mode = {
> + .clock = 33000,
> + .hdisplay = 800,
> + .hsync_start = 800 + 209,
> + .hsync_end = 800 + 209 + 1,
> + .htotal = 800 + 209 + 1 + 45,
> + .vdisplay = 480,
> + .vsync_start = 480 + 22,
> + .vsync_end = 480 + 22 + 1,
> + .vtotal = 480 + 22 + 1 + 22,
> + .vrefresh = 60,
I assume the numbers came from the fex file? Allwinner LCD timing numbers
aren't very precise. This seems to yield a refresh rate of 58.x Hz.
The dot clock can go below MHz resolution, so it should be possible
to set it to a more proper clock rate here.
ChenYu
> +};
> +
> +static const struct panel_desc allwinner_a10_sub_evb_5lcd = {
> + .modes = &allwinner_a10_sub_evb_5lcd_mode,
> + .num_modes = 1,
> + .size = {
> + .width = 110,
> + .height = 67,
> + },
> + .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
> +};
> +
> static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
> .clock = 33333,
> .hdisplay = 800,
> @@ -1515,6 +1538,9 @@ static const struct panel_desc urt_umsh_8596md_parallel = {
>
> static const struct of_device_id platform_of_match[] = {
> {
> + .compatible = "allwinner,sun4i-a10-sub-evb-5-lcd",
> + .data = &allwinner_a10_sub_evb_5lcd,
> + }, {
> .compatible = "ampire,am800480r3tmqwa1h",
> .data = &ire_am800480r3tmqwa1h,
> }, {
> --
> 2.9.2
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 2/6] pinctrl: sunxi: Add GR8 controller support
2016-09-05 12:49 ` Chen-Yu Tsai
@ 2016-09-07 14:04 ` Maxime Ripard
0 siblings, 0 replies; 20+ messages in thread
From: Maxime Ripard @ 2016-09-07 14:04 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: Linus Walleij, Jingoo Han, Lee Jones, Tomi Valkeinen,
Daniel Vetter, David Airlie, Thierry Reding, linux-arm-kernel,
linux-kernel, linux-gpio, dri-devel, linux-fbdev,
Mylene Josserand, Thomas Petazzoni, Alexander Kaplan
[-- Attachment #1: Type: text/plain, Size: 631 bytes --]
On Mon, Sep 05, 2016 at 08:49:55PM +0800, Chen-Yu Tsai wrote:
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
> > + SUNXI_FUNCTION(0x3, "emac")), /* ECRS */
>
> The cover letter said ethernet was gone?
That was my understanding, I doubled check and it's indeed there. I'll
amend the commit log. Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 5/6] ARM: dts: Add NextThing GR8 dtsi
2016-08-31 8:18 ` [PATCH 5/6] ARM: dts: Add NextThing GR8 dtsi Maxime Ripard
2016-09-05 12:47 ` Chen-Yu Tsai
@ 2016-09-07 14:51 ` Javier Martinez Canillas
2016-09-08 9:57 ` Maxime Ripard
2016-09-07 17:51 ` Rask Ingemann Lambertsen
2 siblings, 1 reply; 20+ messages in thread
From: Javier Martinez Canillas @ 2016-09-07 14:51 UTC (permalink / raw)
To: Maxime Ripard
Cc: Linus Walleij, Chen-Yu Tsai, Jingoo Han, Lee Jones,
Tomi Valkeinen, Daniel Vetter, David Airlie, Thierry Reding,
linux-arm-kernel, Linux Kernel, Linux GPIO List, dri-devel,
linux-fbdev, Mylene Josserand, Thomas Petazzoni,
Alexander Kaplan
Hello Maxime,
On Wed, Aug 31, 2016 at 10:18 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
[snip]
> +
> +#include "skeleton.dtsi"
> +
The skeleton.dtsi has been deprecated and shouldn't be used in new DTS files:
http://www.spinics.net/lists/arm-kernel/msg528080.html
Best regards,
Javier
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 5/6] ARM: dts: Add NextThing GR8 dtsi
2016-08-31 8:18 ` [PATCH 5/6] ARM: dts: Add NextThing GR8 dtsi Maxime Ripard
2016-09-05 12:47 ` Chen-Yu Tsai
2016-09-07 14:51 ` Javier Martinez Canillas
@ 2016-09-07 17:51 ` Rask Ingemann Lambertsen
2016-09-08 10:00 ` Maxime Ripard
2 siblings, 1 reply; 20+ messages in thread
From: Rask Ingemann Lambertsen @ 2016-09-07 17:51 UTC (permalink / raw)
To: Maxime Ripard
Cc: Chen-Yu Tsai, Thomas Petazzoni, linux-fbdev, David Airlie,
Jingoo Han, Linus Walleij, linux-kernel, dri-devel, linux-gpio,
Tomi Valkeinen, Thierry Reding, Daniel Vetter, Alexander Kaplan,
Mylene Josserand, Lee Jones, linux-arm-kernel
On Wed, Aug 31, 2016 at 4:18 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> From: Mylène Josserand <mylene.josserand@free-electrons.com>
>
> The GR8 is an SoC made by Nextthing loosely based on the sun5i family.
>
> Since it's not clear yet what we can factor out and merge with the A10s and
> A13 support, let's keep it out of the sun5i.dtsi include tree. We will
> figure out what can be shared when things settle down.
>
> Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
> arch/arm/boot/dts/gr8.dtsi | 1080 ++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 1080 insertions(+)
> create mode 100644 arch/arm/boot/dts/gr8.dtsi
>
> diff --git a/arch/arm/boot/dts/gr8.dtsi b/arch/arm/boot/dts/gr8.dtsi
> new file mode 100644
> index 000000000000..d21cfa3f3c14
> --- /dev/null
> +++ b/arch/arm/boot/dts/gr8.dtsi
In the node names, you sometimes use underscores and sometimes use hyphens.
Here are the ones I spotted:
> + osc3M: osc3M_clk {
> + pll3x2: pll3x2_clk {
> + pll7x2: pll7x2_clk {
> + display-engine {
> + sram-controller@01c00000 {
> + otg_sram: sram-section@0000 {
> + dma: dma-controller@01c02000 {
> + tve0: tv-encoder@01c0a000 {
> + tcon0: lcd-controller@01c0c000 {
> + intc: interrupt-controller@01c20400 {
> + lcd_rgb666_pins: lcd_rgb666@0 {
> + nand_pins_a: nand_base0@0 {
> + nand_cs0_pins_a: nand_cs@0 {
> + nand_rb0_pins_a: nand_rb@0 {
> + uart1_cts_rts_pins_a: uart1-cts-rts@0 {
> + fe0: display-frontend@01e00000 {
> + be0: display-backend@01e60000 {
Underscores should not be used in node names. [1][2] Since you're adding a
new file here, please use hyphens instead.
[1] https://www.mail-archive.com/linux-kernel%40vger.kernel.org/msg1122967.html
[2] https://www.mail-archive.com/linux-kernel%40vger.kernel.org/msg1145633.html
--
Rask Ingemann Lambertsen
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 5/6] ARM: dts: Add NextThing GR8 dtsi
2016-09-07 14:51 ` Javier Martinez Canillas
@ 2016-09-08 9:57 ` Maxime Ripard
0 siblings, 0 replies; 20+ messages in thread
From: Maxime Ripard @ 2016-09-08 9:57 UTC (permalink / raw)
To: Javier Martinez Canillas
Cc: Linus Walleij, Chen-Yu Tsai, Jingoo Han, Lee Jones,
Tomi Valkeinen, Daniel Vetter, David Airlie, Thierry Reding,
linux-arm-kernel, Linux Kernel, Linux GPIO List, dri-devel,
linux-fbdev, Mylene Josserand, Thomas Petazzoni,
Alexander Kaplan
[-- Attachment #1: Type: text/plain, Size: 571 bytes --]
Hi Javier,
On Wed, Sep 07, 2016 at 04:51:55PM +0200, Javier Martinez Canillas wrote:
> Hello Maxime,
>
> On Wed, Aug 31, 2016 at 10:18 AM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
>
> [snip]
>
> > +
> > +#include "skeleton.dtsi"
> > +
>
> The skeleton.dtsi has been deprecated and shouldn't be used in new DTS files:
>
> http://www.spinics.net/lists/arm-kernel/msg528080.html
Ok, thanks, I'll change it in the v3.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 5/6] ARM: dts: Add NextThing GR8 dtsi
2016-09-07 17:51 ` Rask Ingemann Lambertsen
@ 2016-09-08 10:00 ` Maxime Ripard
0 siblings, 0 replies; 20+ messages in thread
From: Maxime Ripard @ 2016-09-08 10:00 UTC (permalink / raw)
To: Rask Ingemann Lambertsen, Rob Herring
Cc: Chen-Yu Tsai, Thomas Petazzoni, linux-fbdev, David Airlie,
Jingoo Han, Linus Walleij, linux-kernel, dri-devel, linux-gpio,
Tomi Valkeinen, Thierry Reding, Daniel Vetter, Alexander Kaplan,
Mylene Josserand, Lee Jones, linux-arm-kernel
[-- Attachment #1: Type: text/plain, Size: 2524 bytes --]
On Wed, Sep 07, 2016 at 07:51:48PM +0200, Rask Ingemann Lambertsen wrote:
> On Wed, Aug 31, 2016 at 4:18 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > From: Mylène Josserand <mylene.josserand@free-electrons.com>
> >
> > The GR8 is an SoC made by Nextthing loosely based on the sun5i family.
> >
> > Since it's not clear yet what we can factor out and merge with the A10s and
> > A13 support, let's keep it out of the sun5i.dtsi include tree. We will
> > figure out what can be shared when things settle down.
> >
> > Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com>
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> > ---
> > arch/arm/boot/dts/gr8.dtsi | 1080 ++++++++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 1080 insertions(+)
> > create mode 100644 arch/arm/boot/dts/gr8.dtsi
> >
> > diff --git a/arch/arm/boot/dts/gr8.dtsi b/arch/arm/boot/dts/gr8.dtsi
> > new file mode 100644
> > index 000000000000..d21cfa3f3c14
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/gr8.dtsi
>
> In the node names, you sometimes use underscores and sometimes use hyphens.
> Here are the ones I spotted:
>
> > + osc3M: osc3M_clk {
> > + pll3x2: pll3x2_clk {
> > + pll7x2: pll7x2_clk {
> > + display-engine {
> > + sram-controller@01c00000 {
> > + otg_sram: sram-section@0000 {
> > + dma: dma-controller@01c02000 {
> > + tve0: tv-encoder@01c0a000 {
> > + tcon0: lcd-controller@01c0c000 {
> > + intc: interrupt-controller@01c20400 {
> > + lcd_rgb666_pins: lcd_rgb666@0 {
> > + nand_pins_a: nand_base0@0 {
> > + nand_cs0_pins_a: nand_cs@0 {
> > + nand_rb0_pins_a: nand_rb@0 {
> > + uart1_cts_rts_pins_a: uart1-cts-rts@0 {
> > + fe0: display-frontend@01e00000 {
> > + be0: display-backend@01e60000 {
>
> Underscores should not be used in node names. [1][2] Since you're adding a
> new file here, please use hyphens instead.
I wonder what the rationale behind this is. The ePAPR clearly
documents the underscore as being a valid character for the node
names.
I'll change the few inconsistencies though.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 3/6] drm/panel: simple: Add A10 EVB 5 inch panel support
2016-09-05 14:00 ` Chen-Yu Tsai
@ 2016-09-09 14:34 ` Maxime Ripard
0 siblings, 0 replies; 20+ messages in thread
From: Maxime Ripard @ 2016-09-09 14:34 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: Linus Walleij, Jingoo Han, Lee Jones, Tomi Valkeinen,
Daniel Vetter, David Airlie, Thierry Reding, linux-arm-kernel,
linux-kernel, linux-gpio, dri-devel, linux-fbdev,
Mylene Josserand, Thomas Petazzoni, Alexander Kaplan
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Hi,
On Mon, Sep 05, 2016 at 10:00:01PM +0800, Chen-Yu Tsai wrote:
> On Wed, Aug 31, 2016 at 4:18 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > The A10-EVB from Allwinner comes with an unidentified panel, with the only
> > mark on the PCB being A10-SUB-EVB-5LCD.
> >
> > Add timings to simple panel to handle it.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> > ---
> > drivers/gpu/drm/panel/panel-simple.c | 26 ++++++++++++++++++++++++++
> > 1 file changed, 26 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
> > index 85143d1b9b31..be371b053aab 100644
> > --- a/drivers/gpu/drm/panel/panel-simple.c
> > +++ b/drivers/gpu/drm/panel/panel-simple.c
> > @@ -386,6 +386,29 @@ static void panel_simple_shutdown(struct device *dev)
> > panel_simple_disable(&panel->base);
> > }
> >
> > +static const struct drm_display_mode allwinner_a10_sub_evb_5lcd_mode = {
> > + .clock = 33000,
> > + .hdisplay = 800,
> > + .hsync_start = 800 + 209,
> > + .hsync_end = 800 + 209 + 1,
> > + .htotal = 800 + 209 + 1 + 45,
> > + .vdisplay = 480,
> > + .vsync_start = 480 + 22,
> > + .vsync_end = 480 + 22 + 1,
> > + .vtotal = 480 + 22 + 1 + 22,
> > + .vrefresh = 60,
>
> I assume the numbers came from the fex file? Allwinner LCD timing numbers
> aren't very precise. This seems to yield a refresh rate of 58.x Hz.
> The dot clock can go below MHz resolution, so it should be possible
> to set it to a more proper clock rate here.
Indeed.
Upon closer inspection, it seems (from the ribbon) that the display is
an hannstar, but there's no screen reference anywhere.
By looking into it using the available references, the date of
production found on that panel, and so on, it seems like it is an
HSD050IDW1-A, whose timings do not seem to far off. But it's pure
speculation at this point.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2016-09-09 14:34 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-08-31 8:18 [PATCH 0/6] Introduce NextThing GR8 support Maxime Ripard
2016-08-31 8:18 ` [PATCH 1/6] backlight: pwm_bl: Handle gpio that can sleep Maxime Ripard
2016-08-31 12:25 ` Lee Jones
2016-08-31 8:18 ` [PATCH 2/6] pinctrl: sunxi: Add GR8 controller support Maxime Ripard
2016-09-05 12:49 ` Chen-Yu Tsai
2016-09-07 14:04 ` Maxime Ripard
2016-08-31 8:18 ` [PATCH 3/6] drm/panel: simple: Add A10 EVB 5 inch panel support Maxime Ripard
2016-09-05 14:00 ` Chen-Yu Tsai
2016-09-09 14:34 ` Maxime Ripard
2016-08-31 8:18 ` [PATCH 4/6] ARM: sunxi: Support the Nextthing GR8 Maxime Ripard
2016-08-31 8:25 ` Chen-Yu Tsai
2016-09-02 6:28 ` Maxime Ripard
2016-08-31 8:18 ` [PATCH 5/6] ARM: dts: Add NextThing GR8 dtsi Maxime Ripard
2016-09-05 12:47 ` Chen-Yu Tsai
2016-09-07 14:51 ` Javier Martinez Canillas
2016-09-08 9:57 ` Maxime Ripard
2016-09-07 17:51 ` Rask Ingemann Lambertsen
2016-09-08 10:00 ` Maxime Ripard
2016-08-31 8:18 ` [PATCH 6/6] ARM: dts: gr8: Add support for the GR8 evaluation board Maxime Ripard
2016-09-05 12:42 ` Chen-Yu Tsai
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