[PATCH] clk: ingenic: Fix recalc_rate for clocks with fixed divider

From: Paul Cercueil <paul@crapouillou.net>
To: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@codeaurora.org>,
	Harvey Hunt <harvey.hunt@imgtec.com>,
	Paul Burton <paul.burton@imgtec.com>,
	linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: Maarten ter Huurne <maarten@treewalker.org>,
	Paul Cercueil <paul@crapouillou.net>
Subject: [PATCH] clk: ingenic: Fix recalc_rate for clocks with fixed divider
Date: Tue,  1 Nov 2016 10:58:36 +0100	[thread overview]
Message-ID: <20161101095836.22210-1-paul@crapouillou.net> (raw)

Previously, the clocks with a fixed divider would report their rate
as being the same as the one of their parent, independently of the
divider in use. This commit fixes this behaviour.

This went unnoticed as neither the jz4740 nor the jz4780 CGU code
have clocks with fixed dividers yet.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
 drivers/clk/ingenic/cgu.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c
index e8248f9..eb9002c 100644
--- a/drivers/clk/ingenic/cgu.c
+++ b/drivers/clk/ingenic/cgu.c
@@ -328,6 +328,8 @@ ingenic_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 		div *= clk_info->div.div;
 
 		rate /= div;
+	} else if (clk_info->type & CGU_CLK_FIXDIV) {
+		rate /= clk_info->fixdiv.div;
 	}
 
 	return rate;
-- 
2.10.1
