* [PATCH 1/2] ahci: qoriq: added a condition to enable dma coherence
@ 2016-11-16 3:11 yuantian.tang
2016-11-16 3:11 ` [PATCH 2/2] ahci: qoriq: report warning when ecc register is missing yuantian.tang
2016-11-16 16:02 ` [PATCH 1/2] ahci: qoriq: added a condition to enable dma coherence Robin Murphy
0 siblings, 2 replies; 4+ messages in thread
From: yuantian.tang @ 2016-11-16 3:11 UTC (permalink / raw)
To: tj
Cc: linux-ide, linux-kernel, linux-arm-kernel, Tang Yuantian, Tang Yuantian
From: Tang Yuantian <Yuantian.Tang@nxp.com>
Enable DMA coherence in SATA controller on condition that
dma-coherent property exists in sata node in DTS.
Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
---
drivers/ata/ahci_qoriq.c | 15 +++++++++++----
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c
index 9884c8c..45c88de 100644
--- a/drivers/ata/ahci_qoriq.c
+++ b/drivers/ata/ahci_qoriq.c
@@ -59,6 +59,7 @@ struct ahci_qoriq_priv {
struct ccsr_ahci *reg_base;
enum ahci_qoriq_type type;
void __iomem *ecc_addr;
+ bool is_dmacoherent;
};
static const struct of_device_id ahci_qoriq_of_match[] = {
@@ -164,26 +165,31 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
- writel(AHCI_PORT_AXICC_CFG, reg_base + LS1021A_AXICC_ADDR);
+ if (qpriv->is_dmacoherent)
+ writel(AHCI_PORT_AXICC_CFG,
+ reg_base + LS1021A_AXICC_ADDR);
break;
case AHCI_LS1043A:
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
- writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
+ if (qpriv->is_dmacoherent)
+ writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
break;
case AHCI_LS2080A:
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
- writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
+ if (qpriv->is_dmacoherent)
+ writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
break;
case AHCI_LS1046A:
writel(LS1046A_SATA_ECC_DIS, qpriv->ecc_addr);
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
- writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
+ if (qpriv->is_dmacoherent)
+ writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
break;
}
@@ -221,6 +227,7 @@ static int ahci_qoriq_probe(struct platform_device *pdev)
if (IS_ERR(qoriq_priv->ecc_addr))
return PTR_ERR(qoriq_priv->ecc_addr);
}
+ qoriq_priv->is_dmacoherent = of_property_read_bool(np, "dma-coherent");
rc = ahci_platform_enable_resources(hpriv);
if (rc)
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/2] ahci: qoriq: report warning when ecc register is missing
2016-11-16 3:11 [PATCH 1/2] ahci: qoriq: added a condition to enable dma coherence yuantian.tang
@ 2016-11-16 3:11 ` yuantian.tang
2016-11-16 15:56 ` Mathieu Poirier
2016-11-16 16:02 ` [PATCH 1/2] ahci: qoriq: added a condition to enable dma coherence Robin Murphy
1 sibling, 1 reply; 4+ messages in thread
From: yuantian.tang @ 2016-11-16 3:11 UTC (permalink / raw)
To: tj
Cc: linux-ide, linux-kernel, linux-arm-kernel, Tang Yuantian, Tang Yuantian
From: Tang Yuantian <Yuantian.Tang@nxp.com>
For ls1021a and ls1046a socs, sata ecc must be disabled.
If ecc register is not found in sata node in dts, report
a warning.
Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
---
drivers/ata/ahci_qoriq.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c
index 45c88de..66eb4b5 100644
--- a/drivers/ata/ahci_qoriq.c
+++ b/drivers/ata/ahci_qoriq.c
@@ -158,6 +158,7 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
switch (qpriv->type) {
case AHCI_LS1021A:
+ WARN_ON(!qpriv->ecc_addr);
writel(SATA_ECC_DISABLE, qpriv->ecc_addr);
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2);
@@ -185,6 +186,7 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
break;
case AHCI_LS1046A:
+ WARN_ON(!qpriv->ecc_addr);
writel(LS1046A_SATA_ECC_DIS, qpriv->ecc_addr);
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 2/2] ahci: qoriq: report warning when ecc register is missing
2016-11-16 3:11 ` [PATCH 2/2] ahci: qoriq: report warning when ecc register is missing yuantian.tang
@ 2016-11-16 15:56 ` Mathieu Poirier
0 siblings, 0 replies; 4+ messages in thread
From: Mathieu Poirier @ 2016-11-16 15:56 UTC (permalink / raw)
To: yuantian.tang; +Cc: tj, linux-ide, linux-kernel, linux-arm-kernel
On Wed, Nov 16, 2016 at 11:11:19AM +0800, yuantian.tang@nxp.com wrote:
> From: Tang Yuantian <Yuantian.Tang@nxp.com>
>
> For ls1021a and ls1046a socs, sata ecc must be disabled.
> If ecc register is not found in sata node in dts, report
> a warning.
Hi Yuantian,
What happens if sata ecc is _not_ disaled on those socs? Can the driver still
work? If not then it is probably a better idea to return an error code that can
prevent the driver from initialising.
Thanks,
Mathieu
>
> Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
> ---
> drivers/ata/ahci_qoriq.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c
> index 45c88de..66eb4b5 100644
> --- a/drivers/ata/ahci_qoriq.c
> +++ b/drivers/ata/ahci_qoriq.c
> @@ -158,6 +158,7 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
>
> switch (qpriv->type) {
> case AHCI_LS1021A:
> + WARN_ON(!qpriv->ecc_addr);
> writel(SATA_ECC_DISABLE, qpriv->ecc_addr);
> writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
> writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2);
> @@ -185,6 +186,7 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
> break;
>
> case AHCI_LS1046A:
> + WARN_ON(!qpriv->ecc_addr);
> writel(LS1046A_SATA_ECC_DIS, qpriv->ecc_addr);
> writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
> writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
> --
> 2.1.0.27.g96db324
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 1/2] ahci: qoriq: added a condition to enable dma coherence
2016-11-16 3:11 [PATCH 1/2] ahci: qoriq: added a condition to enable dma coherence yuantian.tang
2016-11-16 3:11 ` [PATCH 2/2] ahci: qoriq: report warning when ecc register is missing yuantian.tang
@ 2016-11-16 16:02 ` Robin Murphy
1 sibling, 0 replies; 4+ messages in thread
From: Robin Murphy @ 2016-11-16 16:02 UTC (permalink / raw)
To: yuantian.tang, tj; +Cc: linux-ide, linux-kernel, linux-arm-kernel
On 16/11/16 03:11, yuantian.tang@nxp.com wrote:
> From: Tang Yuantian <Yuantian.Tang@nxp.com>
>
> Enable DMA coherence in SATA controller on condition that
> dma-coherent property exists in sata node in DTS.
>
> Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
> ---
> drivers/ata/ahci_qoriq.c | 15 +++++++++++----
> 1 file changed, 11 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c
> index 9884c8c..45c88de 100644
> --- a/drivers/ata/ahci_qoriq.c
> +++ b/drivers/ata/ahci_qoriq.c
> @@ -59,6 +59,7 @@ struct ahci_qoriq_priv {
> struct ccsr_ahci *reg_base;
> enum ahci_qoriq_type type;
> void __iomem *ecc_addr;
> + bool is_dmacoherent;
> };
>
> static const struct of_device_id ahci_qoriq_of_match[] = {
> @@ -164,26 +165,31 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
> writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
> writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
> writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
> - writel(AHCI_PORT_AXICC_CFG, reg_base + LS1021A_AXICC_ADDR);
> + if (qpriv->is_dmacoherent)
> + writel(AHCI_PORT_AXICC_CFG,
> + reg_base + LS1021A_AXICC_ADDR);
> break;
>
> case AHCI_LS1043A:
> writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
> writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
> - writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
> + if (qpriv->is_dmacoherent)
> + writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
> break;
>
> case AHCI_LS2080A:
> writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
> writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
> - writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
> + if (qpriv->is_dmacoherent)
> + writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
> break;
>
> case AHCI_LS1046A:
> writel(LS1046A_SATA_ECC_DIS, qpriv->ecc_addr);
> writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
> writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
> - writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
> + if (qpriv->is_dmacoherent)
> + writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
> break;
> }
>
> @@ -221,6 +227,7 @@ static int ahci_qoriq_probe(struct platform_device *pdev)
> if (IS_ERR(qoriq_priv->ecc_addr))
> return PTR_ERR(qoriq_priv->ecc_addr);
> }
> + qoriq_priv->is_dmacoherent = of_property_read_bool(np, "dma-coherent");
Better to use of_dma_is_coherent(np) rather than open-coding it.
Robin.
>
> rc = ahci_platform_enable_resources(hpriv);
> if (rc)
>
^ permalink raw reply [flat|nested] 4+ messages in thread
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2016-11-16 15:56 ` Mathieu Poirier
2016-11-16 16:02 ` [PATCH 1/2] ahci: qoriq: added a condition to enable dma coherence Robin Murphy
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