* [PATCH v2 1/1] net: macb: ensure ordering write to re-enable RX smoothly
@ 2016-11-28 13:55 Zumeng Chen
2016-11-28 14:04 ` Nicolas Ferre
2016-11-30 1:34 ` David Miller
0 siblings, 2 replies; 3+ messages in thread
From: Zumeng Chen @ 2016-11-28 13:55 UTC (permalink / raw)
To: nicolas.ferre; +Cc: davem, netdev, linux-kernel
When a hardware issue happened as described by inline comments, the register
write pattern looks like the following:
<write ~MACB_BIT(RE)>
+ wmb();
<write MACB_BIT(RE)>
There might be a memory barrier between these two write operations, so add wmb
to ensure an flip from 0 to 1 for NCR.
Signed-off-by: Zumeng Chen <zumeng.chen@windriver.com>
---
V2 changes:
Add the same wmb for at91ether as well based on reviewer's suggestion.
Cheers,
drivers/net/ethernet/cadence/macb.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
index 533653b..6d7cfa7 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -1156,6 +1156,7 @@ static irqreturn_t macb_interrupt(int irq, void *dev_id)
if (status & MACB_BIT(RXUBR)) {
ctrl = macb_readl(bp, NCR);
macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
+ wmb();
macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
@@ -2770,6 +2771,7 @@ static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
if (intstatus & MACB_BIT(RXUBR)) {
ctl = macb_readl(lp, NCR);
macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
+ wmb();
macb_writel(lp, NCR, ctl | MACB_BIT(RE));
}
--
2.4.11
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v2 1/1] net: macb: ensure ordering write to re-enable RX smoothly
2016-11-28 13:55 [PATCH v2 1/1] net: macb: ensure ordering write to re-enable RX smoothly Zumeng Chen
@ 2016-11-28 14:04 ` Nicolas Ferre
2016-11-30 1:34 ` David Miller
1 sibling, 0 replies; 3+ messages in thread
From: Nicolas Ferre @ 2016-11-28 14:04 UTC (permalink / raw)
To: Zumeng Chen
Cc: davem, netdev, linux-kernel, Cyrille Pitchen, Andrei Pistirica
Le 28/11/2016 à 14:55, Zumeng Chen a écrit :
> When a hardware issue happened as described by inline comments, the register
> write pattern looks like the following:
>
> <write ~MACB_BIT(RE)>
> + wmb();
> <write MACB_BIT(RE)>
>
> There might be a memory barrier between these two write operations, so add wmb
> to ensure an flip from 0 to 1 for NCR.
>
> Signed-off-by: Zumeng Chen <zumeng.chen@windriver.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Thanks, best regards,
> ---
>
> V2 changes:
>
> Add the same wmb for at91ether as well based on reviewer's suggestion.
>
> Cheers,
> drivers/net/ethernet/cadence/macb.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
> index 533653b..6d7cfa7 100644
> --- a/drivers/net/ethernet/cadence/macb.c
> +++ b/drivers/net/ethernet/cadence/macb.c
> @@ -1156,6 +1156,7 @@ static irqreturn_t macb_interrupt(int irq, void *dev_id)
> if (status & MACB_BIT(RXUBR)) {
> ctrl = macb_readl(bp, NCR);
> macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
> + wmb();
> macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
>
> if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
> @@ -2770,6 +2771,7 @@ static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
> if (intstatus & MACB_BIT(RXUBR)) {
> ctl = macb_readl(lp, NCR);
> macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
> + wmb();
> macb_writel(lp, NCR, ctl | MACB_BIT(RE));
> }
>
>
--
Nicolas Ferre
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v2 1/1] net: macb: ensure ordering write to re-enable RX smoothly
2016-11-28 13:55 [PATCH v2 1/1] net: macb: ensure ordering write to re-enable RX smoothly Zumeng Chen
2016-11-28 14:04 ` Nicolas Ferre
@ 2016-11-30 1:34 ` David Miller
1 sibling, 0 replies; 3+ messages in thread
From: David Miller @ 2016-11-30 1:34 UTC (permalink / raw)
To: zumeng.chen; +Cc: nicolas.ferre, netdev, linux-kernel
From: Zumeng Chen <zumeng.chen@windriver.com>
Date: Mon, 28 Nov 2016 21:55:00 +0800
> When a hardware issue happened as described by inline comments, the register
> write pattern looks like the following:
>
> <write ~MACB_BIT(RE)>
> + wmb();
> <write MACB_BIT(RE)>
>
> There might be a memory barrier between these two write operations, so add wmb
> to ensure an flip from 0 to 1 for NCR.
>
> Signed-off-by: Zumeng Chen <zumeng.chen@windriver.com>
> ---
>
> V2 changes:
>
> Add the same wmb for at91ether as well based on reviewer's suggestion.
Applied, thanks.
^ permalink raw reply [flat|nested] 3+ messages in thread
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2016-11-28 13:55 [PATCH v2 1/1] net: macb: ensure ordering write to re-enable RX smoothly Zumeng Chen
2016-11-28 14:04 ` Nicolas Ferre
2016-11-30 1:34 ` David Miller
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