From: Bin Liu <b-liu@ti.com>
To: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Icenowy Zheng <icenowy@aosc.xyz>, Chen-Yu Tsai <wens@csie.org>,
Kishon Vijay Abraham I <kishon@ti.com>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-usb@vger.kernel.org" <linux-usb@vger.kernel.org>
Subject: Re: [PATCH 4/4] ARM: dts: sun8i: add OTG function to Lichee Pi Zero
Date: Thu, 12 Jan 2017 08:50:14 -0600 [thread overview]
Message-ID: <20170112145014.GC16865@uda0271908> (raw)
In-Reply-To: <20170111210638.ppdnpzdd2l6x4lyo@lukather>
On Wed, Jan 11, 2017 at 10:06:38PM +0100, Maxime Ripard wrote:
> On Wed, Jan 11, 2017 at 02:08:11PM -0600, Bin Liu wrote:
> > On Thu, Jan 12, 2017 at 03:55:33AM +0800, Icenowy Zheng wrote:
> > >
> > >
> > > 11.01.2017, 04:24, "Bin Liu" <b-liu@ti.com>:
> > > > On Tue, Jan 03, 2017 at 11:25:34PM +0800, Icenowy Zheng wrote:
> > > >> Lichee Pi Zero features a USB OTG port.
> > > >>
> > > >> Add support for it.
> > > >>
> > > >> Note: in order to use the Host mode, the board must be powered via the
> > > >> +5V and GND pins.
> > > >>
> > > >> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> > > >> ---
> > > >> arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 10 ++++++++++
> > > >> 1 file changed, 10 insertions(+)
> > > >>
> > > >> diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
> > > >> index 0099affc6ce3..3d9168cbaeca 100644
> > > >> --- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
> > > >> +++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
> > > >> @@ -71,3 +71,13 @@
> > > >> pinctrl-names = "default";
> > > >> status = "okay";
> > > >> };
> > > >> +
> > > >> +&usb_otg {
> > > >> + dr_mode = "otg";
> > > >
> > > > Why not set this default mode in dtsi instead?
> > > >
> > > > Regards,
> > > > -Bin.
> > >
> > > There's possibly boards which do not have OTG functions.
> >
> > That is board specific.
>
> Exactly, and this is why it should be done in the board DT.
I am just suggesting based on the common practice. If a .dtsi exists for
a family, the .dtsi describes the device and common properties for all
possible boards, and each board .dts adds or overrides its specific
implementation. Kernel has many devices/boards done in this way - define
the default dr_mode in .dtsi.
In this case, I suggest to set the common dr_mode in .dtsi, then each
board .dts only overrides it if the implementation is different.
>
> The controller in the Allwinner SoCs do not handle directly the ID pin
> and VBUS, but rather rely on a GPIO to do so.
>
> So boards with OTG will need setup anyway, at least to tell which
> GPIOs are used. There's no point in enforcing a default if it doesn't
> work by default.
Then define a default which supposes to work for most boards.
Why I suggest this, is because defining a default dr_mode which works
for most cases in dtsi could prevent a little surprise in MUSB function.
If someone designs a new board but forgets to define dr_mode in the new
board DT, the MUSB driver will default to org mode, which might not be
intended.
Regards,
-Bin.
next prev parent reply other threads:[~2017-01-12 14:51 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20170103152534.20118-1-icenowy@aosc.xyz>
[not found] ` <20170103152534.20118-2-icenowy@aosc.xyz>
2017-01-06 13:56 ` [PATCH 1/4] phy: sun4i-usb: add support for V3s USB PHY Maxime Ripard
2017-01-16 9:06 ` Kishon Vijay Abraham I
[not found] ` <20170103152534.20118-3-icenowy@aosc.xyz>
2017-01-06 13:57 ` [PATCH 2/4] musb: sunxi: add support for the variant in H3/V3s SoC Maxime Ripard
2017-01-17 14:38 ` Bin Liu
[not found] ` <20170103152534.20118-4-icenowy@aosc.xyz>
2017-01-06 14:19 ` [PATCH 3/4] ARM: dts: sunxi: add usb_otg and usbphy node for V3s SoC Maxime Ripard
[not found] ` <20170103152534.20118-5-icenowy@aosc.xyz>
2017-01-10 20:24 ` [PATCH 4/4] ARM: dts: sun8i: add OTG function to Lichee Pi Zero Bin Liu
[not found] ` <2733831484164533@web1g.yandex.ru>
2017-01-11 20:08 ` Bin Liu
[not found] ` <418251484165614@web21h.yandex.ru>
2017-01-11 20:33 ` Bin Liu
2017-01-11 21:06 ` Maxime Ripard
2017-01-12 14:50 ` Bin Liu [this message]
2017-01-12 17:39 ` Maxime Ripard
2017-01-13 21:00 ` Bin Liu
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