* [PATCH V3 0/5] PCI: exynos: cleans the minor things
[not found] <CGME20170116063140epcas5p38fffe5effdcfd2650cad98c25c31335e@epcas5p3.samsung.com>
@ 2017-01-16 6:31 ` Jaehoon Chung
[not found] ` <CGME20170116063141epcas1p3defd18e3c6440d3e55adadd86c920a41@epcas1p3.samsung.com>
` (6 more replies)
0 siblings, 7 replies; 10+ messages in thread
From: Jaehoon Chung @ 2017-01-16 6:31 UTC (permalink / raw)
To: linux-pci
Cc: bhelgaas, krzk, linux-kernel, jingoohan1, javier, kgene,
linux-samsung-soc, cpgs, Jaehoon Chung
Current pci-exynos.c is used for only EXYNOS5440.
It's too complex to support the other Exynos SoCs.
Before supporting the other Exynos SoCs, it needs to clean the codes.
Changelog on V3:
- Splits "PCI: exynos: replace to one register accessor from each accessors"
Changelog on V2:
- Changes the all pointer names as "ep" instead of "exynos_pcie"
Jaehoon Chung (5):
PCI: exynos: Rename all pointer names from "exynos_pcie" to "ep"
PCI: exynos: Replace the *_blk/*_phy/*_elb accessors
PCI: exynos: Remove the unnecessary variables
PCI: exynos: Use the bitops API to operate the bit shifting
PCI: exynos: remove the duplicated codes
drivers/pci/host/pci-exynos.c | 392 +++++++++++++++++++-----------------------
1 file changed, 181 insertions(+), 211 deletions(-)
--
2.10.2
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH V3 1/5] PCI: exynos: Rename all pointer names from "exynos_pcie" to "ep"
[not found] ` <CGME20170116063141epcas1p3defd18e3c6440d3e55adadd86c920a41@epcas1p3.samsung.com>
@ 2017-01-16 6:31 ` Jaehoon Chung
0 siblings, 0 replies; 10+ messages in thread
From: Jaehoon Chung @ 2017-01-16 6:31 UTC (permalink / raw)
To: linux-pci
Cc: bhelgaas, krzk, linux-kernel, jingoohan1, javier, kgene,
linux-samsung-soc, cpgs, Jaehoon Chung
Rename the simple pointer name as "ep" instead of "exynos_pcie".
After applying this patch, it can save the 10 characthers within one
line.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
---
Changelog on V3:
- Split from previous [PATCH V2 1/4]
"PCI: exynos: replace to one register accessor from each accessors"
Changelog on V2:
- Changes the all pointer names as "ep" instead of "exynos_pcie"
drivers/pci/host/pci-exynos.c | 348 +++++++++++++++++++++---------------------
1 file changed, 173 insertions(+), 175 deletions(-)
diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
index f1c544b..2e99ff5 100644
--- a/drivers/pci/host/pci-exynos.c
+++ b/drivers/pci/host/pci-exynos.c
@@ -102,212 +102,210 @@ struct exynos_pcie {
#define PCIE_PHY_TRSV3_PD_TSV (0x1 << 7)
#define PCIE_PHY_TRSV3_LVCC 0x31c
-static void exynos_elb_writel(struct exynos_pcie *exynos_pcie, u32 val, u32 reg)
+static void exynos_elb_writel(struct exynos_pcie *ep, u32 val, u32 reg)
{
- writel(val, exynos_pcie->elbi_base + reg);
+ writel(val, ep->elbi_base + reg);
}
-static u32 exynos_elb_readl(struct exynos_pcie *exynos_pcie, u32 reg)
+static u32 exynos_elb_readl(struct exynos_pcie *ep, u32 reg)
{
- return readl(exynos_pcie->elbi_base + reg);
+ return readl(ep->elbi_base + reg);
}
-static void exynos_phy_writel(struct exynos_pcie *exynos_pcie, u32 val, u32 reg)
+static void exynos_phy_writel(struct exynos_pcie *ep, u32 val, u32 reg)
{
- writel(val, exynos_pcie->phy_base + reg);
+ writel(val, ep->phy_base + reg);
}
-static u32 exynos_phy_readl(struct exynos_pcie *exynos_pcie, u32 reg)
+static u32 exynos_phy_readl(struct exynos_pcie *ep, u32 reg)
{
- return readl(exynos_pcie->phy_base + reg);
+ return readl(ep->phy_base + reg);
}
-static void exynos_blk_writel(struct exynos_pcie *exynos_pcie, u32 val, u32 reg)
+static void exynos_blk_writel(struct exynos_pcie *ep, u32 val, u32 reg)
{
- writel(val, exynos_pcie->block_base + reg);
+ writel(val, ep->block_base + reg);
}
-static u32 exynos_blk_readl(struct exynos_pcie *exynos_pcie, u32 reg)
+static u32 exynos_blk_readl(struct exynos_pcie *ep, u32 reg)
{
- return readl(exynos_pcie->block_base + reg);
+ return readl(ep->block_base + reg);
}
-static void exynos_pcie_sideband_dbi_w_mode(struct exynos_pcie *exynos_pcie,
- bool on)
+static void exynos_pcie_sideband_dbi_w_mode(struct exynos_pcie *ep, bool on)
{
u32 val;
if (on) {
- val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_AWMISC);
+ val = exynos_elb_readl(ep, PCIE_ELBI_SLV_AWMISC);
val |= PCIE_ELBI_SLV_DBI_ENABLE;
- exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_AWMISC);
+ exynos_elb_writel(ep, val, PCIE_ELBI_SLV_AWMISC);
} else {
- val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_AWMISC);
+ val = exynos_elb_readl(ep, PCIE_ELBI_SLV_AWMISC);
val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
- exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_AWMISC);
+ exynos_elb_writel(ep, val, PCIE_ELBI_SLV_AWMISC);
}
}
-static void exynos_pcie_sideband_dbi_r_mode(struct exynos_pcie *exynos_pcie,
- bool on)
+static void exynos_pcie_sideband_dbi_r_mode(struct exynos_pcie *ep, bool on)
{
u32 val;
if (on) {
- val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_ARMISC);
+ val = exynos_elb_readl(ep, PCIE_ELBI_SLV_ARMISC);
val |= PCIE_ELBI_SLV_DBI_ENABLE;
- exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_ARMISC);
+ exynos_elb_writel(ep, val, PCIE_ELBI_SLV_ARMISC);
} else {
- val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_ARMISC);
+ val = exynos_elb_readl(ep, PCIE_ELBI_SLV_ARMISC);
val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
- exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_ARMISC);
+ exynos_elb_writel(ep, val, PCIE_ELBI_SLV_ARMISC);
}
}
-static void exynos_pcie_assert_core_reset(struct exynos_pcie *exynos_pcie)
+static void exynos_pcie_assert_core_reset(struct exynos_pcie *ep)
{
u32 val;
- val = exynos_elb_readl(exynos_pcie, PCIE_CORE_RESET);
+ val = exynos_elb_readl(ep, PCIE_CORE_RESET);
val &= ~PCIE_CORE_RESET_ENABLE;
- exynos_elb_writel(exynos_pcie, val, PCIE_CORE_RESET);
- exynos_elb_writel(exynos_pcie, 0, PCIE_PWR_RESET);
- exynos_elb_writel(exynos_pcie, 0, PCIE_STICKY_RESET);
- exynos_elb_writel(exynos_pcie, 0, PCIE_NONSTICKY_RESET);
+ exynos_elb_writel(ep, val, PCIE_CORE_RESET);
+ exynos_elb_writel(ep, 0, PCIE_PWR_RESET);
+ exynos_elb_writel(ep, 0, PCIE_STICKY_RESET);
+ exynos_elb_writel(ep, 0, PCIE_NONSTICKY_RESET);
}
-static void exynos_pcie_deassert_core_reset(struct exynos_pcie *exynos_pcie)
+static void exynos_pcie_deassert_core_reset(struct exynos_pcie *ep)
{
u32 val;
- val = exynos_elb_readl(exynos_pcie, PCIE_CORE_RESET);
+ val = exynos_elb_readl(ep, PCIE_CORE_RESET);
val |= PCIE_CORE_RESET_ENABLE;
- exynos_elb_writel(exynos_pcie, val, PCIE_CORE_RESET);
- exynos_elb_writel(exynos_pcie, 1, PCIE_STICKY_RESET);
- exynos_elb_writel(exynos_pcie, 1, PCIE_NONSTICKY_RESET);
- exynos_elb_writel(exynos_pcie, 1, PCIE_APP_INIT_RESET);
- exynos_elb_writel(exynos_pcie, 0, PCIE_APP_INIT_RESET);
- exynos_blk_writel(exynos_pcie, 1, PCIE_PHY_MAC_RESET);
+ exynos_elb_writel(ep, val, PCIE_CORE_RESET);
+ exynos_elb_writel(ep, 1, PCIE_STICKY_RESET);
+ exynos_elb_writel(ep, 1, PCIE_NONSTICKY_RESET);
+ exynos_elb_writel(ep, 1, PCIE_APP_INIT_RESET);
+ exynos_elb_writel(ep, 0, PCIE_APP_INIT_RESET);
+ exynos_blk_writel(ep, 1, PCIE_PHY_MAC_RESET);
}
-static void exynos_pcie_assert_phy_reset(struct exynos_pcie *exynos_pcie)
+static void exynos_pcie_assert_phy_reset(struct exynos_pcie *ep)
{
- exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_MAC_RESET);
- exynos_blk_writel(exynos_pcie, 1, PCIE_PHY_GLOBAL_RESET);
+ exynos_blk_writel(ep, 0, PCIE_PHY_MAC_RESET);
+ exynos_blk_writel(ep, 1, PCIE_PHY_GLOBAL_RESET);
}
-static void exynos_pcie_deassert_phy_reset(struct exynos_pcie *exynos_pcie)
+static void exynos_pcie_deassert_phy_reset(struct exynos_pcie *ep)
{
- exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_GLOBAL_RESET);
- exynos_elb_writel(exynos_pcie, 1, PCIE_PWR_RESET);
- exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_COMMON_RESET);
- exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_CMN_REG);
- exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_TRSVREG_RESET);
- exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_TRSV_RESET);
+ exynos_blk_writel(ep, 0, PCIE_PHY_GLOBAL_RESET);
+ exynos_elb_writel(ep, 1, PCIE_PWR_RESET);
+ exynos_blk_writel(ep, 0, PCIE_PHY_COMMON_RESET);
+ exynos_blk_writel(ep, 0, PCIE_PHY_CMN_REG);
+ exynos_blk_writel(ep, 0, PCIE_PHY_TRSVREG_RESET);
+ exynos_blk_writel(ep, 0, PCIE_PHY_TRSV_RESET);
}
-static void exynos_pcie_power_on_phy(struct exynos_pcie *exynos_pcie)
+static void exynos_pcie_power_on_phy(struct exynos_pcie *ep)
{
u32 val;
- val = exynos_phy_readl(exynos_pcie, PCIE_PHY_COMMON_POWER);
+ val = exynos_phy_readl(ep, PCIE_PHY_COMMON_POWER);
val &= ~PCIE_PHY_COMMON_PD_CMN;
- exynos_phy_writel(exynos_pcie, val, PCIE_PHY_COMMON_POWER);
+ exynos_phy_writel(ep, val, PCIE_PHY_COMMON_POWER);
- val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV0_POWER);
+ val = exynos_phy_readl(ep, PCIE_PHY_TRSV0_POWER);
val &= ~PCIE_PHY_TRSV0_PD_TSV;
- exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV0_POWER);
+ exynos_phy_writel(ep, val, PCIE_PHY_TRSV0_POWER);
- val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV1_POWER);
+ val = exynos_phy_readl(ep, PCIE_PHY_TRSV1_POWER);
val &= ~PCIE_PHY_TRSV1_PD_TSV;
- exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV1_POWER);
+ exynos_phy_writel(ep, val, PCIE_PHY_TRSV1_POWER);
- val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV2_POWER);
+ val = exynos_phy_readl(ep, PCIE_PHY_TRSV2_POWER);
val &= ~PCIE_PHY_TRSV2_PD_TSV;
- exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV2_POWER);
+ exynos_phy_writel(ep, val, PCIE_PHY_TRSV2_POWER);
- val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV3_POWER);
+ val = exynos_phy_readl(ep, PCIE_PHY_TRSV3_POWER);
val &= ~PCIE_PHY_TRSV3_PD_TSV;
- exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV3_POWER);
+ exynos_phy_writel(ep, val, PCIE_PHY_TRSV3_POWER);
}
-static void exynos_pcie_power_off_phy(struct exynos_pcie *exynos_pcie)
+static void exynos_pcie_power_off_phy(struct exynos_pcie *ep)
{
u32 val;
- val = exynos_phy_readl(exynos_pcie, PCIE_PHY_COMMON_POWER);
+ val = exynos_phy_readl(ep, PCIE_PHY_COMMON_POWER);
val |= PCIE_PHY_COMMON_PD_CMN;
- exynos_phy_writel(exynos_pcie, val, PCIE_PHY_COMMON_POWER);
+ exynos_phy_writel(ep, val, PCIE_PHY_COMMON_POWER);
- val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV0_POWER);
+ val = exynos_phy_readl(ep, PCIE_PHY_TRSV0_POWER);
val |= PCIE_PHY_TRSV0_PD_TSV;
- exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV0_POWER);
+ exynos_phy_writel(ep, val, PCIE_PHY_TRSV0_POWER);
- val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV1_POWER);
+ val = exynos_phy_readl(ep, PCIE_PHY_TRSV1_POWER);
val |= PCIE_PHY_TRSV1_PD_TSV;
- exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV1_POWER);
+ exynos_phy_writel(ep, val, PCIE_PHY_TRSV1_POWER);
- val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV2_POWER);
+ val = exynos_phy_readl(ep, PCIE_PHY_TRSV2_POWER);
val |= PCIE_PHY_TRSV2_PD_TSV;
- exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV2_POWER);
+ exynos_phy_writel(ep, val, PCIE_PHY_TRSV2_POWER);
- val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV3_POWER);
+ val = exynos_phy_readl(ep, PCIE_PHY_TRSV3_POWER);
val |= PCIE_PHY_TRSV3_PD_TSV;
- exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV3_POWER);
+ exynos_phy_writel(ep, val, PCIE_PHY_TRSV3_POWER);
}
-static void exynos_pcie_init_phy(struct exynos_pcie *exynos_pcie)
+static void exynos_pcie_init_phy(struct exynos_pcie *ep)
{
/* DCC feedback control off */
- exynos_phy_writel(exynos_pcie, 0x29, PCIE_PHY_DCC_FEEDBACK);
+ exynos_phy_writel(ep, 0x29, PCIE_PHY_DCC_FEEDBACK);
/* set TX/RX impedance */
- exynos_phy_writel(exynos_pcie, 0xd5, PCIE_PHY_IMPEDANCE);
+ exynos_phy_writel(ep, 0xd5, PCIE_PHY_IMPEDANCE);
/* set 50Mhz PHY clock */
- exynos_phy_writel(exynos_pcie, 0x14, PCIE_PHY_PLL_DIV_0);
- exynos_phy_writel(exynos_pcie, 0x12, PCIE_PHY_PLL_DIV_1);
+ exynos_phy_writel(ep, 0x14, PCIE_PHY_PLL_DIV_0);
+ exynos_phy_writel(ep, 0x12, PCIE_PHY_PLL_DIV_1);
/* set TX Differential output for lane 0 */
- exynos_phy_writel(exynos_pcie, 0x7f, PCIE_PHY_TRSV0_DRV_LVL);
+ exynos_phy_writel(ep, 0x7f, PCIE_PHY_TRSV0_DRV_LVL);
/* set TX Pre-emphasis Level Control for lane 0 to minimum */
- exynos_phy_writel(exynos_pcie, 0x0, PCIE_PHY_TRSV0_EMP_LVL);
+ exynos_phy_writel(ep, 0x0, PCIE_PHY_TRSV0_EMP_LVL);
/* set RX clock and data recovery bandwidth */
- exynos_phy_writel(exynos_pcie, 0xe7, PCIE_PHY_PLL_BIAS);
- exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV0_RXCDR);
- exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV1_RXCDR);
- exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV2_RXCDR);
- exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV3_RXCDR);
+ exynos_phy_writel(ep, 0xe7, PCIE_PHY_PLL_BIAS);
+ exynos_phy_writel(ep, 0x82, PCIE_PHY_TRSV0_RXCDR);
+ exynos_phy_writel(ep, 0x82, PCIE_PHY_TRSV1_RXCDR);
+ exynos_phy_writel(ep, 0x82, PCIE_PHY_TRSV2_RXCDR);
+ exynos_phy_writel(ep, 0x82, PCIE_PHY_TRSV3_RXCDR);
/* change TX Pre-emphasis Level Control for lanes */
- exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV0_EMP_LVL);
- exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV1_EMP_LVL);
- exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV2_EMP_LVL);
- exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV3_EMP_LVL);
+ exynos_phy_writel(ep, 0x39, PCIE_PHY_TRSV0_EMP_LVL);
+ exynos_phy_writel(ep, 0x39, PCIE_PHY_TRSV1_EMP_LVL);
+ exynos_phy_writel(ep, 0x39, PCIE_PHY_TRSV2_EMP_LVL);
+ exynos_phy_writel(ep, 0x39, PCIE_PHY_TRSV3_EMP_LVL);
/* set LVCC */
- exynos_phy_writel(exynos_pcie, 0x20, PCIE_PHY_TRSV0_LVCC);
- exynos_phy_writel(exynos_pcie, 0xa0, PCIE_PHY_TRSV1_LVCC);
- exynos_phy_writel(exynos_pcie, 0xa0, PCIE_PHY_TRSV2_LVCC);
- exynos_phy_writel(exynos_pcie, 0xa0, PCIE_PHY_TRSV3_LVCC);
+ exynos_phy_writel(ep, 0x20, PCIE_PHY_TRSV0_LVCC);
+ exynos_phy_writel(ep, 0xa0, PCIE_PHY_TRSV1_LVCC);
+ exynos_phy_writel(ep, 0xa0, PCIE_PHY_TRSV2_LVCC);
+ exynos_phy_writel(ep, 0xa0, PCIE_PHY_TRSV3_LVCC);
}
-static void exynos_pcie_assert_reset(struct exynos_pcie *exynos_pcie)
+static void exynos_pcie_assert_reset(struct exynos_pcie *ep)
{
- struct pcie_port *pp = &exynos_pcie->pp;
+ struct pcie_port *pp = &ep->pp;
struct device *dev = pp->dev;
- if (exynos_pcie->reset_gpio >= 0)
- devm_gpio_request_one(dev, exynos_pcie->reset_gpio,
+ if (ep->reset_gpio >= 0)
+ devm_gpio_request_one(dev, ep->reset_gpio,
GPIOF_OUT_INIT_HIGH, "RESET");
}
-static int exynos_pcie_establish_link(struct exynos_pcie *exynos_pcie)
+static int exynos_pcie_establish_link(struct exynos_pcie *ep)
{
- struct pcie_port *pp = &exynos_pcie->pp;
+ struct pcie_port *pp = &ep->pp;
struct device *dev = pp->dev;
u32 val;
@@ -316,142 +314,142 @@ static int exynos_pcie_establish_link(struct exynos_pcie *exynos_pcie)
return 0;
}
- exynos_pcie_assert_core_reset(exynos_pcie);
- exynos_pcie_assert_phy_reset(exynos_pcie);
- exynos_pcie_deassert_phy_reset(exynos_pcie);
- exynos_pcie_power_on_phy(exynos_pcie);
- exynos_pcie_init_phy(exynos_pcie);
+ exynos_pcie_assert_core_reset(ep);
+ exynos_pcie_assert_phy_reset(ep);
+ exynos_pcie_deassert_phy_reset(ep);
+ exynos_pcie_power_on_phy(ep);
+ exynos_pcie_init_phy(ep);
/* pulse for common reset */
- exynos_blk_writel(exynos_pcie, 1, PCIE_PHY_COMMON_RESET);
+ exynos_blk_writel(ep, 1, PCIE_PHY_COMMON_RESET);
udelay(500);
- exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_COMMON_RESET);
+ exynos_blk_writel(ep, 0, PCIE_PHY_COMMON_RESET);
- exynos_pcie_deassert_core_reset(exynos_pcie);
+ exynos_pcie_deassert_core_reset(ep);
dw_pcie_setup_rc(pp);
- exynos_pcie_assert_reset(exynos_pcie);
+ exynos_pcie_assert_reset(ep);
/* assert LTSSM enable */
- exynos_elb_writel(exynos_pcie, PCIE_ELBI_LTSSM_ENABLE,
+ exynos_elb_writel(ep, PCIE_ELBI_LTSSM_ENABLE,
PCIE_APP_LTSSM_ENABLE);
/* check if the link is up or not */
if (!dw_pcie_wait_for_link(pp))
return 0;
- while (exynos_phy_readl(exynos_pcie, PCIE_PHY_PLL_LOCKED) == 0) {
- val = exynos_blk_readl(exynos_pcie, PCIE_PHY_PLL_LOCKED);
+ while (exynos_phy_readl(ep, PCIE_PHY_PLL_LOCKED) == 0) {
+ val = exynos_blk_readl(ep, PCIE_PHY_PLL_LOCKED);
dev_info(dev, "PLL Locked: 0x%x\n", val);
}
- exynos_pcie_power_off_phy(exynos_pcie);
+ exynos_pcie_power_off_phy(ep);
return -ETIMEDOUT;
}
-static void exynos_pcie_clear_irq_pulse(struct exynos_pcie *exynos_pcie)
+static void exynos_pcie_clear_irq_pulse(struct exynos_pcie *ep)
{
u32 val;
- val = exynos_elb_readl(exynos_pcie, PCIE_IRQ_PULSE);
- exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_PULSE);
+ val = exynos_elb_readl(ep, PCIE_IRQ_PULSE);
+ exynos_elb_writel(ep, val, PCIE_IRQ_PULSE);
}
-static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *exynos_pcie)
+static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *ep)
{
u32 val;
/* enable INTX interrupt */
val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT |
IRQ_INTC_ASSERT | IRQ_INTD_ASSERT;
- exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_EN_PULSE);
+ exynos_elb_writel(ep, val, PCIE_IRQ_EN_PULSE);
}
static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg)
{
- struct exynos_pcie *exynos_pcie = arg;
+ struct exynos_pcie *ep = arg;
- exynos_pcie_clear_irq_pulse(exynos_pcie);
+ exynos_pcie_clear_irq_pulse(ep);
return IRQ_HANDLED;
}
static irqreturn_t exynos_pcie_msi_irq_handler(int irq, void *arg)
{
- struct exynos_pcie *exynos_pcie = arg;
- struct pcie_port *pp = &exynos_pcie->pp;
+ struct exynos_pcie *ep = arg;
+ struct pcie_port *pp = &ep->pp;
return dw_handle_msi_irq(pp);
}
-static void exynos_pcie_msi_init(struct exynos_pcie *exynos_pcie)
+static void exynos_pcie_msi_init(struct exynos_pcie *ep)
{
- struct pcie_port *pp = &exynos_pcie->pp;
+ struct pcie_port *pp = &ep->pp;
u32 val;
dw_pcie_msi_init(pp);
/* enable MSI interrupt */
- val = exynos_elb_readl(exynos_pcie, PCIE_IRQ_EN_LEVEL);
+ val = exynos_elb_readl(ep, PCIE_IRQ_EN_LEVEL);
val |= IRQ_MSI_ENABLE;
- exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_EN_LEVEL);
+ exynos_elb_writel(ep, val, PCIE_IRQ_EN_LEVEL);
}
-static void exynos_pcie_enable_interrupts(struct exynos_pcie *exynos_pcie)
+static void exynos_pcie_enable_interrupts(struct exynos_pcie *ep)
{
- exynos_pcie_enable_irq_pulse(exynos_pcie);
+ exynos_pcie_enable_irq_pulse(ep);
if (IS_ENABLED(CONFIG_PCI_MSI))
- exynos_pcie_msi_init(exynos_pcie);
+ exynos_pcie_msi_init(ep);
}
static u32 exynos_pcie_readl_rc(struct pcie_port *pp, u32 reg)
{
- struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
+ struct exynos_pcie *ep = to_exynos_pcie(pp);
u32 val;
- exynos_pcie_sideband_dbi_r_mode(exynos_pcie, true);
+ exynos_pcie_sideband_dbi_r_mode(ep, true);
val = readl(pp->dbi_base + reg);
- exynos_pcie_sideband_dbi_r_mode(exynos_pcie, false);
+ exynos_pcie_sideband_dbi_r_mode(ep, false);
return val;
}
static void exynos_pcie_writel_rc(struct pcie_port *pp, u32 reg, u32 val)
{
- struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
+ struct exynos_pcie *ep = to_exynos_pcie(pp);
- exynos_pcie_sideband_dbi_w_mode(exynos_pcie, true);
+ exynos_pcie_sideband_dbi_w_mode(ep, true);
writel(val, pp->dbi_base + reg);
- exynos_pcie_sideband_dbi_w_mode(exynos_pcie, false);
+ exynos_pcie_sideband_dbi_w_mode(ep, false);
}
static int exynos_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
u32 *val)
{
- struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
+ struct exynos_pcie *ep = to_exynos_pcie(pp);
int ret;
- exynos_pcie_sideband_dbi_r_mode(exynos_pcie, true);
+ exynos_pcie_sideband_dbi_r_mode(ep, true);
ret = dw_pcie_cfg_read(pp->dbi_base + where, size, val);
- exynos_pcie_sideband_dbi_r_mode(exynos_pcie, false);
+ exynos_pcie_sideband_dbi_r_mode(ep, false);
return ret;
}
static int exynos_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
u32 val)
{
- struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
+ struct exynos_pcie *ep = to_exynos_pcie(pp);
int ret;
- exynos_pcie_sideband_dbi_w_mode(exynos_pcie, true);
+ exynos_pcie_sideband_dbi_w_mode(ep, true);
ret = dw_pcie_cfg_write(pp->dbi_base + where, size, val);
- exynos_pcie_sideband_dbi_w_mode(exynos_pcie, false);
+ exynos_pcie_sideband_dbi_w_mode(ep, false);
return ret;
}
static int exynos_pcie_link_up(struct pcie_port *pp)
{
- struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
+ struct exynos_pcie *ep = to_exynos_pcie(pp);
u32 val;
- val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_RDLH_LINKUP);
+ val = exynos_elb_readl(ep, PCIE_ELBI_RDLH_LINKUP);
if (val == PCIE_ELBI_LTSSM_ENABLE)
return 1;
@@ -460,10 +458,10 @@ static int exynos_pcie_link_up(struct pcie_port *pp)
static void exynos_pcie_host_init(struct pcie_port *pp)
{
- struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
+ struct exynos_pcie *ep = to_exynos_pcie(pp);
- exynos_pcie_establish_link(exynos_pcie);
- exynos_pcie_enable_interrupts(exynos_pcie);
+ exynos_pcie_establish_link(ep);
+ exynos_pcie_enable_interrupts(ep);
}
static struct pcie_host_ops exynos_pcie_host_ops = {
@@ -475,10 +473,10 @@ static struct pcie_host_ops exynos_pcie_host_ops = {
.host_init = exynos_pcie_host_init,
};
-static int __init exynos_add_pcie_port(struct exynos_pcie *exynos_pcie,
+static int __init exynos_add_pcie_port(struct exynos_pcie *ep,
struct platform_device *pdev)
{
- struct pcie_port *pp = &exynos_pcie->pp;
+ struct pcie_port *pp = &ep->pp;
struct device *dev = pp->dev;
int ret;
@@ -488,7 +486,7 @@ static int __init exynos_add_pcie_port(struct exynos_pcie *exynos_pcie,
return -ENODEV;
}
ret = devm_request_irq(dev, pp->irq, exynos_pcie_irq_handler,
- IRQF_SHARED, "exynos-pcie", exynos_pcie);
+ IRQF_SHARED, "exynos-pcie", ep);
if (ret) {
dev_err(dev, "failed to request irq\n");
return ret;
@@ -504,7 +502,7 @@ static int __init exynos_add_pcie_port(struct exynos_pcie *exynos_pcie,
ret = devm_request_irq(dev, pp->msi_irq,
exynos_pcie_msi_irq_handler,
IRQF_SHARED | IRQF_NO_THREAD,
- "exynos-pcie", exynos_pcie);
+ "exynos-pcie", ep);
if (ret) {
dev_err(dev, "failed to request msi irq\n");
return ret;
@@ -526,7 +524,7 @@ static int __init exynos_add_pcie_port(struct exynos_pcie *exynos_pcie,
static int __init exynos_pcie_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
- struct exynos_pcie *exynos_pcie;
+ struct exynos_pcie *ep;
struct pcie_port *pp;
struct device_node *np = dev->of_node;
struct resource *elbi_base;
@@ -534,75 +532,75 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
struct resource *block_base;
int ret;
- exynos_pcie = devm_kzalloc(dev, sizeof(*exynos_pcie), GFP_KERNEL);
- if (!exynos_pcie)
+ ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
+ if (!ep)
return -ENOMEM;
- pp = &exynos_pcie->pp;
+ pp = &ep->pp;
pp->dev = dev;
- exynos_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
+ ep->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
- exynos_pcie->clk = devm_clk_get(dev, "pcie");
- if (IS_ERR(exynos_pcie->clk)) {
+ ep->clk = devm_clk_get(dev, "pcie");
+ if (IS_ERR(ep->clk)) {
dev_err(dev, "Failed to get pcie rc clock\n");
- return PTR_ERR(exynos_pcie->clk);
+ return PTR_ERR(ep->clk);
}
- ret = clk_prepare_enable(exynos_pcie->clk);
+ ret = clk_prepare_enable(ep->clk);
if (ret)
return ret;
- exynos_pcie->bus_clk = devm_clk_get(dev, "pcie_bus");
- if (IS_ERR(exynos_pcie->bus_clk)) {
+ ep->bus_clk = devm_clk_get(dev, "pcie_bus");
+ if (IS_ERR(ep->bus_clk)) {
dev_err(dev, "Failed to get pcie bus clock\n");
- ret = PTR_ERR(exynos_pcie->bus_clk);
+ ret = PTR_ERR(ep->bus_clk);
goto fail_clk;
}
- ret = clk_prepare_enable(exynos_pcie->bus_clk);
+ ret = clk_prepare_enable(ep->bus_clk);
if (ret)
goto fail_clk;
elbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- exynos_pcie->elbi_base = devm_ioremap_resource(dev, elbi_base);
- if (IS_ERR(exynos_pcie->elbi_base)) {
- ret = PTR_ERR(exynos_pcie->elbi_base);
+ ep->elbi_base = devm_ioremap_resource(dev, elbi_base);
+ if (IS_ERR(ep->elbi_base)) {
+ ret = PTR_ERR(ep->elbi_base);
goto fail_bus_clk;
}
phy_base = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- exynos_pcie->phy_base = devm_ioremap_resource(dev, phy_base);
- if (IS_ERR(exynos_pcie->phy_base)) {
- ret = PTR_ERR(exynos_pcie->phy_base);
+ ep->phy_base = devm_ioremap_resource(dev, phy_base);
+ if (IS_ERR(ep->phy_base)) {
+ ret = PTR_ERR(ep->phy_base);
goto fail_bus_clk;
}
block_base = platform_get_resource(pdev, IORESOURCE_MEM, 2);
- exynos_pcie->block_base = devm_ioremap_resource(dev, block_base);
- if (IS_ERR(exynos_pcie->block_base)) {
- ret = PTR_ERR(exynos_pcie->block_base);
+ ep->block_base = devm_ioremap_resource(dev, block_base);
+ if (IS_ERR(ep->block_base)) {
+ ret = PTR_ERR(ep->block_base);
goto fail_bus_clk;
}
- ret = exynos_add_pcie_port(exynos_pcie, pdev);
+ ret = exynos_add_pcie_port(ep, pdev);
if (ret < 0)
goto fail_bus_clk;
- platform_set_drvdata(pdev, exynos_pcie);
+ platform_set_drvdata(pdev, ep);
return 0;
fail_bus_clk:
- clk_disable_unprepare(exynos_pcie->bus_clk);
+ clk_disable_unprepare(ep->bus_clk);
fail_clk:
- clk_disable_unprepare(exynos_pcie->clk);
+ clk_disable_unprepare(ep->clk);
return ret;
}
static int __exit exynos_pcie_remove(struct platform_device *pdev)
{
- struct exynos_pcie *exynos_pcie = platform_get_drvdata(pdev);
+ struct exynos_pcie *ep = platform_get_drvdata(pdev);
- clk_disable_unprepare(exynos_pcie->bus_clk);
- clk_disable_unprepare(exynos_pcie->clk);
+ clk_disable_unprepare(ep->bus_clk);
+ clk_disable_unprepare(ep->clk);
return 0;
}
--
2.10.2
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH V3 2/5] PCI: exynos: Replace the *_blk/*_phy/*_elb accessors
[not found] ` <CGME20170116063141epcas5p30c3b6fa57b7ef053dbe3755e1f44fd8c@epcas5p3.samsung.com>
@ 2017-01-16 6:31 ` Jaehoon Chung
0 siblings, 0 replies; 10+ messages in thread
From: Jaehoon Chung @ 2017-01-16 6:31 UTC (permalink / raw)
To: linux-pci
Cc: bhelgaas, krzk, linux-kernel, jingoohan1, javier, kgene,
linux-samsung-soc, cpgs, Jaehoon Chung
There is no reason to maintain *_blk/phy/elbi_* as register accessors.
It can be replaced to one accessor for maintaining more easier.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
---
Changelog on V3:
- Split from previous [PATCH V2 1/4]
"PCI: exynos: replace to one register accessor from each accessors"
Changelog on V2:
- Changes the all pointer names as "ep" instead of "exynos_pcie"
drivers/pci/host/pci-exynos.c | 184 +++++++++++++++++++-----------------------
1 file changed, 82 insertions(+), 102 deletions(-)
diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
index 2e99ff5..166881a 100644
--- a/drivers/pci/host/pci-exynos.c
+++ b/drivers/pci/host/pci-exynos.c
@@ -102,34 +102,14 @@ struct exynos_pcie {
#define PCIE_PHY_TRSV3_PD_TSV (0x1 << 7)
#define PCIE_PHY_TRSV3_LVCC 0x31c
-static void exynos_elb_writel(struct exynos_pcie *ep, u32 val, u32 reg)
+static void exynos_pcie_writel(void __iomem *base, u32 val, u32 reg)
{
- writel(val, ep->elbi_base + reg);
+ writel(val, base + reg);
}
-static u32 exynos_elb_readl(struct exynos_pcie *ep, u32 reg)
+static u32 exynos_pcie_readl(void __iomem *base, u32 reg)
{
- return readl(ep->elbi_base + reg);
-}
-
-static void exynos_phy_writel(struct exynos_pcie *ep, u32 val, u32 reg)
-{
- writel(val, ep->phy_base + reg);
-}
-
-static u32 exynos_phy_readl(struct exynos_pcie *ep, u32 reg)
-{
- return readl(ep->phy_base + reg);
-}
-
-static void exynos_blk_writel(struct exynos_pcie *ep, u32 val, u32 reg)
-{
- writel(val, ep->block_base + reg);
-}
-
-static u32 exynos_blk_readl(struct exynos_pcie *ep, u32 reg)
-{
- return readl(ep->block_base + reg);
+ return readl(base + reg);
}
static void exynos_pcie_sideband_dbi_w_mode(struct exynos_pcie *ep, bool on)
@@ -137,13 +117,13 @@ static void exynos_pcie_sideband_dbi_w_mode(struct exynos_pcie *ep, bool on)
u32 val;
if (on) {
- val = exynos_elb_readl(ep, PCIE_ELBI_SLV_AWMISC);
+ val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_AWMISC);
val |= PCIE_ELBI_SLV_DBI_ENABLE;
- exynos_elb_writel(ep, val, PCIE_ELBI_SLV_AWMISC);
+ exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_AWMISC);
} else {
- val = exynos_elb_readl(ep, PCIE_ELBI_SLV_AWMISC);
+ val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_AWMISC);
val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
- exynos_elb_writel(ep, val, PCIE_ELBI_SLV_AWMISC);
+ exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_AWMISC);
}
}
@@ -152,13 +132,13 @@ static void exynos_pcie_sideband_dbi_r_mode(struct exynos_pcie *ep, bool on)
u32 val;
if (on) {
- val = exynos_elb_readl(ep, PCIE_ELBI_SLV_ARMISC);
+ val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_ARMISC);
val |= PCIE_ELBI_SLV_DBI_ENABLE;
- exynos_elb_writel(ep, val, PCIE_ELBI_SLV_ARMISC);
+ exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_ARMISC);
} else {
- val = exynos_elb_readl(ep, PCIE_ELBI_SLV_ARMISC);
+ val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_ARMISC);
val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
- exynos_elb_writel(ep, val, PCIE_ELBI_SLV_ARMISC);
+ exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_ARMISC);
}
}
@@ -166,131 +146,131 @@ static void exynos_pcie_assert_core_reset(struct exynos_pcie *ep)
{
u32 val;
- val = exynos_elb_readl(ep, PCIE_CORE_RESET);
+ val = exynos_pcie_readl(ep->elbi_base, PCIE_CORE_RESET);
val &= ~PCIE_CORE_RESET_ENABLE;
- exynos_elb_writel(ep, val, PCIE_CORE_RESET);
- exynos_elb_writel(ep, 0, PCIE_PWR_RESET);
- exynos_elb_writel(ep, 0, PCIE_STICKY_RESET);
- exynos_elb_writel(ep, 0, PCIE_NONSTICKY_RESET);
+ exynos_pcie_writel(ep->elbi_base, val, PCIE_CORE_RESET);
+ exynos_pcie_writel(ep->elbi_base, 0, PCIE_PWR_RESET);
+ exynos_pcie_writel(ep->elbi_base, 0, PCIE_STICKY_RESET);
+ exynos_pcie_writel(ep->elbi_base, 0, PCIE_NONSTICKY_RESET);
}
static void exynos_pcie_deassert_core_reset(struct exynos_pcie *ep)
{
u32 val;
- val = exynos_elb_readl(ep, PCIE_CORE_RESET);
+ val = exynos_pcie_readl(ep->elbi_base, PCIE_CORE_RESET);
val |= PCIE_CORE_RESET_ENABLE;
- exynos_elb_writel(ep, val, PCIE_CORE_RESET);
- exynos_elb_writel(ep, 1, PCIE_STICKY_RESET);
- exynos_elb_writel(ep, 1, PCIE_NONSTICKY_RESET);
- exynos_elb_writel(ep, 1, PCIE_APP_INIT_RESET);
- exynos_elb_writel(ep, 0, PCIE_APP_INIT_RESET);
- exynos_blk_writel(ep, 1, PCIE_PHY_MAC_RESET);
+ exynos_pcie_writel(ep->elbi_base, val, PCIE_CORE_RESET);
+ exynos_pcie_writel(ep->elbi_base, 1, PCIE_STICKY_RESET);
+ exynos_pcie_writel(ep->elbi_base, 1, PCIE_NONSTICKY_RESET);
+ exynos_pcie_writel(ep->elbi_base, 1, PCIE_APP_INIT_RESET);
+ exynos_pcie_writel(ep->elbi_base, 0, PCIE_APP_INIT_RESET);
+ exynos_pcie_writel(ep->block_base, 1, PCIE_PHY_MAC_RESET);
}
static void exynos_pcie_assert_phy_reset(struct exynos_pcie *ep)
{
- exynos_blk_writel(ep, 0, PCIE_PHY_MAC_RESET);
- exynos_blk_writel(ep, 1, PCIE_PHY_GLOBAL_RESET);
+ exynos_pcie_writel(ep->block_base, 0, PCIE_PHY_MAC_RESET);
+ exynos_pcie_writel(ep->block_base, 1, PCIE_PHY_GLOBAL_RESET);
}
static void exynos_pcie_deassert_phy_reset(struct exynos_pcie *ep)
{
- exynos_blk_writel(ep, 0, PCIE_PHY_GLOBAL_RESET);
- exynos_elb_writel(ep, 1, PCIE_PWR_RESET);
- exynos_blk_writel(ep, 0, PCIE_PHY_COMMON_RESET);
- exynos_blk_writel(ep, 0, PCIE_PHY_CMN_REG);
- exynos_blk_writel(ep, 0, PCIE_PHY_TRSVREG_RESET);
- exynos_blk_writel(ep, 0, PCIE_PHY_TRSV_RESET);
+ exynos_pcie_writel(ep->block_base, 0, PCIE_PHY_GLOBAL_RESET);
+ exynos_pcie_writel(ep->elbi_base, 1, PCIE_PWR_RESET);
+ exynos_pcie_writel(ep->block_base, 0, PCIE_PHY_COMMON_RESET);
+ exynos_pcie_writel(ep->block_base, 0, PCIE_PHY_CMN_REG);
+ exynos_pcie_writel(ep->block_base, 0, PCIE_PHY_TRSVREG_RESET);
+ exynos_pcie_writel(ep->block_base, 0, PCIE_PHY_TRSV_RESET);
}
static void exynos_pcie_power_on_phy(struct exynos_pcie *ep)
{
u32 val;
- val = exynos_phy_readl(ep, PCIE_PHY_COMMON_POWER);
+ val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_COMMON_POWER);
val &= ~PCIE_PHY_COMMON_PD_CMN;
- exynos_phy_writel(ep, val, PCIE_PHY_COMMON_POWER);
+ exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER);
- val = exynos_phy_readl(ep, PCIE_PHY_TRSV0_POWER);
+ val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER);
val &= ~PCIE_PHY_TRSV0_PD_TSV;
- exynos_phy_writel(ep, val, PCIE_PHY_TRSV0_POWER);
+ exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER);
- val = exynos_phy_readl(ep, PCIE_PHY_TRSV1_POWER);
+ val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER);
val &= ~PCIE_PHY_TRSV1_PD_TSV;
- exynos_phy_writel(ep, val, PCIE_PHY_TRSV1_POWER);
+ exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER);
- val = exynos_phy_readl(ep, PCIE_PHY_TRSV2_POWER);
+ val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER);
val &= ~PCIE_PHY_TRSV2_PD_TSV;
- exynos_phy_writel(ep, val, PCIE_PHY_TRSV2_POWER);
+ exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER);
- val = exynos_phy_readl(ep, PCIE_PHY_TRSV3_POWER);
+ val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER);
val &= ~PCIE_PHY_TRSV3_PD_TSV;
- exynos_phy_writel(ep, val, PCIE_PHY_TRSV3_POWER);
+ exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER);
}
static void exynos_pcie_power_off_phy(struct exynos_pcie *ep)
{
u32 val;
- val = exynos_phy_readl(ep, PCIE_PHY_COMMON_POWER);
+ val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_COMMON_POWER);
val |= PCIE_PHY_COMMON_PD_CMN;
- exynos_phy_writel(ep, val, PCIE_PHY_COMMON_POWER);
+ exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER);
- val = exynos_phy_readl(ep, PCIE_PHY_TRSV0_POWER);
+ val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER);
val |= PCIE_PHY_TRSV0_PD_TSV;
- exynos_phy_writel(ep, val, PCIE_PHY_TRSV0_POWER);
+ exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER);
- val = exynos_phy_readl(ep, PCIE_PHY_TRSV1_POWER);
+ val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER);
val |= PCIE_PHY_TRSV1_PD_TSV;
- exynos_phy_writel(ep, val, PCIE_PHY_TRSV1_POWER);
+ exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER);
- val = exynos_phy_readl(ep, PCIE_PHY_TRSV2_POWER);
+ val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER);
val |= PCIE_PHY_TRSV2_PD_TSV;
- exynos_phy_writel(ep, val, PCIE_PHY_TRSV2_POWER);
+ exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER);
- val = exynos_phy_readl(ep, PCIE_PHY_TRSV3_POWER);
+ val = exynos_pcie_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER);
val |= PCIE_PHY_TRSV3_PD_TSV;
- exynos_phy_writel(ep, val, PCIE_PHY_TRSV3_POWER);
+ exynos_pcie_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER);
}
static void exynos_pcie_init_phy(struct exynos_pcie *ep)
{
/* DCC feedback control off */
- exynos_phy_writel(ep, 0x29, PCIE_PHY_DCC_FEEDBACK);
+ exynos_pcie_writel(ep->phy_base, 0x29, PCIE_PHY_DCC_FEEDBACK);
/* set TX/RX impedance */
- exynos_phy_writel(ep, 0xd5, PCIE_PHY_IMPEDANCE);
+ exynos_pcie_writel(ep->phy_base, 0xd5, PCIE_PHY_IMPEDANCE);
/* set 50Mhz PHY clock */
- exynos_phy_writel(ep, 0x14, PCIE_PHY_PLL_DIV_0);
- exynos_phy_writel(ep, 0x12, PCIE_PHY_PLL_DIV_1);
+ exynos_pcie_writel(ep->phy_base, 0x14, PCIE_PHY_PLL_DIV_0);
+ exynos_pcie_writel(ep->phy_base, 0x12, PCIE_PHY_PLL_DIV_1);
/* set TX Differential output for lane 0 */
- exynos_phy_writel(ep, 0x7f, PCIE_PHY_TRSV0_DRV_LVL);
+ exynos_pcie_writel(ep->phy_base, 0x7f, PCIE_PHY_TRSV0_DRV_LVL);
/* set TX Pre-emphasis Level Control for lane 0 to minimum */
- exynos_phy_writel(ep, 0x0, PCIE_PHY_TRSV0_EMP_LVL);
+ exynos_pcie_writel(ep->phy_base, 0x0, PCIE_PHY_TRSV0_EMP_LVL);
/* set RX clock and data recovery bandwidth */
- exynos_phy_writel(ep, 0xe7, PCIE_PHY_PLL_BIAS);
- exynos_phy_writel(ep, 0x82, PCIE_PHY_TRSV0_RXCDR);
- exynos_phy_writel(ep, 0x82, PCIE_PHY_TRSV1_RXCDR);
- exynos_phy_writel(ep, 0x82, PCIE_PHY_TRSV2_RXCDR);
- exynos_phy_writel(ep, 0x82, PCIE_PHY_TRSV3_RXCDR);
+ exynos_pcie_writel(ep->phy_base, 0xe7, PCIE_PHY_PLL_BIAS);
+ exynos_pcie_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV0_RXCDR);
+ exynos_pcie_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV1_RXCDR);
+ exynos_pcie_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV2_RXCDR);
+ exynos_pcie_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV3_RXCDR);
/* change TX Pre-emphasis Level Control for lanes */
- exynos_phy_writel(ep, 0x39, PCIE_PHY_TRSV0_EMP_LVL);
- exynos_phy_writel(ep, 0x39, PCIE_PHY_TRSV1_EMP_LVL);
- exynos_phy_writel(ep, 0x39, PCIE_PHY_TRSV2_EMP_LVL);
- exynos_phy_writel(ep, 0x39, PCIE_PHY_TRSV3_EMP_LVL);
+ exynos_pcie_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV0_EMP_LVL);
+ exynos_pcie_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV1_EMP_LVL);
+ exynos_pcie_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV2_EMP_LVL);
+ exynos_pcie_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV3_EMP_LVL);
/* set LVCC */
- exynos_phy_writel(ep, 0x20, PCIE_PHY_TRSV0_LVCC);
- exynos_phy_writel(ep, 0xa0, PCIE_PHY_TRSV1_LVCC);
- exynos_phy_writel(ep, 0xa0, PCIE_PHY_TRSV2_LVCC);
- exynos_phy_writel(ep, 0xa0, PCIE_PHY_TRSV3_LVCC);
+ exynos_pcie_writel(ep->phy_base, 0x20, PCIE_PHY_TRSV0_LVCC);
+ exynos_pcie_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV1_LVCC);
+ exynos_pcie_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV2_LVCC);
+ exynos_pcie_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV3_LVCC);
}
static void exynos_pcie_assert_reset(struct exynos_pcie *ep)
@@ -321,24 +301,24 @@ static int exynos_pcie_establish_link(struct exynos_pcie *ep)
exynos_pcie_init_phy(ep);
/* pulse for common reset */
- exynos_blk_writel(ep, 1, PCIE_PHY_COMMON_RESET);
+ exynos_pcie_writel(ep->block_base, 1, PCIE_PHY_COMMON_RESET);
udelay(500);
- exynos_blk_writel(ep, 0, PCIE_PHY_COMMON_RESET);
+ exynos_pcie_writel(ep->block_base, 0, PCIE_PHY_COMMON_RESET);
exynos_pcie_deassert_core_reset(ep);
dw_pcie_setup_rc(pp);
exynos_pcie_assert_reset(ep);
/* assert LTSSM enable */
- exynos_elb_writel(ep, PCIE_ELBI_LTSSM_ENABLE,
+ exynos_pcie_writel(ep->elbi_base, PCIE_ELBI_LTSSM_ENABLE,
PCIE_APP_LTSSM_ENABLE);
/* check if the link is up or not */
if (!dw_pcie_wait_for_link(pp))
return 0;
- while (exynos_phy_readl(ep, PCIE_PHY_PLL_LOCKED) == 0) {
- val = exynos_blk_readl(ep, PCIE_PHY_PLL_LOCKED);
+ while (exynos_pcie_readl(ep->phy_base, PCIE_PHY_PLL_LOCKED) == 0) {
+ val = exynos_pcie_readl(ep->block_base, PCIE_PHY_PLL_LOCKED);
dev_info(dev, "PLL Locked: 0x%x\n", val);
}
exynos_pcie_power_off_phy(ep);
@@ -349,8 +329,8 @@ static void exynos_pcie_clear_irq_pulse(struct exynos_pcie *ep)
{
u32 val;
- val = exynos_elb_readl(ep, PCIE_IRQ_PULSE);
- exynos_elb_writel(ep, val, PCIE_IRQ_PULSE);
+ val = exynos_pcie_readl(ep->elbi_base, PCIE_IRQ_PULSE);
+ exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_PULSE);
}
static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *ep)
@@ -360,7 +340,7 @@ static void exynos_pcie_enable_irq_pulse(struct exynos_pcie *ep)
/* enable INTX interrupt */
val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT |
IRQ_INTC_ASSERT | IRQ_INTD_ASSERT;
- exynos_elb_writel(ep, val, PCIE_IRQ_EN_PULSE);
+ exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_EN_PULSE);
}
static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg)
@@ -387,9 +367,9 @@ static void exynos_pcie_msi_init(struct exynos_pcie *ep)
dw_pcie_msi_init(pp);
/* enable MSI interrupt */
- val = exynos_elb_readl(ep, PCIE_IRQ_EN_LEVEL);
+ val = exynos_pcie_readl(ep->elbi_base, PCIE_IRQ_EN_LEVEL);
val |= IRQ_MSI_ENABLE;
- exynos_elb_writel(ep, val, PCIE_IRQ_EN_LEVEL);
+ exynos_pcie_writel(ep->elbi_base, val, PCIE_IRQ_EN_LEVEL);
}
static void exynos_pcie_enable_interrupts(struct exynos_pcie *ep)
@@ -449,7 +429,7 @@ static int exynos_pcie_link_up(struct pcie_port *pp)
struct exynos_pcie *ep = to_exynos_pcie(pp);
u32 val;
- val = exynos_elb_readl(ep, PCIE_ELBI_RDLH_LINKUP);
+ val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_RDLH_LINKUP);
if (val == PCIE_ELBI_LTSSM_ENABLE)
return 1;
--
2.10.2
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH V3 3/5] PCI: exynos: Remove the unnecessary variables
[not found] ` <CGME20170116063141epcas5p329a9496aabe28a9961176539c47065dc@epcas5p3.samsung.com>
@ 2017-01-16 6:31 ` Jaehoon Chung
0 siblings, 0 replies; 10+ messages in thread
From: Jaehoon Chung @ 2017-01-16 6:31 UTC (permalink / raw)
To: linux-pci
Cc: bhelgaas, krzk, linux-kernel, jingoohan1, javier, kgene,
linux-samsung-soc, cpgs, Jaehoon Chung
Remove the unnecessary variables(elbi/phy/block_base).
It needs one resource structure for assigning each resource.
So it replaces with one 'res' variable.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
---
Changelog on V3:
- None
Changelog on V2:
- None
drivers/pci/host/pci-exynos.c | 16 +++++++---------
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
index 166881a..6255294 100644
--- a/drivers/pci/host/pci-exynos.c
+++ b/drivers/pci/host/pci-exynos.c
@@ -507,9 +507,7 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
struct exynos_pcie *ep;
struct pcie_port *pp;
struct device_node *np = dev->of_node;
- struct resource *elbi_base;
- struct resource *phy_base;
- struct resource *block_base;
+ struct resource *res;
int ret;
ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
@@ -540,22 +538,22 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
if (ret)
goto fail_clk;
- elbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- ep->elbi_base = devm_ioremap_resource(dev, elbi_base);
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ ep->elbi_base = devm_ioremap_resource(dev, res);
if (IS_ERR(ep->elbi_base)) {
ret = PTR_ERR(ep->elbi_base);
goto fail_bus_clk;
}
- phy_base = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- ep->phy_base = devm_ioremap_resource(dev, phy_base);
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ ep->phy_base = devm_ioremap_resource(dev, res);
if (IS_ERR(ep->phy_base)) {
ret = PTR_ERR(ep->phy_base);
goto fail_bus_clk;
}
- block_base = platform_get_resource(pdev, IORESOURCE_MEM, 2);
- ep->block_base = devm_ioremap_resource(dev, block_base);
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
+ ep->block_base = devm_ioremap_resource(dev, res);
if (IS_ERR(ep->block_base)) {
ret = PTR_ERR(ep->block_base);
goto fail_bus_clk;
--
2.10.2
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH V3 4/5] PCI: exynos: Use the bitops API to operate the bit shifting
[not found] ` <CGME20170116063141epcas5p3717d40cea33d34b715b6c0016c10ab16@epcas5p3.samsung.com>
@ 2017-01-16 6:31 ` Jaehoon Chung
0 siblings, 0 replies; 10+ messages in thread
From: Jaehoon Chung @ 2017-01-16 6:31 UTC (permalink / raw)
To: linux-pci
Cc: bhelgaas, krzk, linux-kernel, jingoohan1, javier, kgene,
linux-samsung-soc, cpgs, Jaehoon Chung
Just use the bitops api to operate the bit.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
---
Changelog on V3:
- None
Changelog on V2:
- None
drivers/pci/host/pci-exynos.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
index 6255294..c5892c2 100644
--- a/drivers/pci/host/pci-exynos.c
+++ b/drivers/pci/host/pci-exynos.c
@@ -40,19 +40,19 @@ struct exynos_pcie {
/* PCIe ELBI registers */
#define PCIE_IRQ_PULSE 0x000
-#define IRQ_INTA_ASSERT (0x1 << 0)
-#define IRQ_INTB_ASSERT (0x1 << 2)
-#define IRQ_INTC_ASSERT (0x1 << 4)
-#define IRQ_INTD_ASSERT (0x1 << 6)
+#define IRQ_INTA_ASSERT BIT(0)
+#define IRQ_INTB_ASSERT BIT(2)
+#define IRQ_INTC_ASSERT BIT(4)
+#define IRQ_INTD_ASSERT BIT(6)
#define PCIE_IRQ_LEVEL 0x004
#define PCIE_IRQ_SPECIAL 0x008
#define PCIE_IRQ_EN_PULSE 0x00c
#define PCIE_IRQ_EN_LEVEL 0x010
-#define IRQ_MSI_ENABLE (0x1 << 2)
+#define IRQ_MSI_ENABLE BIT(2)
#define PCIE_IRQ_EN_SPECIAL 0x014
#define PCIE_PWR_RESET 0x018
#define PCIE_CORE_RESET 0x01c
-#define PCIE_CORE_RESET_ENABLE (0x1 << 0)
+#define PCIE_CORE_RESET_ENABLE BIT(0)
#define PCIE_STICKY_RESET 0x020
#define PCIE_NONSTICKY_RESET 0x024
#define PCIE_APP_INIT_RESET 0x028
@@ -61,7 +61,7 @@ struct exynos_pcie {
#define PCIE_ELBI_LTSSM_ENABLE 0x1
#define PCIE_ELBI_SLV_AWMISC 0x11c
#define PCIE_ELBI_SLV_ARMISC 0x120
-#define PCIE_ELBI_SLV_DBI_ENABLE (0x1 << 21)
+#define PCIE_ELBI_SLV_DBI_ENABLE BIT(21)
/* PCIe Purple registers */
#define PCIE_PHY_GLOBAL_RESET 0x000
@@ -79,27 +79,27 @@ struct exynos_pcie {
#define PCIE_PHY_DCC_FEEDBACK 0x014
#define PCIE_PHY_PLL_DIV_1 0x05c
#define PCIE_PHY_COMMON_POWER 0x064
-#define PCIE_PHY_COMMON_PD_CMN (0x1 << 3)
+#define PCIE_PHY_COMMON_PD_CMN BIT(3)
#define PCIE_PHY_TRSV0_EMP_LVL 0x084
#define PCIE_PHY_TRSV0_DRV_LVL 0x088
#define PCIE_PHY_TRSV0_RXCDR 0x0ac
#define PCIE_PHY_TRSV0_POWER 0x0c4
-#define PCIE_PHY_TRSV0_PD_TSV (0x1 << 7)
+#define PCIE_PHY_TRSV0_PD_TSV BIT(7)
#define PCIE_PHY_TRSV0_LVCC 0x0dc
#define PCIE_PHY_TRSV1_EMP_LVL 0x144
#define PCIE_PHY_TRSV1_RXCDR 0x16c
#define PCIE_PHY_TRSV1_POWER 0x184
-#define PCIE_PHY_TRSV1_PD_TSV (0x1 << 7)
+#define PCIE_PHY_TRSV1_PD_TSV BIT(7)
#define PCIE_PHY_TRSV1_LVCC 0x19c
#define PCIE_PHY_TRSV2_EMP_LVL 0x204
#define PCIE_PHY_TRSV2_RXCDR 0x22c
#define PCIE_PHY_TRSV2_POWER 0x244
-#define PCIE_PHY_TRSV2_PD_TSV (0x1 << 7)
+#define PCIE_PHY_TRSV2_PD_TSV BIT(7)
#define PCIE_PHY_TRSV2_LVCC 0x25c
#define PCIE_PHY_TRSV3_EMP_LVL 0x2c4
#define PCIE_PHY_TRSV3_RXCDR 0x2ec
#define PCIE_PHY_TRSV3_POWER 0x304
-#define PCIE_PHY_TRSV3_PD_TSV (0x1 << 7)
+#define PCIE_PHY_TRSV3_PD_TSV BIT(7)
#define PCIE_PHY_TRSV3_LVCC 0x31c
static void exynos_pcie_writel(void __iomem *base, u32 val, u32 reg)
--
2.10.2
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH V3 5/5] PCI: exynos: remove the duplicated codes
[not found] ` <CGME20170116063142epcas1p32d52a367a66410206b3ddb4149fde079@epcas1p3.samsung.com>
@ 2017-01-16 6:31 ` Jaehoon Chung
0 siblings, 0 replies; 10+ messages in thread
From: Jaehoon Chung @ 2017-01-16 6:31 UTC (permalink / raw)
To: linux-pci
Cc: bhelgaas, krzk, linux-kernel, jingoohan1, javier, kgene,
linux-samsung-soc, cpgs, Jaehoon Chung
Removed the duplicated codes.
It can use the more simply than now.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
---
Changelog on V3:
- None
Changelog on V2:
- None
drivers/pci/host/pci-exynos.c | 22 ++++++++--------------
1 file changed, 8 insertions(+), 14 deletions(-)
diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
index c5892c2..faee7d3 100644
--- a/drivers/pci/host/pci-exynos.c
+++ b/drivers/pci/host/pci-exynos.c
@@ -116,30 +116,24 @@ static void exynos_pcie_sideband_dbi_w_mode(struct exynos_pcie *ep, bool on)
{
u32 val;
- if (on) {
- val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_AWMISC);
+ val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_AWMISC);
+ if (on)
val |= PCIE_ELBI_SLV_DBI_ENABLE;
- exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_AWMISC);
- } else {
- val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_AWMISC);
+ else
val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
- exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_AWMISC);
- }
+ exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_AWMISC);
}
static void exynos_pcie_sideband_dbi_r_mode(struct exynos_pcie *ep, bool on)
{
u32 val;
- if (on) {
- val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_ARMISC);
+ val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_ARMISC);
+ if (on)
val |= PCIE_ELBI_SLV_DBI_ENABLE;
- exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_ARMISC);
- } else {
- val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_ARMISC);
+ else
val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
- exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_ARMISC);
- }
+ exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_ARMISC);
}
static void exynos_pcie_assert_core_reset(struct exynos_pcie *ep)
--
2.10.2
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH V3 0/5] PCI: exynos: cleans the minor things
2017-01-16 6:31 ` [PATCH V3 0/5] PCI: exynos: cleans the minor things Jaehoon Chung
` (4 preceding siblings ...)
[not found] ` <CGME20170116063142epcas1p32d52a367a66410206b3ddb4149fde079@epcas1p3.samsung.com>
@ 2017-01-28 21:27 ` Bjorn Helgaas
2017-01-31 21:16 ` Jingoo Han
2017-02-08 19:42 ` Bjorn Helgaas
6 siblings, 1 reply; 10+ messages in thread
From: Bjorn Helgaas @ 2017-01-28 21:27 UTC (permalink / raw)
To: Jaehoon Chung
Cc: linux-pci, bhelgaas, krzk, linux-kernel, jingoohan1, javier,
kgene, linux-samsung-soc, cpgs, Pankaj Dubey
On Mon, Jan 16, 2017 at 03:31:33PM +0900, Jaehoon Chung wrote:
> Current pci-exynos.c is used for only EXYNOS5440.
> It's too complex to support the other Exynos SoCs.
> Before supporting the other Exynos SoCs, it needs to clean the codes.
>
> Changelog on V3:
> - Splits "PCI: exynos: replace to one register accessor from each accessors"
>
> Changelog on V2:
> - Changes the all pointer names as "ep" instead of "exynos_pcie"
>
> Jaehoon Chung (5):
> PCI: exynos: Rename all pointer names from "exynos_pcie" to "ep"
> PCI: exynos: Replace the *_blk/*_phy/*_elb accessors
> PCI: exynos: Remove the unnecessary variables
> PCI: exynos: Use the bitops API to operate the bit shifting
> PCI: exynos: remove the duplicated codes
>
> drivers/pci/host/pci-exynos.c | 392 +++++++++++++++++++-----------------------
Waiting for ack from Jingoom, per MAINTAINERS:
Jingoo Han <jingoohan1@gmail.com> (maintainer:PCI DRIVER FOR SAMSUNG EXYNOS)
Pankaj has a follow-on patch that depends on this series:
https://patchwork.ozlabs.org/patch/711210/
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH V3 0/5] PCI: exynos: cleans the minor things
2017-01-28 21:27 ` [PATCH V3 0/5] PCI: exynos: cleans the minor things Bjorn Helgaas
@ 2017-01-31 21:16 ` Jingoo Han
2017-01-31 23:41 ` Jaehoon Chung
0 siblings, 1 reply; 10+ messages in thread
From: Jingoo Han @ 2017-01-31 21:16 UTC (permalink / raw)
To: 'Bjorn Helgaas', 'Jaehoon Chung'
Cc: linux-pci, bhelgaas, krzk, linux-kernel, javier, kgene,
linux-samsung-soc, cpgs, 'Pankaj Dubey'
On Saturday, January 28, 2017 4:28 PM, Bjorn Helgaas wrote:
> On Mon, Jan 16, 2017 at 03:31:33PM +0900, Jaehoon Chung wrote:
> > Current pci-exynos.c is used for only EXYNOS5440.
> > It's too complex to support the other Exynos SoCs.
> > Before supporting the other Exynos SoCs, it needs to clean the codes.
> >
> > Changelog on V3:
> > - Splits "PCI: exynos: replace to one register accessor from each
> accessors"
> >
> > Changelog on V2:
> > - Changes the all pointer names as "ep" instead of "exynos_pcie"
> >
> > Jaehoon Chung (5):
> > PCI: exynos: Rename all pointer names from "exynos_pcie" to "ep"
> > PCI: exynos: Replace the *_blk/*_phy/*_elb accessors
> > PCI: exynos: Remove the unnecessary variables
> > PCI: exynos: Use the bitops API to operate the bit shifting
> > PCI: exynos: remove the duplicated codes
> >
> > drivers/pci/host/pci-exynos.c | 392 +++++++++++++++++++----------------
> -------
>
> Waiting for ack from Jingoom, per MAINTAINERS:
>
> Jingoo Han <jingoohan1@gmail.com> (maintainer:PCI DRIVER FOR SAMSUNG
> EXYNOS)
It looks good.
Acked-by: Jingoo Han <jingoohan1@gmail.com>
Thanks,
Jingoo
>
> Pankaj has a follow-on patch that depends on this series:
> https://patchwork.ozlabs.org/patch/711210/
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH V3 0/5] PCI: exynos: cleans the minor things
2017-01-31 21:16 ` Jingoo Han
@ 2017-01-31 23:41 ` Jaehoon Chung
0 siblings, 0 replies; 10+ messages in thread
From: Jaehoon Chung @ 2017-01-31 23:41 UTC (permalink / raw)
To: Jingoo Han, 'Bjorn Helgaas'
Cc: linux-pci, bhelgaas, krzk, linux-kernel, javier, kgene,
linux-samsung-soc, cpgs, 'Pankaj Dubey'
On 02/01/2017 06:16 AM, Jingoo Han wrote:
> On Saturday, January 28, 2017 4:28 PM, Bjorn Helgaas wrote:
>> On Mon, Jan 16, 2017 at 03:31:33PM +0900, Jaehoon Chung wrote:
>>> Current pci-exynos.c is used for only EXYNOS5440.
>>> It's too complex to support the other Exynos SoCs.
>>> Before supporting the other Exynos SoCs, it needs to clean the codes.
>>>
>>> Changelog on V3:
>>> - Splits "PCI: exynos: replace to one register accessor from each
>> accessors"
>>>
>>> Changelog on V2:
>>> - Changes the all pointer names as "ep" instead of "exynos_pcie"
>>>
>>> Jaehoon Chung (5):
>>> PCI: exynos: Rename all pointer names from "exynos_pcie" to "ep"
>>> PCI: exynos: Replace the *_blk/*_phy/*_elb accessors
>>> PCI: exynos: Remove the unnecessary variables
>>> PCI: exynos: Use the bitops API to operate the bit shifting
>>> PCI: exynos: remove the duplicated codes
>>>
>>> drivers/pci/host/pci-exynos.c | 392 +++++++++++++++++++----------------
>> -------
>>
>> Waiting for ack from Jingoom, per MAINTAINERS:
>>
>> Jingoo Han <jingoohan1@gmail.com> (maintainer:PCI DRIVER FOR SAMSUNG
>> EXYNOS)
>
> It looks good.
>
> Acked-by: Jingoo Han <jingoohan1@gmail.com>
Thank you! I will post the other patches soon.
Best Regards,
Jaehoon Chung
>
> Thanks,
> Jingoo
>
>>
>> Pankaj has a follow-on patch that depends on this series:
>> https://patchwork.ozlabs.org/patch/711210/
>
>
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH V3 0/5] PCI: exynos: cleans the minor things
2017-01-16 6:31 ` [PATCH V3 0/5] PCI: exynos: cleans the minor things Jaehoon Chung
` (5 preceding siblings ...)
2017-01-28 21:27 ` [PATCH V3 0/5] PCI: exynos: cleans the minor things Bjorn Helgaas
@ 2017-02-08 19:42 ` Bjorn Helgaas
6 siblings, 0 replies; 10+ messages in thread
From: Bjorn Helgaas @ 2017-02-08 19:42 UTC (permalink / raw)
To: Jaehoon Chung
Cc: linux-pci, bhelgaas, krzk, linux-kernel, jingoohan1, javier,
kgene, linux-samsung-soc, cpgs
On Mon, Jan 16, 2017 at 03:31:33PM +0900, Jaehoon Chung wrote:
> Current pci-exynos.c is used for only EXYNOS5440.
> It's too complex to support the other Exynos SoCs.
> Before supporting the other Exynos SoCs, it needs to clean the codes.
>
> Changelog on V3:
> - Splits "PCI: exynos: replace to one register accessor from each accessors"
>
> Changelog on V2:
> - Changes the all pointer names as "ep" instead of "exynos_pcie"
>
> Jaehoon Chung (5):
> PCI: exynos: Rename all pointer names from "exynos_pcie" to "ep"
> PCI: exynos: Replace the *_blk/*_phy/*_elb accessors
> PCI: exynos: Remove the unnecessary variables
> PCI: exynos: Use the bitops API to operate the bit shifting
> PCI: exynos: remove the duplicated codes
>
> drivers/pci/host/pci-exynos.c | 392 +++++++++++++++++++-----------------------
> 1 file changed, 181 insertions(+), 211 deletions(-)
Applied with Jingoo's ack to pci/host-exynos for v4.11, thanks!
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2017-02-08 19:42 UTC | newest]
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2017-01-16 6:31 ` [PATCH V3 2/5] PCI: exynos: Replace the *_blk/*_phy/*_elb accessors Jaehoon Chung
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2017-01-16 6:31 ` [PATCH V3 3/5] PCI: exynos: Remove the unnecessary variables Jaehoon Chung
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2017-01-16 6:31 ` [PATCH V3 4/5] PCI: exynos: Use the bitops API to operate the bit shifting Jaehoon Chung
[not found] ` <CGME20170116063142epcas1p32d52a367a66410206b3ddb4149fde079@epcas1p3.samsung.com>
2017-01-16 6:31 ` [PATCH V3 5/5] PCI: exynos: remove the duplicated codes Jaehoon Chung
2017-01-28 21:27 ` [PATCH V3 0/5] PCI: exynos: cleans the minor things Bjorn Helgaas
2017-01-31 21:16 ` Jingoo Han
2017-01-31 23:41 ` Jaehoon Chung
2017-02-08 19:42 ` Bjorn Helgaas
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