From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Andrzej Hajda <a.hajda@samsung.com>
Cc: Inki Dae <inki.dae@samsung.com>,
dri-devel@lists.freedesktop.org,
Krzysztof Kozlowski <krzk@kernel.org>,
linux-samsung-soc@vger.kernel.org,
Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>,
linux-kernel@vger.kernel.org,
Kyungmin Park <kyungmin.park@samsung.com>,
Marek Szyprowski <m.szyprowski@samsung.com>
Subject: Re: [PATCH 6/7] drm/exynos/decon5433: signal vblank only on odd fields
Date: Fri, 20 Jan 2017 15:55:40 +0200 [thread overview]
Message-ID: <20170120135540.GC31595@intel.com> (raw)
In-Reply-To: <1484895145-511-7-git-send-email-a.hajda@samsung.com>
On Fri, Jan 20, 2017 at 07:52:24AM +0100, Andrzej Hajda wrote:
> In case of interlace mode irq is generated for odd and even fields, but
> vblank should be signaled only for the last emitted field.
I'm pretty sure most drivers signal it for both fields. At least i915
does.
>
> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
> ---
> drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 7 +++++++
> include/video/exynos5433_decon.h | 1 +
> 2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
> index 46434ba9..ad8b93a 100644
> --- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
> +++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
> @@ -591,6 +591,13 @@ static irqreturn_t decon_irq_handler(int irq, void *dev_id)
>
> if (val) {
> writel(val, ctx->addr + DECON_VIDINTCON1);
> + if (ctx->out_type & IFTYPE_HDMI) {
> + val = readl(ctx->addr + DECON_VIDOUTCON0);
> + val &= VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F;
> + if (val ==
> + (VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F))
> + return IRQ_HANDLED;
> + }
> drm_crtc_handle_vblank(&ctx->crtc->base);
> }
>
> diff --git a/include/video/exynos5433_decon.h b/include/video/exynos5433_decon.h
> index b26511a..ef8e2a8 100644
> --- a/include/video/exynos5433_decon.h
> +++ b/include/video/exynos5433_decon.h
> @@ -89,6 +89,7 @@
> #define VIDCON0_ENVID_F (1 << 0)
>
> /* VIDOUTCON0 */
> +#define VIDOUT_INTERLACE_FIELD_F (1 << 29)
> #define VIDOUT_INTERLACE_EN_F (1 << 28)
> #define VIDOUT_LCD_ON (1 << 24)
> #define VIDOUT_IF_F_MASK (0x3 << 20)
> --
> 2.7.4
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Ville Syrjälä
Intel OTC
next prev parent reply other threads:[~2017-01-20 13:55 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20170120065229eucas1p22f0eed53220820b1145294029d4bd706@eucas1p2.samsung.com>
2017-01-20 6:52 ` [PATCH 0/7] drm/exynos: add Ultra HD and interlace modes support to Exynos5433 Andrzej Hajda
[not found] ` <CGME20170120065229eucas1p173d2b1844498dd3afdd9d2860cd1ee93@eucas1p1.samsung.com>
2017-01-20 6:52 ` [PATCH 1/7] drm/exynos/hdmi: add 297MHz pixel clock support Andrzej Hajda
[not found] ` <CGME20170120065230eucas1p20a73a6911158fb6eb2f2d2b22db36aba@eucas1p2.samsung.com>
2017-01-20 6:52 ` [PATCH 2/7] drm/exynos/hdmi: fix VSI infoframe registers Andrzej Hajda
[not found] ` <CGME20170120065230eucas1p1839ddd9b5fefa265ad5feab59e67fd2a@eucas1p1.samsung.com>
2017-01-20 6:52 ` [PATCH 3/7] drm/exynos/hdmi: fix PLL for 27MHz settings Andrzej Hajda
[not found] ` <CGME20170120065230eucas1p2e22f7b832ec7e1c770c3e8a27a3341f5@eucas1p2.samsung.com>
2017-01-20 6:52 ` [PATCH 4/7] drm/exynos/hdmi: add bridge support Andrzej Hajda
2017-02-01 7:31 ` Inki Dae
2017-02-01 7:34 ` Andrzej Hajda
2017-02-01 7:44 ` Inki Dae
2017-02-01 8:12 ` Andrzej Hajda
2017-02-01 8:17 ` Inki Dae
[not found] ` <CGME20170201082940eucas1p1f19e15328a787d6b77cba97bad92afce@eucas1p1.samsung.com>
2017-02-01 8:29 ` [PATCH v3 " Andrzej Hajda
2017-02-03 6:38 ` Inki Dae
2017-02-03 6:39 ` Inki Dae
[not found] ` <CGME20170120065231eucas1p23fa4730d36c855bc441ba23411ab6ffd@eucas1p2.samsung.com>
2017-01-20 6:52 ` [PATCH 5/7] drm/exynos/decon5433: add support for interlace modes Andrzej Hajda
[not found] ` <CGME20170120065231eucas1p121d2a987695fdce00e1b2bba445f1818@eucas1p1.samsung.com>
2017-01-20 6:52 ` [PATCH 6/7] drm/exynos/decon5433: signal vblank only on odd fields Andrzej Hajda
2017-01-20 13:55 ` Ville Syrjälä [this message]
2017-01-23 9:15 ` Andrzej Hajda
2017-01-25 14:06 ` Ville Syrjälä
2017-01-26 8:22 ` Andrzej Hajda
2017-01-26 10:42 ` Ville Syrjälä
[not found] ` <CGME20170120065232eucas1p170340d5a71e89db7c08d7218adbe4c2c@eucas1p1.samsung.com>
2017-01-20 6:52 ` [PATCH 7/7] arm64: dts: exynos: configure TV path clocks for Ultra HD modes Andrzej Hajda
2017-01-20 14:51 ` Krzysztof Kozlowski
[not found] ` <CGME20170123075623eucas1p19a1edd12eec91abdbbf786b308f65051@eucas1p1.samsung.com>
2017-01-23 7:56 ` [PATCH v2 " Andrzej Hajda
2017-01-23 9:08 ` Marek Szyprowski
[not found] ` <CGME20170123100557eucas1p28174748d64c4e8503a2006a9c5b554a6@eucas1p2.samsung.com>
2017-01-23 10:05 ` [PATCH v3 " Andrzej Hajda
2017-01-23 16:35 ` Krzysztof Kozlowski
2017-01-20 14:49 ` [PATCH 0/7] drm/exynos: add Ultra HD and interlace modes support to Exynos5433 Krzysztof Kozlowski
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