* [PATCH 0/2] gpio: aspeed: Implement banks Y, Z, AA, AB and AC
@ 2017-01-23 5:26 Andrew Jeffery
2017-01-23 5:26 ` [PATCH 1/2] gpio: aspeed: Make bank names strings Andrew Jeffery
2017-01-23 5:26 ` [PATCH 2/2] gpio: aspeed: Add banks Y, Z, AA, AB and AC Andrew Jeffery
0 siblings, 2 replies; 6+ messages in thread
From: Andrew Jeffery @ 2017-01-23 5:26 UTC (permalink / raw)
To: Linus Walleij
Cc: Andrew Jeffery, Joel Stanley, linux-gpio, linux-kernel, openbmc
Hi Linus,
This short series resolves a TODO comment in the Aspeed GPIO driver regarding
banks Y, Z, AA, AB and AC by implementing their support. It's a little involved
given some of the characteristics of these banks, but hopefully nothing too
controversial.
Cheers,
Andrew
Andrew Jeffery (1):
gpio: aspeed: Add banks Y, Z, AA, AB and AC
Joel Stanley (1):
gpio: aspeed: Make bank names strings
drivers/gpio/gpio-aspeed.c | 187 ++++++++++++++++++++++++++++++++++++++++-----
1 file changed, 166 insertions(+), 21 deletions(-)
--
2.9.3
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/2] gpio: aspeed: Make bank names strings
2017-01-23 5:26 [PATCH 0/2] gpio: aspeed: Implement banks Y, Z, AA, AB and AC Andrew Jeffery
@ 2017-01-23 5:26 ` Andrew Jeffery
2017-01-26 13:32 ` Linus Walleij
2017-01-23 5:26 ` [PATCH 2/2] gpio: aspeed: Add banks Y, Z, AA, AB and AC Andrew Jeffery
1 sibling, 1 reply; 6+ messages in thread
From: Andrew Jeffery @ 2017-01-23 5:26 UTC (permalink / raw)
To: Linus Walleij
Cc: Joel Stanley, linux-gpio, linux-kernel, openbmc, Andrew Jeffery
From: Joel Stanley <joel@jms.id.au>
The Aspeed SoCs have more GPIOs than can be represented with A-Z. The
documentation uses two letter names such as AA and AB, so make the names
a three-character array in the bank struct to accommodate this.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
drivers/gpio/gpio-aspeed.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c
index 03a5925a423c..20f6f8ae4671 100644
--- a/drivers/gpio/gpio-aspeed.c
+++ b/drivers/gpio/gpio-aspeed.c
@@ -28,39 +28,39 @@ struct aspeed_gpio {
struct aspeed_gpio_bank {
uint16_t val_regs;
uint16_t irq_regs;
- const char names[4];
+ const char names[4][3];
};
static const struct aspeed_gpio_bank aspeed_gpio_banks[] = {
{
.val_regs = 0x0000,
.irq_regs = 0x0008,
- .names = { 'A', 'B', 'C', 'D' },
+ .names = { "A", "B", "C", "D" },
},
{
.val_regs = 0x0020,
.irq_regs = 0x0028,
- .names = { 'E', 'F', 'G', 'H' },
+ .names = { "E", "F", "G", "H" },
},
{
.val_regs = 0x0070,
.irq_regs = 0x0098,
- .names = { 'I', 'J', 'K', 'L' },
+ .names = { "I", "J", "K", "L" },
},
{
.val_regs = 0x0078,
.irq_regs = 0x00e8,
- .names = { 'M', 'N', 'O', 'P' },
+ .names = { "M", "N", "O", "P" },
},
{
.val_regs = 0x0080,
.irq_regs = 0x0118,
- .names = { 'Q', 'R', 'S', 'T' },
+ .names = { "Q", "R", "S", "T" },
},
{
.val_regs = 0x0088,
.irq_regs = 0x0148,
- .names = { 'U', 'V', 'W', 'X' },
+ .names = { "U", "V", "W", "X" },
},
/*
* A bank exists for { 'Y', 'Z', "AA", "AB" }, but is not implemented.
--
2.9.3
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/2] gpio: aspeed: Add banks Y, Z, AA, AB and AC
2017-01-23 5:26 [PATCH 0/2] gpio: aspeed: Implement banks Y, Z, AA, AB and AC Andrew Jeffery
2017-01-23 5:26 ` [PATCH 1/2] gpio: aspeed: Make bank names strings Andrew Jeffery
@ 2017-01-23 5:26 ` Andrew Jeffery
2017-01-23 6:47 ` kbuild test robot
2017-01-23 6:59 ` kbuild test robot
1 sibling, 2 replies; 6+ messages in thread
From: Andrew Jeffery @ 2017-01-23 5:26 UTC (permalink / raw)
To: Linus Walleij
Cc: Andrew Jeffery, Joel Stanley, linux-gpio, linux-kernel, openbmc
This is less straight-forward than one would hope, as some banks only
have 4 pins rather than 8, others are output only, yet more (W and
X, already supported) are input-only, and in the case of the g4 SoC bank
AC doesn't exist.
Add some structs to describe the varying properties of different banks
and integrate mechanisms to deny requests for unsupported
configurations.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
drivers/gpio/gpio-aspeed.c | 173 +++++++++++++++++++++++++++++++++++++++++----
1 file changed, 159 insertions(+), 14 deletions(-)
diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c
index 20f6f8ae4671..365b5ab8bbab 100644
--- a/drivers/gpio/gpio-aspeed.c
+++ b/drivers/gpio/gpio-aspeed.c
@@ -15,14 +15,27 @@
#include <linux/io.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>
+#include <linux/gpio.h>
#include <linux/gpio/driver.h>
#include <linux/pinctrl/consumer.h>
+struct aspeed_bank_props {
+ unsigned int bank;
+ u32 input;
+ u32 output;
+};
+
+struct aspeed_gpio_config {
+ unsigned int nr_gpios;
+ const struct aspeed_bank_props *props;
+};
+
struct aspeed_gpio {
struct gpio_chip chip;
spinlock_t lock;
void __iomem *base;
int irq;
+ const struct aspeed_gpio_config *config;
};
struct aspeed_gpio_bank {
@@ -62,11 +75,16 @@ static const struct aspeed_gpio_bank aspeed_gpio_banks[] = {
.irq_regs = 0x0148,
.names = { "U", "V", "W", "X" },
},
- /*
- * A bank exists for { 'Y', 'Z', "AA", "AB" }, but is not implemented.
- * Only half of GPIOs Y support interrupt configuration, and none of Z,
- * AA or AB do as they are output only.
- */
+ {
+ .val_regs = 0x01E0,
+ .irq_regs = 0x0178,
+ .names = { "Y", "Z", "AA", "AB" },
+ },
+ {
+ .val_regs = 0x01E8,
+ .irq_regs = 0x01A8,
+ .names = { "AC", "", "", "" },
+ },
};
#define GPIO_BANK(x) ((x) >> 5)
@@ -90,6 +108,51 @@ static const struct aspeed_gpio_bank *to_bank(unsigned int offset)
return &aspeed_gpio_banks[bank];
}
+static inline bool is_bank_props_sentinel(const struct aspeed_bank_props *props)
+{
+ return !(props->input || props->output);
+}
+
+static inline const struct aspeed_bank_props *find_bank_props(
+ struct aspeed_gpio *gpio, unsigned int offset)
+{
+ const struct aspeed_bank_props *props = gpio->config->props;
+
+ while (!is_bank_props_sentinel(props)) {
+ if (props->bank == GPIO_BANK(offset))
+ return props;
+ props++;
+ }
+
+ return NULL;
+}
+
+static inline bool have_gpio(struct aspeed_gpio *gpio, unsigned int offset)
+{
+ const struct aspeed_bank_props *props = find_bank_props(gpio, offset);
+ const struct aspeed_gpio_bank *bank = to_bank(offset);
+ unsigned int group = GPIO_OFFSET(offset) / 8;
+
+ return bank->names[group][0] != '\0' &&
+ (!props || ((props->input | props->output) & GPIO_BIT(offset)));
+}
+
+static inline bool have_input(struct aspeed_gpio *gpio, unsigned int offset)
+{
+ const struct aspeed_bank_props *props = find_bank_props(gpio, offset);
+
+ return !props || (props->input & GPIO_BIT(offset));
+}
+
+#define have_irq(g, o) have_input((g), (o))
+
+static inline bool have_output(struct aspeed_gpio *gpio, unsigned int offset)
+{
+ const struct aspeed_bank_props *props = find_bank_props(gpio, offset);
+
+ return !props || (props->output & GPIO_BIT(offset));
+}
+
static void __iomem *bank_val_reg(struct aspeed_gpio *gpio,
const struct aspeed_gpio_bank *bank,
unsigned int reg)
@@ -152,6 +215,9 @@ static int aspeed_gpio_dir_in(struct gpio_chip *gc, unsigned int offset)
unsigned long flags;
u32 reg;
+ if (!have_input(gpio, offset))
+ return -ENOTSUPP;
+
spin_lock_irqsave(&gpio->lock, flags);
reg = ioread32(bank_val_reg(gpio, bank, GPIO_DIR));
@@ -170,6 +236,9 @@ static int aspeed_gpio_dir_out(struct gpio_chip *gc,
unsigned long flags;
u32 reg;
+ if (!have_output(gpio, offset))
+ return -ENOTSUPP;
+
spin_lock_irqsave(&gpio->lock, flags);
reg = ioread32(bank_val_reg(gpio, bank, GPIO_DIR));
@@ -189,6 +258,12 @@ static int aspeed_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
unsigned long flags;
u32 val;
+ if (!have_input(gpio, offset))
+ return GPIOF_DIR_OUT;
+
+ if (!have_output(gpio, offset))
+ return GPIOF_DIR_IN;
+
spin_lock_irqsave(&gpio->lock, flags);
val = ioread32(bank_val_reg(gpio, bank, GPIO_DIR)) & GPIO_BIT(offset);
@@ -205,10 +280,17 @@ static inline int irqd_to_aspeed_gpio_data(struct irq_data *d,
u32 *bit)
{
int offset;
+ struct aspeed_gpio *internal;
offset = irqd_to_hwirq(d);
- *gpio = irq_data_get_irq_chip_data(d);
+ internal = irq_data_get_irq_chip_data(d);
+
+ /* This might be a bit of a questionable place to check */
+ if (!have_irq(internal, offset))
+ return -ENOTSUPP;
+
+ *gpio = internal;
*bank = to_bank(offset);
*bit = GPIO_BIT(offset);
@@ -364,6 +446,27 @@ static struct irq_chip aspeed_gpio_irqchip = {
.irq_set_type = aspeed_gpio_set_type,
};
+static void set_irq_valid_mask(struct aspeed_gpio *gpio)
+{
+ const struct aspeed_bank_props *props = gpio->config->props;
+
+ while (!is_bank_props_sentinel(props)) {
+ unsigned int offset;
+
+ /* Pretty crummy approach, but similar to GPIO core */
+ for_each_clear_bit(offset, &props->input, 32) {
+ unsigned int i = props->bank * 32 + offset;
+
+ if (i >= gpio->config->nr_gpios)
+ break;
+
+ clear_bit(i, gpio->chip.irq_valid_mask);
+ }
+
+ props++;
+ }
+}
+
static int aspeed_gpio_setup_irqs(struct aspeed_gpio *gpio,
struct platform_device *pdev)
{
@@ -375,6 +478,8 @@ static int aspeed_gpio_setup_irqs(struct aspeed_gpio *gpio,
gpio->irq = rc;
+ set_irq_valid_mask(gpio);
+
rc = gpiochip_irqchip_add(&gpio->chip, &aspeed_gpio_irqchip,
0, handle_bad_irq, IRQ_TYPE_NONE);
if (rc) {
@@ -390,6 +495,9 @@ static int aspeed_gpio_setup_irqs(struct aspeed_gpio *gpio,
static int aspeed_gpio_request(struct gpio_chip *chip, unsigned int offset)
{
+ if (!have_gpio(gpiochip_get_data(chip), offset))
+ return -ENODEV;
+
return pinctrl_request_gpio(chip->base + offset);
}
@@ -398,8 +506,46 @@ static void aspeed_gpio_free(struct gpio_chip *chip, unsigned int offset)
pinctrl_free_gpio(chip->base + offset);
}
+/*
+ * Any banks not specified in a struct aspeed_bank_props array are assumed to
+ * have the properties:
+ *
+ * { .input = 0xffffffff, .output = 0xffffffff }
+ */
+
+static const struct aspeed_bank_props ast2400_bank_props[] = {
+ /* input output */
+ { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */
+ { 6, 0x0000000f, 0x0fffff0f }, /* Y/Z/AA/AB, two 4-GPIO holes */
+ { },
+};
+
+static const struct aspeed_gpio_config ast2400_config =
+ /* 220 for simplicity, really 216 with two 4-GPIO holes, four at end */
+ { .nr_gpios = 220, .props = ast2400_bank_props, };
+
+static const struct aspeed_bank_props ast2500_bank_props[] = {
+ /* input output */
+ { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */
+ { 6, 0x0fffffff, 0x0fffffff }, /* Y/Z/AA/AB, 4-GPIO hole */
+ { 7, 0x000000ff, 0x000000ff }, /* AC */
+ { },
+};
+
+static const struct aspeed_gpio_config ast2500_config =
+ /* 232 for simplicity, actual number is 228 (4-GPIO hole in GPIOAB) */
+ { .nr_gpios = 232, .props = ast2500_bank_props, };
+
+static const struct of_device_id aspeed_gpio_of_table[] = {
+ { .compatible = "aspeed,ast2400-gpio", .data = &ast2400_config, },
+ { .compatible = "aspeed,ast2500-gpio", .data = &ast2500_config, },
+ {}
+};
+MODULE_DEVICE_TABLE(of, aspeed_gpio_of_table);
+
static int __init aspeed_gpio_probe(struct platform_device *pdev)
{
+ const struct of_device_id *gpio_id;
struct aspeed_gpio *gpio;
struct resource *res;
int rc;
@@ -415,8 +561,13 @@ static int __init aspeed_gpio_probe(struct platform_device *pdev)
spin_lock_init(&gpio->lock);
- gpio->chip.ngpio = ARRAY_SIZE(aspeed_gpio_banks) * 32;
+ gpio_id = of_match_node(aspeed_gpio_of_table, pdev->dev.of_node);
+ if (!gpio_id)
+ return -EINVAL;
+ gpio->config = gpio_id->data;
+
+ gpio->chip.ngpio = gpio->config->nr_gpios;
gpio->chip.parent = &pdev->dev;
gpio->chip.direction_input = aspeed_gpio_dir_in;
gpio->chip.direction_output = aspeed_gpio_dir_out;
@@ -427,6 +578,7 @@ static int __init aspeed_gpio_probe(struct platform_device *pdev)
gpio->chip.set = aspeed_gpio_set;
gpio->chip.label = dev_name(&pdev->dev);
gpio->chip.base = -1;
+ gpio->chip.irq_need_valid_mask = true;
rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
if (rc < 0)
@@ -435,13 +587,6 @@ static int __init aspeed_gpio_probe(struct platform_device *pdev)
return aspeed_gpio_setup_irqs(gpio, pdev);
}
-static const struct of_device_id aspeed_gpio_of_table[] = {
- { .compatible = "aspeed,ast2400-gpio" },
- { .compatible = "aspeed,ast2500-gpio" },
- {}
-};
-MODULE_DEVICE_TABLE(of, aspeed_gpio_of_table);
-
static struct platform_driver aspeed_gpio_driver = {
.driver = {
.name = KBUILD_MODNAME,
--
2.9.3
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] gpio: aspeed: Add banks Y, Z, AA, AB and AC
2017-01-23 5:26 ` [PATCH 2/2] gpio: aspeed: Add banks Y, Z, AA, AB and AC Andrew Jeffery
@ 2017-01-23 6:47 ` kbuild test robot
2017-01-23 6:59 ` kbuild test robot
1 sibling, 0 replies; 6+ messages in thread
From: kbuild test robot @ 2017-01-23 6:47 UTC (permalink / raw)
To: Andrew Jeffery
Cc: kbuild-all, Linus Walleij, Andrew Jeffery, Joel Stanley,
linux-gpio, linux-kernel, openbmc
[-- Attachment #1: Type: text/plain, Size: 4262 bytes --]
Hi Andrew,
[auto build test ERROR on gpio/for-next]
[also build test ERROR on v4.10-rc5 next-20170123]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Andrew-Jeffery/gpio-aspeed-Implement-banks-Y-Z-AA-AB-and-AC/20170123-134930
base: https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio.git for-next
config: i386-allmodconfig (attached as .config)
compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
All error/warnings (new ones prefixed by >>):
In file included from include/linux/kernel.h:10:0,
from include/linux/list.h:8,
from include/linux/module.h:9,
from drivers/gpio/gpio-aspeed.c:12:
drivers/gpio/gpio-aspeed.c: In function 'set_irq_valid_mask':
>> include/linux/bitops.h:50:35: error: passing argument 1 of 'find_first_zero_bit' from incompatible pointer type [-Werror=incompatible-pointer-types]
for ((bit) = find_first_zero_bit((addr), (size)); \
^
>> drivers/gpio/gpio-aspeed.c:457:3: note: in expansion of macro 'for_each_clear_bit'
for_each_clear_bit(offset, &props->input, 32) {
^~~~~~~~~~~~~~~~~~
In file included from arch/x86/include/asm/bitops.h:509:0,
from include/linux/bitops.h:36,
from include/linux/kernel.h:10,
from include/linux/list.h:8,
from include/linux/module.h:9,
from drivers/gpio/gpio-aspeed.c:12:
include/asm-generic/bitops/find.h:53:22: note: expected 'const long unsigned int *' but argument is of type 'const u32 * {aka const unsigned int *}'
extern unsigned long find_first_zero_bit(const unsigned long *addr,
^~~~~~~~~~~~~~~~~~~
In file included from include/linux/kernel.h:10:0,
from include/linux/list.h:8,
from include/linux/module.h:9,
from drivers/gpio/gpio-aspeed.c:12:
>> include/linux/bitops.h:52:34: error: passing argument 1 of 'find_next_zero_bit' from incompatible pointer type [-Werror=incompatible-pointer-types]
(bit) = find_next_zero_bit((addr), (size), (bit) + 1))
^
>> drivers/gpio/gpio-aspeed.c:457:3: note: in expansion of macro 'for_each_clear_bit'
for_each_clear_bit(offset, &props->input, 32) {
^~~~~~~~~~~~~~~~~~
In file included from arch/x86/include/asm/bitops.h:509:0,
from include/linux/bitops.h:36,
from include/linux/kernel.h:10,
from include/linux/list.h:8,
from include/linux/module.h:9,
from drivers/gpio/gpio-aspeed.c:12:
include/asm-generic/bitops/find.h:28:22: note: expected 'const long unsigned int *' but argument is of type 'const u32 * {aka const unsigned int *}'
extern unsigned long find_next_zero_bit(const unsigned long *addr, unsigned
^~~~~~~~~~~~~~~~~~
cc1: some warnings being treated as errors
vim +/for_each_clear_bit +457 drivers/gpio/gpio-aspeed.c
441 static struct irq_chip aspeed_gpio_irqchip = {
442 .name = "aspeed-gpio",
443 .irq_ack = aspeed_gpio_irq_ack,
444 .irq_mask = aspeed_gpio_irq_mask,
445 .irq_unmask = aspeed_gpio_irq_unmask,
446 .irq_set_type = aspeed_gpio_set_type,
447 };
448
449 static void set_irq_valid_mask(struct aspeed_gpio *gpio)
450 {
451 const struct aspeed_bank_props *props = gpio->config->props;
452
453 while (!is_bank_props_sentinel(props)) {
454 unsigned int offset;
455
456 /* Pretty crummy approach, but similar to GPIO core */
> 457 for_each_clear_bit(offset, &props->input, 32) {
458 unsigned int i = props->bank * 32 + offset;
459
460 if (i >= gpio->config->nr_gpios)
461 break;
462
463 clear_bit(i, gpio->chip.irq_valid_mask);
464 }
465
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 57922 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] gpio: aspeed: Add banks Y, Z, AA, AB and AC
2017-01-23 5:26 ` [PATCH 2/2] gpio: aspeed: Add banks Y, Z, AA, AB and AC Andrew Jeffery
2017-01-23 6:47 ` kbuild test robot
@ 2017-01-23 6:59 ` kbuild test robot
1 sibling, 0 replies; 6+ messages in thread
From: kbuild test robot @ 2017-01-23 6:59 UTC (permalink / raw)
To: Andrew Jeffery
Cc: kbuild-all, Linus Walleij, Andrew Jeffery, Joel Stanley,
linux-gpio, linux-kernel, openbmc
[-- Attachment #1: Type: text/plain, Size: 5594 bytes --]
Hi Andrew,
[auto build test ERROR on gpio/for-next]
[also build test ERROR on v4.10-rc5 next-20170123]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Andrew-Jeffery/gpio-aspeed-Implement-banks-Y-Z-AA-AB-and-AC/20170123-134930
base: https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio.git for-next
config: sparc64-allmodconfig (attached as .config)
compiler: sparc64-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=sparc64
All errors (new ones prefixed by >>):
In file included from arch/sparc/include/asm/bitops_64.h:53:0,
from arch/sparc/include/asm/bitops.h:4,
from include/linux/bitops.h:36,
from include/linux/kernel.h:10,
from include/linux/list.h:8,
from include/linux/module.h:9,
from drivers/gpio/gpio-aspeed.c:12:
drivers/gpio/gpio-aspeed.c: In function 'set_irq_valid_mask':
>> include/asm-generic/bitops/find.h:58:60: error: passing argument 1 of 'find_next_zero_bit' from incompatible pointer type [-Werror=incompatible-pointer-types]
#define find_first_zero_bit(addr, size) find_next_zero_bit((addr), (size), 0)
^
include/linux/bitops.h:50:15: note: in expansion of macro 'find_first_zero_bit'
for ((bit) = find_first_zero_bit((addr), (size)); \
^~~~~~~~~~~~~~~~~~~
drivers/gpio/gpio-aspeed.c:457:3: note: in expansion of macro 'for_each_clear_bit'
for_each_clear_bit(offset, &props->input, 32) {
^~~~~~~~~~~~~~~~~~
include/asm-generic/bitops/find.h:28:22: note: expected 'const long unsigned int *' but argument is of type 'const u32 * {aka const unsigned int *}'
extern unsigned long find_next_zero_bit(const unsigned long *addr, unsigned
^~~~~~~~~~~~~~~~~~
In file included from include/linux/kernel.h:10:0,
from include/linux/list.h:8,
from include/linux/module.h:9,
from drivers/gpio/gpio-aspeed.c:12:
include/linux/bitops.h:52:34: error: passing argument 1 of 'find_next_zero_bit' from incompatible pointer type [-Werror=incompatible-pointer-types]
(bit) = find_next_zero_bit((addr), (size), (bit) + 1))
^
drivers/gpio/gpio-aspeed.c:457:3: note: in expansion of macro 'for_each_clear_bit'
for_each_clear_bit(offset, &props->input, 32) {
^~~~~~~~~~~~~~~~~~
In file included from arch/sparc/include/asm/bitops_64.h:53:0,
from arch/sparc/include/asm/bitops.h:4,
from include/linux/bitops.h:36,
from include/linux/kernel.h:10,
from include/linux/list.h:8,
from include/linux/module.h:9,
from drivers/gpio/gpio-aspeed.c:12:
include/asm-generic/bitops/find.h:28:22: note: expected 'const long unsigned int *' but argument is of type 'const u32 * {aka const unsigned int *}'
extern unsigned long find_next_zero_bit(const unsigned long *addr, unsigned
^~~~~~~~~~~~~~~~~~
cc1: some warnings being treated as errors
vim +/find_next_zero_bit +58 include/asm-generic/bitops/find.h
708ff2a0 Akinobu Mita 2010-09-29 42 extern unsigned long find_first_bit(const unsigned long *addr,
708ff2a0 Akinobu Mita 2010-09-29 43 unsigned long size);
708ff2a0 Akinobu Mita 2010-09-29 44
708ff2a0 Akinobu Mita 2010-09-29 45 /**
708ff2a0 Akinobu Mita 2010-09-29 46 * find_first_zero_bit - find the first cleared bit in a memory region
708ff2a0 Akinobu Mita 2010-09-29 47 * @addr: The address to start the search at
ec778edf Cody P Schafer 2013-11-12 48 * @size: The maximum number of bits to search
708ff2a0 Akinobu Mita 2010-09-29 49 *
708ff2a0 Akinobu Mita 2010-09-29 50 * Returns the bit number of the first cleared bit.
ec778edf Cody P Schafer 2013-11-12 51 * If no bits are zero, returns @size.
708ff2a0 Akinobu Mita 2010-09-29 52 */
708ff2a0 Akinobu Mita 2010-09-29 53 extern unsigned long find_first_zero_bit(const unsigned long *addr,
708ff2a0 Akinobu Mita 2010-09-29 54 unsigned long size);
708ff2a0 Akinobu Mita 2010-09-29 55 #else /* CONFIG_GENERIC_FIND_FIRST_BIT */
708ff2a0 Akinobu Mita 2010-09-29 56
c7f612cd Akinobu Mita 2006-03-26 57 #define find_first_bit(addr, size) find_next_bit((addr), (size), 0)
c7f612cd Akinobu Mita 2006-03-26 @58 #define find_first_zero_bit(addr, size) find_next_zero_bit((addr), (size), 0)
c7f612cd Akinobu Mita 2006-03-26 59
708ff2a0 Akinobu Mita 2010-09-29 60 #endif /* CONFIG_GENERIC_FIND_FIRST_BIT */
708ff2a0 Akinobu Mita 2010-09-29 61
c7f612cd Akinobu Mita 2006-03-26 62 #endif /*_ASM_GENERIC_BITOPS_FIND_H_ */
:::::: The code at line 58 was first introduced by commit
:::::: c7f612cdf091def01454e7e132c7d7a3f419fbc4 [PATCH] bitops: generic find_{next,first}{,_zero}_bit()
:::::: TO: Akinobu Mita <mita@miraclelinux.com>
:::::: CC: Linus Torvalds <torvalds@g5.osdl.org>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] gpio: aspeed: Make bank names strings
2017-01-23 5:26 ` [PATCH 1/2] gpio: aspeed: Make bank names strings Andrew Jeffery
@ 2017-01-26 13:32 ` Linus Walleij
0 siblings, 0 replies; 6+ messages in thread
From: Linus Walleij @ 2017-01-26 13:32 UTC (permalink / raw)
To: Andrew Jeffery; +Cc: Joel Stanley, linux-gpio, linux-kernel, OpenBMC Maillist
On Mon, Jan 23, 2017 at 6:26 AM, Andrew Jeffery <andrew@aj.id.au> wrote:
> From: Joel Stanley <joel@jms.id.au>
>
> The Aspeed SoCs have more GPIOs than can be represented with A-Z. The
> documentation uses two letter names such as AA and AB, so make the names
> a three-character array in the bank struct to accommodate this.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Patch applied.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2017-01-26 13:32 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-01-23 5:26 [PATCH 0/2] gpio: aspeed: Implement banks Y, Z, AA, AB and AC Andrew Jeffery
2017-01-23 5:26 ` [PATCH 1/2] gpio: aspeed: Make bank names strings Andrew Jeffery
2017-01-26 13:32 ` Linus Walleij
2017-01-23 5:26 ` [PATCH 2/2] gpio: aspeed: Add banks Y, Z, AA, AB and AC Andrew Jeffery
2017-01-23 6:47 ` kbuild test robot
2017-01-23 6:59 ` kbuild test robot
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