[PATCH v2 00/17] ARM: Initial Actions Semi S500 and S900 enablement

[PATCH v2 00/17] ARM: Initial Actions Semi S500 and S900 enablement

[Andreas Färber]

Hello,

This series adds initial support for Actions Semiconductor S500 (ARMv7) and
S900 (ARMv8) SoCs.

In addition to earlycon serial output, v2 includes a serial console driver RFC.
Guitar output is coming further along thanks to a new timer implementation, but
is still earlycon only - to be investigated. Bubblegum-96 reaches an initrd,
but a small part of the serial output just before is lost (visible in dmesg).

https://github.com/afaerber/linux/commits/bg96-next

Booting from U-Boot is straightforward on both boards:

https://en.opensuse.org/HCL:Guitar
https://en.opensuse.org/HCL:Bubblegum-96

Have a lot of fun!

Cheers,
Andreas

v1 -> v2:
* S900 DT fixes (Mark)
* Kconfig name changes (Arnd)
* Bubblegum-96 .dts rename
* Vendor prefix rename
* Minor cleanups
* Add serial driver
* Add MAINTAINERS section
* Use SPDX-License-Identifier in DT (Rob)
* Add clocksource driver

Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robh@kernel.org>
Cc: mp-cs@actions-semi.com
Cc: 96boards@ucrobotics.com
Cc: support@lemaker.org
Cc: devicetree@vger.kernel.org

Andreas Färber (17):
  dt-bindings: Add vendor prefix for Actions Semi
  dt-bindings: arm: Document Actions Semi S500
  dt-bindings: timer: Document Owl timer
  clocksource: Add Owl timer
  ARM: Prepare Actions Semi S500
  ARM64: Prepare Actions Semi S900
  dt-bindings: serial: Document Actions Semi Owl UARTs
  tty: serial: Add Actions Semi Owl UART earlycon
  Documentation: kernel-parameters: Document owl earlycon
  ARM: dts: Add Actions Semi S500 and LeMaker Guitar
  dt-bindings: Add vendor prefix for uCRobotics
  dt-bindings: arm: Document Actions Semi S900
  ARM64: dts: Add Actions Semi S900 and Bubblegum-96
  MAINTAINERS: Add Actions Semi Owl section
  tty: serial: owl: Implement console driver
  ARM64: dts: actions: s900-bubblegum-96: Add fake uart5 clk
  ARM: dts: s500-guitar-bb-rev-b: Add fake uart3 clock

 Documentation/admin-guide/kernel-parameters.txt    |   6 +
 Documentation/devicetree/bindings/arm/actions.txt  |  39 ++
 .../bindings/serial/actions,owl-uart.txt           |  16 +
 .../bindings/timer/actions,owl-timer.txt           |  16 +
 .../devicetree/bindings/vendor-prefixes.txt        |   2 +
 MAINTAINERS                                        |  10 +
 arch/arm/Kconfig                                   |   2 +
 arch/arm/Makefile                                  |   1 +
 arch/arm/boot/dts/Makefile                         |   2 +
 arch/arm/boot/dts/s500-guitar-bb-rev-b.dts         |  33 +
 arch/arm/boot/dts/s500-guitar.dtsi                 |  20 +
 arch/arm/boot/dts/s500.dtsi                        | 135 ++++
 arch/arm/mach-actions/Kconfig                      |  10 +
 arch/arm/mach-actions/Makefile                     |   1 +
 arch/arm/mach-actions/owl.c                        |  28 +
 arch/arm64/Kconfig.platforms                       |   5 +
 arch/arm64/boot/dts/Makefile                       |   1 +
 arch/arm64/boot/dts/actions/Makefile               |   5 +
 arch/arm64/boot/dts/actions/s900-bubblegum-96.dts  |  38 ++
 arch/arm64/boot/dts/actions/s900.dtsi              | 109 ++++
 drivers/clocksource/Kconfig                        |   7 +
 drivers/clocksource/Makefile                       |   1 +
 drivers/clocksource/owl-timer.c                    | 146 +++++
 drivers/tty/serial/Kconfig                         |  19 +
 drivers/tty/serial/Makefile                        |   1 +
 drivers/tty/serial/owl-uart.c                      | 707 +++++++++++++++++++++
 include/uapi/linux/serial_core.h                   |   3 +
 27 files changed, 1363 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/actions.txt
 create mode 100644 Documentation/devicetree/bindings/serial/actions,owl-uart.txt
 create mode 100644 Documentation/devicetree/bindings/timer/actions,owl-timer.txt
 create mode 100644 arch/arm/boot/dts/s500-guitar-bb-rev-b.dts
 create mode 100644 arch/arm/boot/dts/s500-guitar.dtsi
 create mode 100644 arch/arm/boot/dts/s500.dtsi
 create mode 100644 arch/arm/mach-actions/Kconfig
 create mode 100644 arch/arm/mach-actions/Makefile
 create mode 100644 arch/arm/mach-actions/owl.c
 create mode 100644 arch/arm64/boot/dts/actions/Makefile
 create mode 100644 arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
 create mode 100644 arch/arm64/boot/dts/actions/s900.dtsi
 create mode 100644 drivers/clocksource/owl-timer.c
 create mode 100644 drivers/tty/serial/owl-uart.c

-- 
2.10.2

[PATCH v2 01/17] dt-bindings: Add vendor prefix for Actions Semi

[Andreas Färber]

Actions Semiconductor was listed on NASDAQ as ACTS until Dec 16, 2016.

Cc: mp-cs@actions-semi.com
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 v1 -> v2:
 * Reverted from "acts" to "actions" (cf. IAP140 "mrvl" vs. "marvell")
 
 Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index a76b981..64f8469 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -6,6 +6,7 @@ using them to avoid name-space collisions.
 abcn	Abracon Corporation
 abilis	Abilis Systems
 active-semi	Active-Semi International Inc
+actions	Actions Semiconductor Co., Ltd.
 ad	Avionic Design GmbH
 adapteva	Adapteva, Inc.
 adh	AD Holdings Plc.
-- 
2.10.2

Re: [PATCH v2 01/17] dt-bindings: Add vendor prefix for Actions Semi

[Andreas Färber]

Am 24.02.2017 um 04:40 schrieb Andreas Färber:
> Actions Semiconductor was listed on NASDAQ as ACTS until Dec 16, 2016.
> 
> Cc: mp-cs@actions-semi.com
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> ---
>  v1 -> v2:
>  * Reverted from "acts" to "actions" (cf. IAP140 "mrvl" vs. "marvell")
>  
>  Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
> index a76b981..64f8469 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.txt
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
> @@ -6,6 +6,7 @@ using them to avoid name-space collisions.
>  abcn	Abracon Corporation
>  abilis	Abilis Systems
>  active-semi	Active-Semi International Inc
> +actions	Actions Semiconductor Co., Ltd.

If the use of "actions" gets ack'ed, I realize it should move one line up.

Regards,
Andreas

-- 
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)

Re: [PATCH v2 01/17] dt-bindings: Add vendor prefix for Actions Semi

[Rob Herring]

On Mon, Feb 27, 2017 at 03:57:19PM +0100, Andreas Färber wrote:
> Am 24.02.2017 um 04:40 schrieb Andreas Färber:
> > Actions Semiconductor was listed on NASDAQ as ACTS until Dec 16, 2016.
> > 
> > Cc: mp-cs@actions-semi.com
> > Signed-off-by: Andreas Färber <afaerber@suse.de>
> > ---
> >  v1 -> v2:
> >  * Reverted from "acts" to "actions" (cf. IAP140 "mrvl" vs. "marvell")
> >  
> >  Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
> > index a76b981..64f8469 100644
> > --- a/Documentation/devicetree/bindings/vendor-prefixes.txt
> > +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
> > @@ -6,6 +6,7 @@ using them to avoid name-space collisions.
> >  abcn	Abracon Corporation
> >  abilis	Abilis Systems
> >  active-semi	Active-Semi International Inc
> > +actions	Actions Semiconductor Co., Ltd.
> 
> If the use of "actions" gets ack'ed, I realize it should move one line up.

With that fix,

Acked-by: Rob Herring <robh@kernel.org>

[PATCH v2 02/17] dt-bindings: arm: Document Actions Semi S500

[Andreas Färber]

The Actions Semi S500 is a quad-core ARM Cortex-A9 SoC.
The LeMaker Guitar is an SODIMM-format module with that SoC.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 v1 -> v2:
 * Adopted "actions" vendor prefix
 * Extended text
 
 Documentation/devicetree/bindings/arm/actions.txt | 24 +++++++++++++++++++++++
 1 file changed, 24 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/actions.txt

diff --git a/Documentation/devicetree/bindings/arm/actions.txt b/Documentation/devicetree/bindings/arm/actions.txt
new file mode 100644
index 0000000..1d3782e
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/actions.txt
@@ -0,0 +1,24 @@
+Actions Semi platforms device tree bindings
+-------------------------------------------
+
+
+S500 SoC
+========
+
+Required root node properties:
+
+ - compatible :  must contain "actions,s500"
+
+
+Modules:
+
+Root node property compatible must contain, depending on module:
+
+ - LeMaker Guitar: "lemaker,guitar"
+
+
+Boards:
+
+Root node property compatible must contain, depending on board:
+
+ - LeMaker Guitar Base Board rev. B: "lemaker,guitar-bb-rev-b", "lemaker,guitar"
-- 
2.10.2

Re: [PATCH v2 02/17] dt-bindings: arm: Document Actions Semi S500

[Rob Herring]

On Fri, Feb 24, 2017 at 04:40:40AM +0100, Andreas Färber wrote:
> The Actions Semi S500 is a quad-core ARM Cortex-A9 SoC.
> The LeMaker Guitar is an SODIMM-format module with that SoC.
> 
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> ---
>  v1 -> v2:
>  * Adopted "actions" vendor prefix
>  * Extended text
>  
>  Documentation/devicetree/bindings/arm/actions.txt | 24 +++++++++++++++++++++++
>  1 file changed, 24 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/actions.txt

Acked-by: Rob Herring <robh@kernel.org>

[RFC v2 03/17] dt-bindings: timer: Document Owl timer

[Andreas Färber]

The Actions Semi S500 SoC contains a timer block with two timers.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 v2: new
 
 .../devicetree/bindings/timer/actions,owl-timer.txt      | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/timer/actions,owl-timer.txt

diff --git a/Documentation/devicetree/bindings/timer/actions,owl-timer.txt b/Documentation/devicetree/bindings/timer/actions,owl-timer.txt
new file mode 100644
index 0000000..141bc7b
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/actions,owl-timer.txt
@@ -0,0 +1,16 @@
+Actions Semi Owl Timer
+
+Required properties:
+- compatible :  "actions,owl-timer"
+- reg        :  Offset and length of the register set for the device.
+- interrupts :  Should contain two timer interrupts.
+
+
+Example:
+
+		timer@b0168000 {
+			compatible = "actions,owl-timer";
+			reg = <0xb0168000 0x100>;
+			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+			             <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+		};
-- 
2.10.2

Re: [RFC v2 03/17] dt-bindings: timer: Document Owl timer

[Andreas Färber]

Am 24.02.2017 um 04:40 schrieb Andreas Färber:
> The Actions Semi S500 SoC contains a timer block with two timers.
> 
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> ---
>  v2: new

Sorry, script error: nothing particularly RFC here.

Regards,
Andreas

-- 
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)

Re: [RFC v2 03/17] dt-bindings: timer: Document Owl timer

[Andreas Färber]

Am 24.02.2017 um 04:40 schrieb Andreas Färber:
> The Actions Semi S500 SoC contains a timer block with two timers.
> 
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> ---
>  v2: new
>  
>  .../devicetree/bindings/timer/actions,owl-timer.txt      | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/timer/actions,owl-timer.txt
> 
> diff --git a/Documentation/devicetree/bindings/timer/actions,owl-timer.txt b/Documentation/devicetree/bindings/timer/actions,owl-timer.txt
> new file mode 100644
> index 0000000..141bc7b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/actions,owl-timer.txt
> @@ -0,0 +1,16 @@
> +Actions Semi Owl Timer
> +
> +Required properties:
> +- compatible :  "actions,owl-timer"
> +- reg        :  Offset and length of the register set for the device.
> +- interrupts :  Should contain two timer interrupts.
> +
> +
> +Example:
> +
> +		timer@b0168000 {
> +			compatible = "actions,owl-timer";
> +			reg = <0xb0168000 0x100>;
> +			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
> +			             <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> +		};

I need to modify these bindings for upcoming v3 in the following ways:

* "actions,s500-timer", "actions,owl-timer" to deal with S500 vs. S900
differences while keeping a single driver registration (or would two
registrations be preferred, dropping the second compatible? they do
share a common subset)

* Use named interrupts to deal with 2x 2Hz + 2x Timer vs. 4x Timer for
complete hardware description

Regards,
Andreas

-- 
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)

Re: [RFC v2 03/17] dt-bindings: timer: Document Owl timer

[Rob Herring]

On Mon, Feb 27, 2017 at 03:40:07PM +0100, Andreas Färber wrote:
> Am 24.02.2017 um 04:40 schrieb Andreas Färber:
> > The Actions Semi S500 SoC contains a timer block with two timers.
> > 
> > Signed-off-by: Andreas Färber <afaerber@suse.de>
> > ---
> >  v2: new
> >  
> >  .../devicetree/bindings/timer/actions,owl-timer.txt      | 16 ++++++++++++++++
> >  1 file changed, 16 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/timer/actions,owl-timer.txt
> > 
> > diff --git a/Documentation/devicetree/bindings/timer/actions,owl-timer.txt b/Documentation/devicetree/bindings/timer/actions,owl-timer.txt
> > new file mode 100644
> > index 0000000..141bc7b
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/timer/actions,owl-timer.txt
> > @@ -0,0 +1,16 @@
> > +Actions Semi Owl Timer
> > +
> > +Required properties:
> > +- compatible :  "actions,owl-timer"
> > +- reg        :  Offset and length of the register set for the device.
> > +- interrupts :  Should contain two timer interrupts.
> > +
> > +
> > +Example:
> > +
> > +		timer@b0168000 {
> > +			compatible = "actions,owl-timer";
> > +			reg = <0xb0168000 0x100>;
> > +			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
> > +			             <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> > +		};
> 
> I need to modify these bindings for upcoming v3 in the following ways:
> 
> * "actions,s500-timer", "actions,owl-timer" to deal with S500 vs. S900
> differences while keeping a single driver registration (or would two
> registrations be preferred, dropping the second compatible? they do
> share a common subset)

The former is fine.

> 
> * Use named interrupts to deal with 2x 2Hz + 2x Timer vs. 4x Timer for
> complete hardware description

The compatible should imply this difference.

Rob

[PATCH v2 04/17] clocksource: Add Owl timer

[Andreas Färber]

Implement clocksource and clockevents for Actions Semi S500.

Based on LeMaker linux-actions tree.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 v2: new
 
 drivers/clocksource/Kconfig     |   7 ++
 drivers/clocksource/Makefile    |   1 +
 drivers/clocksource/owl-timer.c | 146 ++++++++++++++++++++++++++++++++++++++++
 3 files changed, 154 insertions(+)
 create mode 100644 drivers/clocksource/owl-timer.c

diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 3356ab8..2551365 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -107,6 +107,13 @@ config ORION_TIMER
 	help
 	  Enables the support for the Orion timer driver
 
+config OWL_TIMER
+	bool "Owl timer driver" if COMPILE_TEST
+	depends on GENERIC_CLOCKEVENTS
+	select CLKSRC_MMIO
+	help
+	  Enables the support for the Actions Semi Owl timer driver.
+
 config SUN4I_TIMER
 	bool "Sun4i timer driver" if COMPILE_TEST
 	depends on GENERIC_CLOCKEVENTS
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index d227d13..801b65a 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -53,6 +53,7 @@ obj-$(CONFIG_CLKSRC_PISTACHIO)	+= time-pistachio.o
 obj-$(CONFIG_CLKSRC_TI_32K)	+= timer-ti-32k.o
 obj-$(CONFIG_CLKSRC_NPS)	+= timer-nps.o
 obj-$(CONFIG_OXNAS_RPS_TIMER)	+= timer-oxnas-rps.o
+obj-$(CONFIG_OWL_TIMER)		+= owl-timer.o
 
 obj-$(CONFIG_ARC_TIMERS)		+= arc_timer.o
 obj-$(CONFIG_ARM_ARCH_TIMER)		+= arm_arch_timer.o
diff --git a/drivers/clocksource/owl-timer.c b/drivers/clocksource/owl-timer.c
new file mode 100644
index 0000000..e218ad7
--- /dev/null
+++ b/drivers/clocksource/owl-timer.c
@@ -0,0 +1,146 @@
+/*
+ * Actions Semi Owl timer
+ *
+ * Copyright 2012 Actions Semi Inc.
+ * Author: Actions Semi, Inc.
+ *
+ * Copyright (c) 2017 SUSE Linux GmbH
+ * Author: Andreas Färber
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/clockchips.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/irqreturn.h>
+#include <linux/sched_clock.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+
+#define OWL_T0_CTL		0x08
+#define OWL_T0_CMP		0x0c
+#define OWL_T0_VAL		0x10
+#define OWL_T1_CTL		0x14
+#define OWL_T1_CMP		0x18
+#define OWL_T1_VAL		0x1c
+
+#define OWL_Tx_CTL_INTEN	(1 << 1)
+#define OWL_Tx_CTL_EN		(1 << 2)
+
+static void __iomem *owl_timer_base;
+
+static u64 notrace owl_timer_sched_read(void)
+{
+	return (u64)readl(owl_timer_base + OWL_T0_VAL);
+}
+
+static int owl_timer_set_state_shutdown(struct clock_event_device *evt)
+{
+	writel(0, owl_timer_base + OWL_T1_CTL);
+
+	return 0;
+}
+
+static int owl_timer_set_state_oneshot(struct clock_event_device *evt)
+{
+	writel(0, owl_timer_base + OWL_T1_CTL);
+	writel(0, owl_timer_base + OWL_T1_VAL);
+	writel(0, owl_timer_base + OWL_T1_CMP);
+
+	return 0;
+}
+
+static int owl_timer_tick_resume(struct clock_event_device *evt)
+{
+	return 0;
+}
+
+static int owl_timer_set_next_event(unsigned long evt,
+				    struct clock_event_device *ev)
+{
+	writel(0, owl_timer_base + OWL_T1_CTL);
+
+	writel(0, owl_timer_base + OWL_T1_VAL);
+	writel(evt, owl_timer_base + OWL_T1_CMP);
+
+	writel(OWL_Tx_CTL_EN | OWL_Tx_CTL_INTEN, owl_timer_base + OWL_T1_CTL);
+
+	return 0;
+}
+
+static struct clock_event_device owl_clockevent = {
+	.name			= "owl_tick",
+	.rating			= 200,
+	.features		= CLOCK_EVT_FEAT_ONESHOT,
+	.set_state_shutdown	= owl_timer_set_state_shutdown,
+	.set_state_oneshot	= owl_timer_set_state_oneshot,
+	.tick_resume		= owl_timer_tick_resume,
+	.set_next_event		= owl_timer_set_next_event,
+};
+
+static irqreturn_t owl_timer_interrupt(int irq, void *dev_id)
+{
+	struct clock_event_device *evt = (struct clock_event_device *)dev_id;
+
+	evt->event_handler(evt);
+
+	return IRQ_HANDLED;
+}
+
+static struct irqaction owl_timer_irq = {
+	.name = "owl-timer",
+	.flags = IRQF_TIMER,
+	.handler = owl_timer_interrupt,
+	.dev_id = &owl_clockevent,
+};
+
+static int __init owl_timer_init(struct device_node *node)
+{
+	const unsigned long rate = 24000000;
+	int irq1, ret;
+
+	owl_timer_base = of_io_request_and_map(node, 0, "owl-timer");
+	if (IS_ERR(owl_timer_base)) {
+		pr_err("Can't map timer registers");
+		return -ENXIO;
+	}
+
+	irq1 = irq_of_parse_and_map(node, 1);
+	if (irq1 <= 0) {
+		pr_err("Can't parse timer1 IRQ");
+		return -EINVAL;
+	}
+
+	writel(0, owl_timer_base + OWL_T0_CTL);
+	writel(0, owl_timer_base + OWL_T0_VAL);
+	writel(0, owl_timer_base + OWL_T0_CMP);
+	writel(OWL_Tx_CTL_EN, owl_timer_base + OWL_T0_CTL);
+
+	sched_clock_register(owl_timer_sched_read, 32, rate);
+	clocksource_mmio_init(owl_timer_base + OWL_T0_VAL, node->name,
+			      rate, 200, 32, clocksource_mmio_readl_up);
+
+	writel(0, owl_timer_base + OWL_T1_CTL);
+	writel(0, owl_timer_base + OWL_T1_VAL);
+	writel(0, owl_timer_base + OWL_T1_CMP);
+
+	ret = setup_irq(irq1, &owl_timer_irq);
+	if (ret) {
+		pr_warn("failed to setup irq %d\n", irq1);
+		return ret;
+	}
+
+	owl_clockevent.cpumask = cpumask_of(0);
+	owl_clockevent.irq = irq1;
+
+	clockevents_config_and_register(&owl_clockevent, rate,
+					0xf, 0xffffffff);
+
+	return 0;
+}
+CLOCKSOURCE_OF_DECLARE(owl, "actions,owl-timer", owl_timer_init);
-- 
2.10.2

Re: [PATCH v2 04/17] clocksource: Add Owl timer

[Daniel Lezcano]

On Fri, Feb 24, 2017 at 04:40:42AM +0100, Andreas Färber wrote:
> Implement clocksource and clockevents for Actions Semi S500.
> 
> Based on LeMaker linux-actions tree.
> 
> Signed-off-by: Andreas Färber <afaerber@suse.de>

As this is a new driver, please give some technical information about the
driver itself and a pointer to documentation if it is publicly available.

[ ... ]

> +#define OWL_T0_CMP		0x0c
> +#define OWL_T0_VAL		0x10
> +#define OWL_T1_CTL		0x14
> +#define OWL_T1_CMP		0x18
> +#define OWL_T1_VAL		0x1c
> +
> +#define OWL_Tx_CTL_INTEN	(1 << 1)
> +#define OWL_Tx_CTL_EN		(1 << 2)

s/(1 << 1)/BIT(1)/
s/(1 << 2)/BIT(2)/

> +
> +static void __iomem *owl_timer_base;
> +
> +static u64 notrace owl_timer_sched_read(void)
> +{
> +	return (u64)readl(owl_timer_base + OWL_T0_VAL);
> +}
> +
> +static int owl_timer_set_state_shutdown(struct clock_event_device *evt)
> +{
> +	writel(0, owl_timer_base + OWL_T1_CTL);
> +
> +	return 0;
> +}
> +
> +static int owl_timer_set_state_oneshot(struct clock_event_device *evt)
> +{
> +	writel(0, owl_timer_base + OWL_T1_CTL);
> +	writel(0, owl_timer_base + OWL_T1_VAL);
> +	writel(0, owl_timer_base + OWL_T1_CMP);
> +
> +	return 0;
> +}
> +
> +static int owl_timer_tick_resume(struct clock_event_device *evt)
> +{
> +	return 0;
> +}
> +
> +static int owl_timer_set_next_event(unsigned long evt,
> +				    struct clock_event_device *ev)
> +{
> +	writel(0, owl_timer_base + OWL_T1_CTL);
> +
> +	writel(0, owl_timer_base + OWL_T1_VAL);
> +	writel(evt, owl_timer_base + OWL_T1_CMP);
> +
> +	writel(OWL_Tx_CTL_EN | OWL_Tx_CTL_INTEN, owl_timer_base + OWL_T1_CTL);
> +
> +	return 0;
> +}
> +
> +static struct clock_event_device owl_clockevent = {
> +	.name			= "owl_tick",
> +	.rating			= 200,
> +	.features		= CLOCK_EVT_FEAT_ONESHOT,

Did you consider adding CLOCK_EVT_FEAT_DYNIRQ ?

> +	.set_state_shutdown	= owl_timer_set_state_shutdown,
> +	.set_state_oneshot	= owl_timer_set_state_oneshot,
> +	.tick_resume		= owl_timer_tick_resume,
> +	.set_next_event		= owl_timer_set_next_event,
> +};
> +
> +static irqreturn_t owl_timer_interrupt(int irq, void *dev_id)
> +{
> +	struct clock_event_device *evt = (struct clock_event_device *)dev_id;
> +
> +	evt->event_handler(evt);
> +
> +	return IRQ_HANDLED;
> +}
> +
> +static struct irqaction owl_timer_irq = {
> +	.name = "owl-timer",
> +	.flags = IRQF_TIMER,
> +	.handler = owl_timer_interrupt,
> +	.dev_id = &owl_clockevent,
> +};
> +
> +static int __init owl_timer_init(struct device_node *node)
> +{
> +	const unsigned long rate = 24000000;

Use DT, either use clock-frequency or a clock ref.

> +	int irq1, ret;
> +
> +	owl_timer_base = of_io_request_and_map(node, 0, "owl-timer");
> +	if (IS_ERR(owl_timer_base)) {
> +		pr_err("Can't map timer registers");
> +		return -ENXIO;

Why not PTR_ERR(owl_timer_base) ?

> +	}
> +
> +	irq1 = irq_of_parse_and_map(node, 1);
> +	if (irq1 <= 0) {
> +		pr_err("Can't parse timer1 IRQ");
> +		return -EINVAL;
> +	}
> +
> +	writel(0, owl_timer_base + OWL_T0_CTL);
> +	writel(0, owl_timer_base + OWL_T0_VAL);
> +	writel(0, owl_timer_base + OWL_T0_CMP);
> +	writel(OWL_Tx_CTL_EN, owl_timer_base + OWL_T0_CTL);

Please factor out these calls into a function.

> +
> +	sched_clock_register(owl_timer_sched_read, 32, rate);
> +	clocksource_mmio_init(owl_timer_base + OWL_T0_VAL, node->name,
> +			      rate, 200, 32, clocksource_mmio_readl_up);
> +
> +	writel(0, owl_timer_base + OWL_T1_CTL);
> +	writel(0, owl_timer_base + OWL_T1_VAL);
> +	writel(0, owl_timer_base + OWL_T1_CMP);
> +
> +	ret = setup_irq(irq1, &owl_timer_irq);
> +	if (ret) {
> +		pr_warn("failed to setup irq %d\n", irq1);
> +		return ret;
> +	}

s/setup_irq/request_irq/

> +
> +	owl_clockevent.cpumask = cpumask_of(0);
> +	owl_clockevent.irq = irq1;
> +
> +	clockevents_config_and_register(&owl_clockevent, rate,
> +					0xf, 0xffffffff);
> +
> +	return 0;
> +}
> +CLOCKSOURCE_OF_DECLARE(owl, "actions,owl-timer", owl_timer_init);

Thanks !

  -- Daniel 

-- 

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Re: [PATCH v2 04/17] clocksource: Add Owl timer

[Andreas Färber]

Am 24.02.2017 um 23:29 schrieb Daniel Lezcano:
> On Fri, Feb 24, 2017 at 04:40:42AM +0100, Andreas Färber wrote:
>> Implement clocksource and clockevents for Actions Semi S500.
>>
>> Based on LeMaker linux-actions tree.
>>
>> Signed-off-by: Andreas Färber <afaerber@suse.de>
> 
> As this is a new driver, please give some technical information about the
> driver itself and a pointer to documentation if it is publicly available.

What technical information would that be? Which of the timers we use as
clock source vs. clock events?

The only public documentation beyond the source tree mentioned is here:

http://www.lemaker.org/product-guitar-download-29.html (section 3.4)

>> +#define OWL_Tx_CTL_INTEN	(1 << 1)
>> +#define OWL_Tx_CTL_EN		(1 << 2)
> 
> s/(1 << 1)/BIT(1)/
> s/(1 << 2)/BIT(2)/

OK

>> +
>> +static void __iomem *owl_timer_base;
>> +
>> +static u64 notrace owl_timer_sched_read(void)
>> +{
>> +	return (u64)readl(owl_timer_base + OWL_T0_VAL);
>> +}
>> +
>> +static int owl_timer_set_state_shutdown(struct clock_event_device *evt)
>> +{
>> +	writel(0, owl_timer_base + OWL_T1_CTL);
>> +
>> +	return 0;
>> +}
>> +
>> +static int owl_timer_set_state_oneshot(struct clock_event_device *evt)
>> +{
>> +	writel(0, owl_timer_base + OWL_T1_CTL);
>> +	writel(0, owl_timer_base + OWL_T1_VAL);
>> +	writel(0, owl_timer_base + OWL_T1_CMP);
>> +
>> +	return 0;
>> +}
>> +
>> +static int owl_timer_tick_resume(struct clock_event_device *evt)
>> +{
>> +	return 0;
>> +}
>> +
>> +static int owl_timer_set_next_event(unsigned long evt,
>> +				    struct clock_event_device *ev)
>> +{
>> +	writel(0, owl_timer_base + OWL_T1_CTL);
>> +
>> +	writel(0, owl_timer_base + OWL_T1_VAL);
>> +	writel(evt, owl_timer_base + OWL_T1_CMP);
>> +
>> +	writel(OWL_Tx_CTL_EN | OWL_Tx_CTL_INTEN, owl_timer_base + OWL_T1_CTL);
>> +
>> +	return 0;
>> +}
>> +
>> +static struct clock_event_device owl_clockevent = {
>> +	.name			= "owl_tick",
>> +	.rating			= 200,
>> +	.features		= CLOCK_EVT_FEAT_ONESHOT,
> 
> Did you consider adding CLOCK_EVT_FEAT_DYNIRQ ?

No, it was not present downstream. Got a good example?

>> +	.set_state_shutdown	= owl_timer_set_state_shutdown,
>> +	.set_state_oneshot	= owl_timer_set_state_oneshot,
>> +	.tick_resume		= owl_timer_tick_resume,
>> +	.set_next_event		= owl_timer_set_next_event,
>> +};
>> +
>> +static irqreturn_t owl_timer_interrupt(int irq, void *dev_id)
>> +{
>> +	struct clock_event_device *evt = (struct clock_event_device *)dev_id;
>> +
>> +	evt->event_handler(evt);
>> +
>> +	return IRQ_HANDLED;
>> +}
>> +
>> +static struct irqaction owl_timer_irq = {
>> +	.name = "owl-timer",
>> +	.flags = IRQF_TIMER,
>> +	.handler = owl_timer_interrupt,
>> +	.dev_id = &owl_clockevent,
>> +};
>> +
>> +static int __init owl_timer_init(struct device_node *node)
>> +{
>> +	const unsigned long rate = 24000000;
> 
> Use DT, either use clock-frequency or a clock ref.

Are clk drivers really available at this point? clock-frequency sounds
more promising.

>> +	int irq1, ret;
>> +
>> +	owl_timer_base = of_io_request_and_map(node, 0, "owl-timer");
>> +	if (IS_ERR(owl_timer_base)) {
>> +		pr_err("Can't map timer registers");
>> +		return -ENXIO;
> 
> Why not PTR_ERR(owl_timer_base) ?

Only one in-tree driver (sun5i) matches such an expression. Will change.

>> +	}
>> +
>> +	irq1 = irq_of_parse_and_map(node, 1);
>> +	if (irq1 <= 0) {
>> +		pr_err("Can't parse timer1 IRQ");
>> +		return -EINVAL;
>> +	}
>> +
>> +	writel(0, owl_timer_base + OWL_T0_CTL);
>> +	writel(0, owl_timer_base + OWL_T0_VAL);
>> +	writel(0, owl_timer_base + OWL_T0_CMP);
>> +	writel(OWL_Tx_CTL_EN, owl_timer_base + OWL_T0_CTL);
> 
> Please factor out these calls into a function.

Do you have something in particular in mind? Maybe ..._reset() for the
first three?

>> +
>> +	sched_clock_register(owl_timer_sched_read, 32, rate);
>> +	clocksource_mmio_init(owl_timer_base + OWL_T0_VAL, node->name,
>> +			      rate, 200, 32, clocksource_mmio_readl_up);
>> +
>> +	writel(0, owl_timer_base + OWL_T1_CTL);
>> +	writel(0, owl_timer_base + OWL_T1_VAL);
>> +	writel(0, owl_timer_base + OWL_T1_CMP);
>> +
>> +	ret = setup_irq(irq1, &owl_timer_irq);
>> +	if (ret) {
>> +		pr_warn("failed to setup irq %d\n", irq1);
>> +		return ret;
>> +	}
> 
> s/setup_irq/request_irq/

Care to explain? setup_irq has 32 hits vs. 28 for request_irq.

>> +
>> +	owl_clockevent.cpumask = cpumask_of(0);
>> +	owl_clockevent.irq = irq1;
>> +
>> +	clockevents_config_and_register(&owl_clockevent, rate,
>> +					0xf, 0xffffffff);
>> +
>> +	return 0;
>> +}
>> +CLOCKSOURCE_OF_DECLARE(owl, "actions,owl-timer", owl_timer_init);

Do you spot anything functionally wrong in this driver? Despite adding
this new driver, I am only getting the following additional earlycon output:

[    0.000029] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps
every 89478484971ns
[    0.007888] clocksource: timer: mask: 0xffffffff max_cycles:
0xffffffff, max_idle_ns: 79635851949 ns
[    0.017748] Console: colour dummy device 80x30
[    0.022243] Calibrating delay loop...
[    0.030895] random: fast init done
[    0.231021] random: crng init done

For S900 I'm using the generic timer instead.

Thanks for your review,

Andreas

-- 
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)

Re: [PATCH v2 04/17] clocksource: Add Owl timer

[Daniel Lezcano]

On Sat, Feb 25, 2017 at 12:25:32AM +0100, Andreas Färber wrote:
> Am 24.02.2017 um 23:29 schrieb Daniel Lezcano:
> > On Fri, Feb 24, 2017 at 04:40:42AM +0100, Andreas Färber wrote:
> >> Implement clocksource and clockevents for Actions Semi S500.
> >>
> >> Based on LeMaker linux-actions tree.
> >>
> >> Signed-off-by: Andreas Färber <afaerber@suse.de>
> > 
> > As this is a new driver, please give some technical information about the
> > driver itself and a pointer to documentation if it is publicly available.
> 
> What technical information would that be? Which of the timers we use as
> clock source vs. clock events?

Have a look at commit 07862c1 and e4a6b37 as reference.
 
> The only public documentation beyond the source tree mentioned is here:
> 
> http://www.lemaker.org/product-guitar-download-29.html (section 3.4)
> 
> >> +#define OWL_Tx_CTL_INTEN	(1 << 1)
> >> +#define OWL_Tx_CTL_EN		(1 << 2)
> > 
> > s/(1 << 1)/BIT(1)/
> > s/(1 << 2)/BIT(2)/
> 
> OK
> 

[ ... ]

> >> +static struct clock_event_device owl_clockevent = {
> >> +	.name			= "owl_tick",
> >> +	.rating			= 200,
> >> +	.features		= CLOCK_EVT_FEAT_ONESHOT,
> > 
> > Did you consider adding CLOCK_EVT_FEAT_DYNIRQ ?
> 
> No, it was not present downstream. Got a good example?

https://lwn.net/Articles/541000/

> >> +	.set_state_shutdown	= owl_timer_set_state_shutdown,
> >> +	.set_state_oneshot	= owl_timer_set_state_oneshot,
> >> +	.tick_resume		= owl_timer_tick_resume,
> >> +	.set_next_event		= owl_timer_set_next_event,
> >> +};
> >> +
> >> +static irqreturn_t owl_timer_interrupt(int irq, void *dev_id)
> >> +{
> >> +	struct clock_event_device *evt = (struct clock_event_device *)dev_id;
> >> +
> >> +	evt->event_handler(evt);
> >> +
> >> +	return IRQ_HANDLED;
> >> +}
> >> +
> >> +static struct irqaction owl_timer_irq = {
> >> +	.name = "owl-timer",
> >> +	.flags = IRQF_TIMER,
> >> +	.handler = owl_timer_interrupt,
> >> +	.dev_id = &owl_clockevent,
> >> +};
> >> +
> >> +static int __init owl_timer_init(struct device_node *node)
> >> +{
> >> +	const unsigned long rate = 24000000;
> > 
> > Use DT, either use clock-frequency or a clock ref.
> 
> Are clk drivers really available at this point? clock-frequency sounds
> more promising.

Yes they are. Have a look at the other drivers.
 
> >> +	int irq1, ret;
> >> +
> >> +	owl_timer_base = of_io_request_and_map(node, 0, "owl-timer");
> >> +	if (IS_ERR(owl_timer_base)) {
> >> +		pr_err("Can't map timer registers");
> >> +		return -ENXIO;
> > 
> > Why not PTR_ERR(owl_timer_base) ?
> 
> Only one in-tree driver (sun5i) matches such an expression. Will change.

[ ... ]

> > Please factor out these calls into a function.
> 
> Do you have something in particular in mind? Maybe ..._reset() for the
> first three?

Yes.

> >> +
> >> +	sched_clock_register(owl_timer_sched_read, 32, rate);
> >> +	clocksource_mmio_init(owl_timer_base + OWL_T0_VAL, node->name,
> >> +			      rate, 200, 32, clocksource_mmio_readl_up);
> >> +
> >> +	writel(0, owl_timer_base + OWL_T1_CTL);
> >> +	writel(0, owl_timer_base + OWL_T1_VAL);
> >> +	writel(0, owl_timer_base + OWL_T1_CMP);
> >> +
> >> +	ret = setup_irq(irq1, &owl_timer_irq);
> >> +	if (ret) {
> >> +		pr_warn("failed to setup irq %d\n", irq1);
> >> +		return ret;
> >> +	}
> > 
> > s/setup_irq/request_irq/
> 
> Care to explain? setup_irq has 32 hits vs. 28 for request_irq.

The function setup_irq takes an irqaction as parameter. That forces all the
drivers to declare a structure, so for a multiple platforms support (aka single
kernel image), there are multiple structures declaration for nothing. The
function request_irq allocates the structure and then call setup_irq.

So now, request_irq is used in place of setup_irq.

> >> +
> >> +	owl_clockevent.cpumask = cpumask_of(0);
> >> +	owl_clockevent.irq = irq1;
> >> +
> >> +	clockevents_config_and_register(&owl_clockevent, rate,
> >> +					0xf, 0xffffffff);
> >> +
> >> +	return 0;
> >> +}
> >> +CLOCKSOURCE_OF_DECLARE(owl, "actions,owl-timer", owl_timer_init);
> 
> Do you spot anything functionally wrong in this driver? Despite adding
> this new driver, I am only getting the following additional earlycon output:
>
> [    0.000029] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps
> every 89478484971ns
> [    0.007888] clocksource: timer: mask: 0xffffffff max_cycles:
> 0xffffffff, max_idle_ns: 79635851949 ns
> [    0.017748] Console: colour dummy device 80x30
> [    0.022243] Calibrating delay loop...
> [    0.030895] random: fast init done
> [    0.231021] random: crng init done
> 
> For S900 I'm using the generic timer instead.

I don't get the issue, can you elaborate ?

Thanks

  -- Daniel


-- 

 <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs

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Re: [PATCH v2 04/17] clocksource: Add Owl timer

[Andreas Färber]

Am 25.02.2017 um 22:59 schrieb Daniel Lezcano:
> On Sat, Feb 25, 2017 at 12:25:32AM +0100, Andreas Färber wrote:
>> Am 24.02.2017 um 23:29 schrieb Daniel Lezcano:
>>> On Fri, Feb 24, 2017 at 04:40:42AM +0100, Andreas Färber wrote:
>>>> +static struct clock_event_device owl_clockevent = {
>>>> +	.name			= "owl_tick",
>>>> +	.rating			= 200,
>>>> +	.features		= CLOCK_EVT_FEAT_ONESHOT,
>>>
>>> Did you consider adding CLOCK_EVT_FEAT_DYNIRQ ?
>>
>> No, it was not present downstream. Got a good example?
> 
> https://lwn.net/Articles/541000/

Looking at your current Nomadik code, it seems I can literally should
just add this flag (done), without needing to implement any new hooks.

On a related topic, how do we determine the cpumask? Downstream and some
in-tree drivers use cpumask_of(0), others use cpu_possible_mask.

>> Do you spot anything functionally wrong in this driver? Despite adding
>> this new driver, I am only getting the following additional earlycon output:
>>
>> [    0.000029] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps
>> every 89478484971ns
>> [    0.007888] clocksource: timer: mask: 0xffffffff max_cycles:
>> 0xffffffff, max_idle_ns: 79635851949 ns
>> [    0.017748] Console: colour dummy device 80x30
>> [    0.022243] Calibrating delay loop...
>> [    0.030895] random: fast init done
>> [    0.231021] random: crng init done
>>
>> For S900 I'm using the generic timer instead.
> 
> I don't get the issue, can you elaborate ?

Found it myself: I forgot to clear the interrupt pending bit in the
interrupt handler routine.

+       writel(OWL_Tx_CTL_PD, owl_timer_base + OWL_T1_CTL);

Now it goes past this point, initializes the real serial driver and
boots up to not finding the rootfs:

[    0.000032] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps
every 89478484971ns
[    0.007898] clocksource: timer: mask: 0xffffffff max_cycles:
0xffffffff, max_idle_ns: 79635851949 ns
[    0.017886] Console: colour dummy device 80x30
[    0.022386] Calibrating delay loop... 405.50 BogoMIPS (lpj=2027520)
[    0.083523] pid_max: default: 32768 minimum: 301
...

Regards,
Andreas

-- 
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)

Re: [PATCH v2 04/17] clocksource: Add Owl timer

[Daniel Lezcano]

On Sun, Feb 26, 2017 at 03:40:49PM +0100, Andreas Färber wrote:
> Am 25.02.2017 um 22:59 schrieb Daniel Lezcano:
> > On Sat, Feb 25, 2017 at 12:25:32AM +0100, Andreas Färber wrote:
> >> Am 24.02.2017 um 23:29 schrieb Daniel Lezcano:
> >>> On Fri, Feb 24, 2017 at 04:40:42AM +0100, Andreas Färber wrote:
> >>>> +static struct clock_event_device owl_clockevent = {
> >>>> +	.name			= "owl_tick",
> >>>> +	.rating			= 200,
> >>>> +	.features		= CLOCK_EVT_FEAT_ONESHOT,
> >>>
> >>> Did you consider adding CLOCK_EVT_FEAT_DYNIRQ ?
> >>
> >> No, it was not present downstream. Got a good example?
> > 
> > https://lwn.net/Articles/541000/
> 
> Looking at your current Nomadik code, it seems I can literally should
> just add this flag (done), without needing to implement any new hooks.
> 
> On a related topic, how do we determine the cpumask? Downstream and some
> in-tree drivers use cpumask_of(0), others use cpu_possible_mask.

If you specify the CLOCK_EVT_FEAT_DYNIRQ, the cpumask is not important as it
will be changed dynamically.

Otherwise, cpumask_of(0) is often the default because it concentrates the
wakeup on a single cpu, allowing the other cpus to go to deep idle state and if
there are two clusters, it allows to have a cluster idle state. That results on
a better energy saving.

The usage of cpu_possible_mask will randomly wakeup any cpu.
 
> >> Do you spot anything functionally wrong in this driver? Despite adding
> >> this new driver, I am only getting the following additional earlycon output:
> >>
> >> [    0.000029] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps
> >> every 89478484971ns
> >> [    0.007888] clocksource: timer: mask: 0xffffffff max_cycles:
> >> 0xffffffff, max_idle_ns: 79635851949 ns
> >> [    0.017748] Console: colour dummy device 80x30
> >> [    0.022243] Calibrating delay loop...
> >> [    0.030895] random: fast init done
> >> [    0.231021] random: crng init done
> >>
> >> For S900 I'm using the generic timer instead.
> > 
> > I don't get the issue, can you elaborate ?
> 
> Found it myself: I forgot to clear the interrupt pending bit in the
> interrupt handler routine.
> 
> +       writel(OWL_Tx_CTL_PD, owl_timer_base + OWL_T1_CTL);
> 
> Now it goes past this point, initializes the real serial driver and
> boots up to not finding the rootfs:
> 
> [    0.000032] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps
> every 89478484971ns
> [    0.007898] clocksource: timer: mask: 0xffffffff max_cycles:
> 0xffffffff, max_idle_ns: 79635851949 ns
> [    0.017886] Console: colour dummy device 80x30
> [    0.022386] Calibrating delay loop... 405.50 BogoMIPS (lpj=2027520)

May be you should also consider using register_current_timer_delay() instead of
jiffies based delay loops.

> [    0.083523] pid_max: default: 32768 minimum: 301

-- 

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<http://www.linaro.org/linaro-blog/> Blog

[PATCH v2 05/17] ARM: Prepare Actions Semi S500

[Andreas Färber]

Add ARCH_ACTIONS and mach-actions/owl.c for "actions,s500".

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 v1 -> v2:
 * Renamed ARCH_OWL to ARCH_ACTION (Arnd)
 * Renamed mach-owl to mach-actions, leaving owl.c
 * Adopted "actions" vendor prefix
 
 arch/arm/Kconfig               |  2 ++
 arch/arm/Makefile              |  1 +
 arch/arm/mach-actions/Kconfig  | 10 ++++++++++
 arch/arm/mach-actions/Makefile |  1 +
 arch/arm/mach-actions/owl.c    | 28 ++++++++++++++++++++++++++++
 5 files changed, 42 insertions(+)
 create mode 100644 arch/arm/mach-actions/Kconfig
 create mode 100644 arch/arm/mach-actions/Makefile
 create mode 100644 arch/arm/mach-actions/owl.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0d4e71b..94fa3925 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -720,6 +720,8 @@ config ARCH_VIRT
 #
 source "arch/arm/mach-mvebu/Kconfig"
 
+source "arch/arm/mach-actions/Kconfig"
+
 source "arch/arm/mach-alpine/Kconfig"
 
 source "arch/arm/mach-artpec/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index ab30cc6..d2ccf72 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -151,6 +151,7 @@ textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
 
 # Machine directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
+machine-$(CONFIG_ARCH_ACTIONS)		+= actions
 machine-$(CONFIG_ARCH_ALPINE)		+= alpine
 machine-$(CONFIG_ARCH_ARTPEC)		+= artpec
 machine-$(CONFIG_ARCH_AT91)		+= at91
diff --git a/arch/arm/mach-actions/Kconfig b/arch/arm/mach-actions/Kconfig
new file mode 100644
index 0000000..d40cec7
--- /dev/null
+++ b/arch/arm/mach-actions/Kconfig
@@ -0,0 +1,10 @@
+menuconfig ARCH_ACTIONS
+	bool "Actions Semi SoCs"
+	depends on ARCH_MULTI_V7
+	select ARM_GIC
+	select CACHE_L2X0
+	select COMMON_CLK
+	select GENERIC_IRQ_CHIP
+	select OWL_TIMER
+	help
+	  This enables support for the Actions Semiconductor S500 SoC family.
diff --git a/arch/arm/mach-actions/Makefile b/arch/arm/mach-actions/Makefile
new file mode 100644
index 0000000..524c381
--- /dev/null
+++ b/arch/arm/mach-actions/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_ARCH_ACTIONS) += owl.o
diff --git a/arch/arm/mach-actions/owl.c b/arch/arm/mach-actions/owl.c
new file mode 100644
index 0000000..74dc670
--- /dev/null
+++ b/arch/arm/mach-actions/owl.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2017 Andreas Färber
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+
+static const char * const owl_dt_compat[] = {
+	"actions,s500",
+	NULL
+};
+
+DT_MACHINE_START(MESON, "Actions Semi Owl platform")
+	.dt_compat	= owl_dt_compat,
+	.l2c_aux_val	= 0,
+	.l2c_aux_mask	= ~0,
+MACHINE_END
-- 
2.10.2

[PATCH v2 06/17] ARM64: Prepare Actions Semi S900

[Andreas Färber]

Add ARCH_ACTIONS.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 v1 -> v2:
 * Renamed ARCH_OWL to ARCH_ACTION (Arnd)
 
 arch/arm64/Kconfig.platforms | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 129cc5a..b0266cd 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -1,5 +1,10 @@
 menu "Platform selection"
 
+config ARCH_ACTIONS
+	bool "Actions Semi Platforms"
+	help
+	  This enables support for the Actions Semiconductor S900 SoC family.
+
 config ARCH_SUNXI
 	bool "Allwinner sunxi 64-bit SoC Family"
 	select GENERIC_IRQ_CHIP
-- 
2.10.2

[PATCH v2 07/17] dt-bindings: serial: Document Actions Semi Owl UARTs

[Andreas Färber]

This UART is found on S500 and S900 SoCs.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 v1 -> v2:
 * Adopted "actions" vendor prefix
 
 .../devicetree/bindings/serial/actions,owl-uart.txt      | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/serial/actions,owl-uart.txt

diff --git a/Documentation/devicetree/bindings/serial/actions,owl-uart.txt b/Documentation/devicetree/bindings/serial/actions,owl-uart.txt
new file mode 100644
index 0000000..aa873ea
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/actions,owl-uart.txt
@@ -0,0 +1,16 @@
+Actions Semi Owl UART
+
+Required properties:
+- compatible :  "actions,s500-uart", "actions,owl-uart" for S500
+                "actions,s900-uart", "actions,owl-uart" for S900
+- reg        :  Offset and length of the register set for the device.
+- interrupts :  Should contain UART interrupt.
+
+
+Example:
+
+		uart3: serial@b0126000 {
+			compatible = "actions,s500-uart", "actions,owl-uart";
+			reg = <0xb0126000 0x1000>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+		};
-- 
2.10.2

Re: [PATCH v2 07/17] dt-bindings: serial: Document Actions Semi Owl UARTs

[Rob Herring]

On Fri, Feb 24, 2017 at 04:40:45AM +0100, Andreas Färber wrote:
> This UART is found on S500 and S900 SoCs.
> 
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> ---
>  v1 -> v2:
>  * Adopted "actions" vendor prefix
>  
>  .../devicetree/bindings/serial/actions,owl-uart.txt      | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/serial/actions,owl-uart.txt

Acked-by: Rob Herring <robh@kernel.org>

[PATCH v2 08/17] tty: serial: Add Actions Semi Owl UART earlycon

[Andreas Färber]

This implements an earlycon for Actions Semi S500/S900 SoCs.

Based on LeMaker linux-actions tree.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 v1 -> v2:
 * Extended Kconfig help to mention earlycon (Arnd)
 * Spelled out Actions Semiconductor in Kconfig help
 * Adopted "actions" vendor prefix
 
 drivers/tty/serial/Kconfig    |  19 ++++++
 drivers/tty/serial/Makefile   |   1 +
 drivers/tty/serial/owl-uart.c | 135 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 155 insertions(+)
 create mode 100644 drivers/tty/serial/owl-uart.c

diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 6117ac8..e145822 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1677,6 +1677,25 @@ config SERIAL_MVEBU_CONSOLE
 	  and warnings and which allows logins in single user mode)
 	  Otherwise, say 'N'.
 
+config SERIAL_OWL
+	bool "Actions Semi Owl serial port support"
+	depends on ARCH_ACTIONS || COMPILE_TEST
+	select SERIAL_CORE
+	help
+	  This driver is for Actions Semiconductor S500/S900 SoC's UART.
+	  Say 'Y' here if you wish to use the on-board serial port.
+	  Otherwise, say 'N'.
+
+config SERIAL_OWL_CONSOLE
+	bool "Console on Actions Semi Owl serial port"
+	depends on SERIAL_OWL=y
+	select SERIAL_CORE_CONSOLE
+	select SERIAL_EARLYCON
+	default y
+	help
+	  Say 'Y' here if you wish to use Actions Semiconductor S500/S900 UART
+	  as the system console. Only earlycon is implemented currently.
+
 endmenu
 
 config SERIAL_MCTRL_GPIO
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index 2d6288b..91f3571 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
@@ -91,6 +91,7 @@ obj-$(CONFIG_SERIAL_STM32)	+= stm32-usart.o
 obj-$(CONFIG_SERIAL_MVEBU_UART)	+= mvebu-uart.o
 obj-$(CONFIG_SERIAL_PIC32)	+= pic32_uart.o
 obj-$(CONFIG_SERIAL_MPS2_UART)	+= mps2-uart.o
+obj-$(CONFIG_SERIAL_OWL)	+= owl-uart.o
 
 # GPIOLIB helpers for modem control lines
 obj-$(CONFIG_SERIAL_MCTRL_GPIO)	+= serial_mctrl_gpio.o
diff --git a/drivers/tty/serial/owl-uart.c b/drivers/tty/serial/owl-uart.c
new file mode 100644
index 0000000..e097443
--- /dev/null
+++ b/drivers/tty/serial/owl-uart.c
@@ -0,0 +1,135 @@
+/*
+ * Actions Semi Owl family serial console
+ *
+ * Copyright 2013 Actions Semi Inc.
+ * Author: Actions Semi, Inc.
+ *
+ * Copyright (c) 2016-2017 Andreas Färber
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/console.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+
+#define OWL_UART_CTL	0x000
+#define OWL_UART_TXDAT	0x008
+#define OWL_UART_STAT	0x00c
+
+#define OWL_UART_CTL_TRFS_TX		(1 << 14)
+#define OWL_UART_CTL_EN			(1 << 15)
+#define OWL_UART_CTL_RXIE		(1 << 18)
+#define OWL_UART_CTL_TXIE		(1 << 19)
+
+#define OWL_UART_STAT_RIP		(1 << 0)
+#define OWL_UART_STAT_TIP		(1 << 1)
+#define OWL_UART_STAT_TFFU		(1 << 6)
+#define OWL_UART_STAT_TRFL_MASK		(0x1f << 11)
+#define OWL_UART_STAT_UTBB		(1 << 17)
+
+static inline void owl_uart_write(struct uart_port *port, u32 val, unsigned int off)
+{
+	writel(val, port->membase + off);
+}
+
+static inline u32 owl_uart_read(struct uart_port *port, unsigned int off)
+{
+	return readl(port->membase + off);
+}
+
+#ifdef CONFIG_SERIAL_OWL_CONSOLE
+
+static void owl_console_putchar(struct uart_port *port, int ch)
+{
+	if (!port->membase)
+		return;
+
+	while (owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU)
+		cpu_relax();
+
+	owl_uart_write(port, ch, OWL_UART_TXDAT);
+}
+
+static void owl_uart_port_write(struct uart_port *port, const char *s,
+				u_int count)
+{
+	u32 old_ctl, val;
+	unsigned long flags;
+	int locked;
+
+	local_irq_save(flags);
+
+	if (port->sysrq)
+		locked = 0;
+	else if (oops_in_progress)
+		locked = spin_trylock(&port->lock);
+	else {
+		spin_lock(&port->lock);
+		locked = 1;
+	}
+
+	old_ctl = owl_uart_read(port, OWL_UART_CTL);
+	val = old_ctl | OWL_UART_CTL_TRFS_TX;
+	/* disable IRQ */
+	val &= ~(OWL_UART_CTL_RXIE | OWL_UART_CTL_TXIE);
+	owl_uart_write(port, val, OWL_UART_CTL);
+
+	uart_console_write(port, s, count, owl_console_putchar);
+
+	/* wait until all contents have been sent out */
+	while (owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TRFL_MASK)
+		cpu_relax();
+
+	/* clear IRQ pending */
+	val = owl_uart_read(port, OWL_UART_STAT);
+	val |= OWL_UART_STAT_TIP | OWL_UART_STAT_RIP;
+	owl_uart_write(port, val, OWL_UART_STAT);
+
+	owl_uart_write(port, old_ctl, OWL_UART_CTL);
+
+	if (locked)
+		spin_unlock(&port->lock);
+
+	local_irq_restore(flags);
+}
+
+static void owl_uart_early_console_write(struct console *co,
+					 const char *s,
+					 u_int count)
+{
+	struct earlycon_device *dev = co->data;
+
+	owl_uart_port_write(&dev->port, s, count);
+}
+
+static int __init
+owl_uart_early_console_setup(struct earlycon_device *device, const char *opt)
+{
+	if (!device->port.membase)
+		return -ENODEV;
+
+	device->con->write = owl_uart_early_console_write;
+
+	return 0;
+}
+OF_EARLYCON_DECLARE(owl, "actions,owl-uart",
+		    owl_uart_early_console_setup);
+
+#endif /* CONFIG_SERIAL_OWL_CONSOLE */
-- 
2.10.2

[PATCH v2 09/17] Documentation: kernel-parameters: Document owl earlycon

[Andreas Färber]

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 v1 -> v2: unchanged
 
 Documentation/admin-guide/kernel-parameters.txt | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
index 986e443..f48a142 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -943,6 +943,12 @@
 			must already be setup and configured. Options are not
 			yet supported.
 
+		owl,<addr>
+			Start an early, polled-mode console on an Owl serial
+			port at the specified address. The serial port must
+			already be setup and configured. Options are not yet
+			supported.
+
 		smh	Use ARM semihosting calls for early console.
 
 		s3c2410,<addr>
-- 
2.10.2

Re: [PATCH v2 09/17] Documentation: kernel-parameters: Document owl earlycon

[Jonathan Corbet]

On Fri, 24 Feb 2017 04:40:47 +0100
Andreas Färber <afaerber@suse.de> wrote:

> +		owl,<addr>
> +			Start an early, polled-mode console on an Owl serial
> +			port at the specified address. The serial port must
> +			already be setup and configured. Options are not yet
> +			supported.
> +

Apologies, I'm just getting around to looking at this.

Is there any chance of getting a version of it that (1) has a proper
changelog, and (2) better describes the applicability of this option.
Presumably if I don't know what an "Owl serial port" is I don't need it,
but maybe a phrase saying where such ports might be found would be helpful
here?

Thanks,

jon

Re: [PATCH v2 09/17] Documentation: kernel-parameters: Document owl earlycon

[Andreas Färber]

Am 03.03.2017 um 23:46 schrieb Jonathan Corbet:
> On Fri, 24 Feb 2017 04:40:47 +0100
> Andreas Färber <afaerber@suse.de> wrote:
> 
>> +		owl,<addr>
>> +			Start an early, polled-mode console on an Owl serial
>> +			port at the specified address. The serial port must
>> +			already be setup and configured. Options are not yet
>> +			supported.
>> +
> 
> Apologies, I'm just getting around to looking at this.
> 
> Is there any chance of getting a version of it that (1) has a proper
> changelog, and (2) better describes the applicability of this option.
> Presumably if I don't know what an "Owl serial port" is I don't need it,
> but maybe a phrase saying where such ports might be found would be helpful
> here?

Note that there is already a v3 of this patch.

Both v2 and v3 do have a changelog, indicating that nothing changed here
between versions. Did you mean commit message, and if so what would you
like to see added exactly?

Did you notice that most earlycon options are described like this?
pl011, my meson, msm, lantiq all just repeat the driver name. In this
case Owl is a family of Actions Semiconductor SoCs that are newly being
enabled in this series - I can add the vendor name to the text, but no
idea what else to say about "applicability"...

While at it, it is really ugly for both users and contributors that
there is no consistent (e.g., alphabetical) order of these options.

Regards,
Andreas

-- 
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)

[PATCH v2 10/17] ARM: dts: Add Actions Semi S500 and LeMaker Guitar

[Andreas Färber]

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 v1 -> v2:
 * Reworded subject
 * Updated ARCH_OWL to ARCH_ACTIONS (Arnd)
 * Adopted "actions" vendor prefix
 * Dropped irq.h include
 * Added memory@0 node for Guitar SoM
 * Dropped bogus uart3 clock-frequency
 * Added device_type for CPU nodes
 * Fixed UART reg size
 * Adopted SPDX-License-Identifier (Rob)
 * Added remaining UART nodes
 * Added timer node
 
 arch/arm/boot/dts/Makefile                 |   2 +
 arch/arm/boot/dts/s500-guitar-bb-rev-b.dts |  26 ++++++
 arch/arm/boot/dts/s500-guitar.dtsi         |  20 +++++
 arch/arm/boot/dts/s500.dtsi                | 135 +++++++++++++++++++++++++++++
 4 files changed, 183 insertions(+)
 create mode 100644 arch/arm/boot/dts/s500-guitar-bb-rev-b.dts
 create mode 100644 arch/arm/boot/dts/s500-guitar.dtsi
 create mode 100644 arch/arm/boot/dts/s500.dtsi

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 0118084..578a20b 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -638,6 +638,8 @@ dtb-$(CONFIG_ARCH_ORION5X) += \
 	orion5x-maxtor-shared-storage-2.dtb \
 	orion5x-netgear-wnr854t.dtb \
 	orion5x-rd88f5182-nas.dtb
+dtb-$(CONFIG_ARCH_ACTIONS) += \
+	s500-guitar-bb-rev-b.dtb
 dtb-$(CONFIG_ARCH_PRIMA2) += \
 	prima2-evb.dtb
 dtb-$(CONFIG_ARCH_OXNAS) += \
diff --git a/arch/arm/boot/dts/s500-guitar-bb-rev-b.dts b/arch/arm/boot/dts/s500-guitar-bb-rev-b.dts
new file mode 100644
index 0000000..834b71d
--- /dev/null
+++ b/arch/arm/boot/dts/s500-guitar-bb-rev-b.dts
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2016-2017 Andreas Färber
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+/dts-v1/;
+
+#include "s500-guitar.dtsi"
+
+/ {
+	compatible = "lemaker,guitar-bb-rev-b", "lemaker,guitar", "actions,s500";
+	model = "LeMaker Guitar Base Board rev. B";
+
+	aliases {
+		serial3 = &uart3;
+	};
+
+	chosen {
+		stdout-path = "serial3:115200n8";
+	};
+};
+
+&uart3 {
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/s500-guitar.dtsi b/arch/arm/boot/dts/s500-guitar.dtsi
new file mode 100644
index 0000000..ef0e7e3
--- /dev/null
+++ b/arch/arm/boot/dts/s500-guitar.dtsi
@@ -0,0 +1,20 @@
+/*
+ * LeMaker Guitar SoM
+ *
+ * Copyright (c) 2016-2017 Andreas Färber
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+#include "s500.dtsi"
+
+/ {
+	compatible = "lemaker,guitar", "actions,s500";
+
+	/delete-node/ memory;
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x40000000>;
+	};
+};
diff --git a/arch/arm/boot/dts/s500.dtsi b/arch/arm/boot/dts/s500.dtsi
new file mode 100644
index 0000000..149bb7a
--- /dev/null
+++ b/arch/arm/boot/dts/s500.dtsi
@@ -0,0 +1,135 @@
+/*
+ * Actions Semi S500 SoC
+ *
+ * Copyright (c) 2016-2017 Andreas Färber
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+#include "skeleton.dtsi"
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "actions,s500";
+	interrupt-parent = <&gic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <0x0>;
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <0x1>;
+		};
+
+		cpu2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <0x2>;
+		};
+
+		cpu3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <0x3>;
+		};
+	};
+
+	arm-pmu {
+		compatible = "arm,cortex-a9-pmu";
+		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+		             <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+		             <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+		             <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		gic: interrupt-controller@b0021000 {
+			compatible = "arm,cortex-a9-gic";
+			reg = <0xb0021000 0x1000>,
+			      <0xb0020100 0x0100>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+		};
+
+		l2: cache-controller@b0022000 {
+			compatible = "arm,pl310-cache";
+			reg = <0xb0022000 0x1000>;
+			cache-unified;
+			cache-level = <2>;
+			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+			arm,tag-latency = <3 3 2>;
+			arm,data-latency = <5 3 3>;
+		};
+
+		uart0: serial@b0120000 {
+			compatible = "actions,s500-uart", "actions,owl-uart";
+			reg = <0xb0120000 0x2000>;
+			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		uart1: serial@b0122000 {
+			compatible = "actions,s500-uart", "actions,owl-uart";
+			reg = <0xb0122000 0x2000>;
+			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		uart2: serial@b0124000 {
+			compatible = "actions,s500-uart", "actions,owl-uart";
+			reg = <0xb0126000 0x2000>;
+			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		uart3: serial@b0126000 {
+			compatible = "actions,s500-uart", "actions,owl-uart";
+			reg = <0xb0126000 0x2000>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		uart4: serial@b0128000 {
+			compatible = "actions,s500-uart", "actions,owl-uart";
+			reg = <0xb0128000 0x2000>;
+			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		uart5: serial@b012a000 {
+			compatible = "actions,s500-uart", "actions,owl-uart";
+			reg = <0xb012a000 0x2000>;
+			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		uart6: serial@b012c000 {
+			compatible = "actions,s500-uart", "actions,owl-uart";
+			reg = <0xb012c000 0x2000>;
+			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		timer@b0168000 {
+			compatible = "actions,owl-timer";
+			reg = <0xb0168000 0x100>;
+			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+			             <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+		};
+	};
+};
-- 
2.10.2

Re: [PATCH v2 10/17] ARM: dts: Add Actions Semi S500 and LeMaker Guitar

[Andreas Färber]

Am 24.02.2017 um 04:40 schrieb Andreas Färber:
> +		uart2: serial@b0124000 {
> +			compatible = "actions,s500-uart", "actions,owl-uart";
> +			reg = <0xb0126000 0x2000>;

Wrong reg offset.

> +			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
> +			status = "disabled";
> +		};
> +
> +		uart3: serial@b0126000 {
> +			compatible = "actions,s500-uart", "actions,owl-uart";
> +			reg = <0xb0126000 0x2000>;
> +			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> +			status = "disabled";
> +		};

-- 
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)

[PATCH v2 11/17] dt-bindings: Add vendor prefix for uCRobotics

[Andreas Färber]

Cc: 96boards@ucrobotics.com
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 v1 -> v2: unchanged
 
 Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 64f8469..a89dbab 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -320,6 +320,7 @@ tronfy	Tronfy
 tronsmart	Tronsmart
 truly	Truly Semiconductors Limited
 tyan	Tyan Computer Corporation
+ucrobotics	uCRobotics
 udoo	Udoo
 uniwest	United Western Technologies Corp (UniWest)
 upisemi	uPI Semiconductor Corp.
-- 
2.10.2

Re: [PATCH v2 11/17] dt-bindings: Add vendor prefix for uCRobotics

[Rob Herring]

On Fri, Feb 24, 2017 at 04:40:49AM +0100, Andreas Färber wrote:
> Cc: 96boards@ucrobotics.com
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> ---
>  v1 -> v2: unchanged
>  
>  Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
>  1 file changed, 1 insertion(+)

Acked-by: Rob Herring <robh@kernel.org>

[PATCH v2 12/17] dt-bindings: arm: Document Actions Semi S900

[Andreas Färber]

The Actions Semi S900 is a quad-core ARM Cortex-A53 SoC.
The Bubblegum-96 is a 96Boards Consumer Edition compliant board (4/96).

Cc: 96boards@ucrobotics.com
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 v1 -> v2:
 * Adopted "actions" vendor prefix
 * Extended text
 
 Documentation/devicetree/bindings/arm/actions.txt | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/actions.txt b/Documentation/devicetree/bindings/arm/actions.txt
index 1d3782e..3bc7ea5 100644
--- a/Documentation/devicetree/bindings/arm/actions.txt
+++ b/Documentation/devicetree/bindings/arm/actions.txt
@@ -22,3 +22,18 @@ Boards:
 Root node property compatible must contain, depending on board:
 
  - LeMaker Guitar Base Board rev. B: "lemaker,guitar-bb-rev-b", "lemaker,guitar"
+
+
+S900 SoC
+========
+
+Required root node properties:
+
+- compatible :  must contain "actions,s900"
+
+
+Boards:
+
+Root node property compatible must contain, depending on board:
+
+ - uCRobotics Bubblegum-96: "ucrobotics,bubblegum-96"
-- 
2.10.2

Re: [PATCH v2 12/17] dt-bindings: arm: Document Actions Semi S900

[Rob Herring]

On Fri, Feb 24, 2017 at 04:40:50AM +0100, Andreas Färber wrote:
> The Actions Semi S900 is a quad-core ARM Cortex-A53 SoC.
> The Bubblegum-96 is a 96Boards Consumer Edition compliant board (4/96).
> 
> Cc: 96boards@ucrobotics.com
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> ---
>  v1 -> v2:
>  * Adopted "actions" vendor prefix
>  * Extended text
>  
>  Documentation/devicetree/bindings/arm/actions.txt | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)

Acked-by: Rob Herring <robh@kernel.org>

[RFC v2 13/17] ARM64: dts: Add Actions Semi S900 and Bubblegum-96

[Andreas Färber]

Cc: 96boards@ucrobotics.com
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 v1 -> v2:
 * Reworded subject
 * Added memory@0 node for Bubblegum-96 (Mark)
 * Filled in reserved-memory sub-node for Bubblegum-96 (Mark)
 * Added arm-pmu interrupt-affinity property (Mark)
 * Changed second GIC reg size 0x1000 -> 0x2000 for Bubblegum-96 (Mark)
 * Updated ARCH_OWL to ARCH_ACTIONS (Arnd)
 * Renamed s900-bubblegum96.dts to s900-bubblegum-96.dts
 * Adopted "actions" vendor prefix
 * Dropped irq.h include
 * Adopted SPDX-License-Identifier (Rob)
 
 arch/arm64/boot/dts/Makefile                      |   1 +
 arch/arm64/boot/dts/actions/Makefile              |   5 +
 arch/arm64/boot/dts/actions/s900-bubblegum-96.dts |  31 ++++++
 arch/arm64/boot/dts/actions/s900.dtsi             | 109 ++++++++++++++++++++++
 4 files changed, 146 insertions(+)
 create mode 100644 arch/arm64/boot/dts/actions/Makefile
 create mode 100644 arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
 create mode 100644 arch/arm64/boot/dts/actions/s900.dtsi

diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 080232b..d1a6b0a 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,3 +1,4 @@
+dts-dirs += actions
 dts-dirs += al
 dts-dirs += allwinner
 dts-dirs += altera
diff --git a/arch/arm64/boot/dts/actions/Makefile b/arch/arm64/boot/dts/actions/Makefile
new file mode 100644
index 0000000..62922d6
--- /dev/null
+++ b/arch/arm64/boot/dts/actions/Makefile
@@ -0,0 +1,5 @@
+dtb-$(CONFIG_ARCH_ACTIONS) += s900-bubblegum-96.dtb
+
+always		:= $(dtb-y)
+subdir-y	:= $(dts-dirs)
+clean-files	:= *.dtb
diff --git a/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
new file mode 100644
index 0000000..a4ab7df
--- /dev/null
+++ b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2017 Andreas Färber
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+/dts-v1/;
+
+#include "s900.dtsi"
+
+/ {
+	compatible = "ucrobotics,bubblegum-96", "actions,s900";
+	model = "Bubblegum-96";
+
+	aliases {
+		serial5 = &uart5;
+	};
+
+	chosen {
+		stdout-path = "serial5:115200n8";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x80000000>;
+	};
+};
+
+&uart5 {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/actions/s900.dtsi b/arch/arm64/boot/dts/actions/s900.dtsi
new file mode 100644
index 0000000..75e1dea2
--- /dev/null
+++ b/arch/arm64/boot/dts/actions/s900.dtsi
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2017 Andreas Färber
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "actions,s900";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53", "arm,armv8";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53", "arm,armv8";
+			reg = <0x0 0x1>;
+			enable-method = "psci";
+		};
+
+		cpu2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53", "arm,armv8";
+			reg = <0x0 0x2>;
+			enable-method = "psci";
+		};
+
+		cpu3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53", "arm,armv8";
+			reg = <0x0 0x3>;
+			enable-method = "psci";
+		};
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		secmon@1f000000 {
+			reg = <0x0 0x1f000000 0x0 0x1000000>;
+			no-map;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	arm-pmu {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+		             <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+		             <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+		             <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		gic: interrupt-controller@e00f1000 {
+			compatible = "arm,gic-400";
+			reg = <0x0 0xe00f1000 0x0 0x1000>,
+			      <0x0 0xe00f2000 0x0 0x2000>,
+			      <0x0 0xe00f4000 0x0 0x2000>,
+			      <0x0 0xe00f6000 0x0 0x2000>;
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+		};
+
+		uart5: serial@e012a000 {
+			compatible = "actions,s900-uart", "actions,owl-uart";
+			reg = <0x0 0xe012a000 0x0 0x1000>;
+			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+	};
+};
-- 
2.10.2

Re: [RFC v2 13/17] ARM64: dts: Add Actions Semi S900 and Bubblegum-96

[Andreas Färber]

Am 24.02.2017 um 04:40 schrieb Andreas Färber:
> Cc: 96boards@ucrobotics.com
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> ---
>  v1 -> v2:
>  * Reworded subject
>  * Added memory@0 node for Bubblegum-96 (Mark)
>  * Filled in reserved-memory sub-node for Bubblegum-96 (Mark)
>  * Added arm-pmu interrupt-affinity property (Mark)
>  * Changed second GIC reg size 0x1000 -> 0x2000 for Bubblegum-96 (Mark)
>  * Updated ARCH_OWL to ARCH_ACTIONS (Arnd)
>  * Renamed s900-bubblegum96.dts to s900-bubblegum-96.dts
>  * Adopted "actions" vendor prefix
>  * Dropped irq.h include
>  * Adopted SPDX-License-Identifier (Rob)

Sorry, not this patch but the tty patches 15ff/17 should've been RFC.

Regards,
Andreas

-- 
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)

[RFC v2 14/17] MAINTAINERS: Add Actions Semi Owl section

[Andreas Färber]

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 v2: new
 
 MAINTAINERS | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index b9af886..467121e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1026,6 +1026,16 @@ S:	Maintained
 F:	drivers/amba/
 F:	include/linux/amba/bus.h
 
+ARM/ACTIONS SEMI ARCHITECTURE
+M:	Andreas Färber <afaerber@suse.de>
+L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+S:	Maintained
+N:	owl
+F:	arch/arm/mach-actions/
+F:	arch/arm/boot/dts/s500*
+F:	arch/arm64/boot/dts/actions/
+F:	Documentation/devicetree/bindings/arm/actions.txt
+
 ARM/ADS SPHERE MACHINE SUPPORT
 M:	Lennert Buytenhek <kernel@wantstofly.org>
 L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
-- 
2.10.2

[PATCH v2 15/17] tty: serial: owl: Implement console driver

[Andreas Färber]

Implement serial console driver to complement earlycon.

Based on LeMaker linux-actions tree.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 v2: new
 
 drivers/tty/serial/Kconfig       |   4 +-
 drivers/tty/serial/owl-uart.c    | 574 ++++++++++++++++++++++++++++++++++++++-
 include/uapi/linux/serial_core.h |   3 +
 3 files changed, 578 insertions(+), 3 deletions(-)

diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index e145822..ef232ac 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1678,7 +1678,7 @@ config SERIAL_MVEBU_CONSOLE
 	  Otherwise, say 'N'.
 
 config SERIAL_OWL
-	bool "Actions Semi Owl serial port support"
+	tristate "Actions Semi Owl serial port support"
 	depends on ARCH_ACTIONS || COMPILE_TEST
 	select SERIAL_CORE
 	help
@@ -1694,7 +1694,7 @@ config SERIAL_OWL_CONSOLE
 	default y
 	help
 	  Say 'Y' here if you wish to use Actions Semiconductor S500/S900 UART
-	  as the system console. Only earlycon is implemented currently.
+	  as the system console.
 
 endmenu
 
diff --git a/drivers/tty/serial/owl-uart.c b/drivers/tty/serial/owl-uart.c
index e097443..c249472 100644
--- a/drivers/tty/serial/owl-uart.c
+++ b/drivers/tty/serial/owl-uart.c
@@ -20,6 +20,7 @@
  * along with this program. If not, see <http://www.gnu.org/licenses/>.
  */
 
+#include <linux/clk.h>
 #include <linux/console.h>
 #include <linux/delay.h>
 #include <linux/io.h>
@@ -28,22 +29,52 @@
 #include <linux/platform_device.h>
 #include <linux/serial.h>
 #include <linux/serial_core.h>
+#include <linux/tty.h>
+#include <linux/tty_flip.h>
+
+#define OWL_UART_PORT_NUM 7
+#define OWL_UART_DEV_NAME "ttyOWL"
 
 #define OWL_UART_CTL	0x000
+#define OWL_UART_RXDAT	0x004
 #define OWL_UART_TXDAT	0x008
 #define OWL_UART_STAT	0x00c
 
+#define OWL_UART_CTL_DWLS_MASK		(0x3 << 0)
+#define OWL_UART_CTL_DWLS_5BITS		(0x0 << 0)
+#define OWL_UART_CTL_DWLS_6BITS		(0x1 << 0)
+#define OWL_UART_CTL_DWLS_7BITS		(0x2 << 0)
+#define OWL_UART_CTL_DWLS_8BITS		(0x3 << 0)
+#define OWL_UART_CTL_STPS_2BITS		(1 << 2)
+#define OWL_UART_CTL_PRS_MASK		(0x7 << 4)
+#define OWL_UART_CTL_PRS_NONE		(0x0 << 4)
+#define OWL_UART_CTL_PRS_ODD		(0x4 << 4)
+#define OWL_UART_CTL_PRS_MARK		(0x5 << 4)
+#define OWL_UART_CTL_PRS_EVEN		(0x6 << 4)
+#define OWL_UART_CTL_PRS_SPACE		(0x7 << 4)
+#define OWL_UART_CTL_AFE		(1 << 12)
 #define OWL_UART_CTL_TRFS_TX		(1 << 14)
 #define OWL_UART_CTL_EN			(1 << 15)
+#define OWL_UART_CTL_RXDE		(1 << 16)
+#define OWL_UART_CTL_TXDE		(1 << 17)
 #define OWL_UART_CTL_RXIE		(1 << 18)
 #define OWL_UART_CTL_TXIE		(1 << 19)
 
 #define OWL_UART_STAT_RIP		(1 << 0)
 #define OWL_UART_STAT_TIP		(1 << 1)
+#define OWL_UART_STAT_RXER		(1 << 2)
+#define OWL_UART_STAT_TFER		(1 << 3)
+#define OWL_UART_STAT_RXST		(1 << 4)
+#define OWL_UART_STAT_RFEM		(1 << 5)
 #define OWL_UART_STAT_TFFU		(1 << 6)
+#define OWL_UART_STAT_TFES		(1 << 10)
 #define OWL_UART_STAT_TRFL_MASK		(0x1f << 11)
 #define OWL_UART_STAT_UTBB		(1 << 17)
 
+static struct uart_driver owl_uart_driver;
+
+static struct uart_port *owl_uart_ports[OWL_UART_PORT_NUM];
+
 static inline void owl_uart_write(struct uart_port *port, u32 val, unsigned int off)
 {
 	writel(val, port->membase + off);
@@ -54,6 +85,377 @@ static inline u32 owl_uart_read(struct uart_port *port, unsigned int off)
 	return readl(port->membase + off);
 }
 
+static void owl_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
+{
+}
+
+static unsigned int owl_uart_get_mctrl(struct uart_port *port)
+{
+	return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
+}
+
+static unsigned int owl_uart_tx_empty(struct uart_port *port)
+{
+	unsigned long flags;
+	u32 val;
+	unsigned int ret;
+
+	spin_lock_irqsave(&port->lock, flags);
+
+	val = owl_uart_read(port, OWL_UART_STAT);
+	ret = (val & OWL_UART_STAT_TFES) ? TIOCSER_TEMT : 0;
+
+	spin_unlock_irqrestore(&port->lock, flags);
+
+	return ret;
+}
+
+static void owl_uart_stop_rx(struct uart_port *port)
+{
+	u32 val;
+
+	val = owl_uart_read(port, OWL_UART_CTL);
+	val &= ~(OWL_UART_CTL_RXIE | OWL_UART_CTL_RXDE);
+	owl_uart_write(port, val, OWL_UART_CTL);
+
+	val = owl_uart_read(port, OWL_UART_STAT);
+	val |= OWL_UART_STAT_RIP;
+	owl_uart_write(port, val, OWL_UART_STAT);
+}
+
+static void owl_uart_stop_tx(struct uart_port *port)
+{
+	u32 val;
+
+	val = owl_uart_read(port, OWL_UART_CTL);
+	val &= ~(OWL_UART_CTL_TXIE | OWL_UART_CTL_TXDE);
+	owl_uart_write(port, val, OWL_UART_CTL);
+
+	val = owl_uart_read(port, OWL_UART_STAT);
+	val |= OWL_UART_STAT_TIP;
+	owl_uart_write(port, val, OWL_UART_STAT);
+}
+
+static void owl_uart_start_tx(struct uart_port *port)
+{
+	u32 val;
+
+	if (uart_tx_stopped(port)) {
+		owl_uart_stop_tx(port);
+		return;
+	}
+
+	val = owl_uart_read(port, OWL_UART_STAT);
+	val |= OWL_UART_STAT_TIP;
+	owl_uart_write(port, val, OWL_UART_STAT);
+
+	val = owl_uart_read(port, OWL_UART_CTL);
+	val |= OWL_UART_CTL_TXIE;
+	owl_uart_write(port, val, OWL_UART_CTL);
+}
+
+static void owl_uart_send_chars(struct uart_port *port)
+{
+	struct circ_buf *xmit = &port->state->xmit;
+	unsigned int ch;
+
+	if (uart_tx_stopped(port))
+		return;
+
+	if (port->x_char) {
+		while (!(owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU))
+			cpu_relax();
+		owl_uart_write(port, port->x_char, OWL_UART_TXDAT);
+		port->icount.tx++;
+		port->x_char = 0;
+	}
+
+	while (!(owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU)) {
+		if (uart_circ_empty(xmit))
+			break;
+
+		ch = xmit->buf[xmit->tail];
+		owl_uart_write(port, ch, OWL_UART_TXDAT);
+		xmit->tail = (xmit->tail + 1) & (SERIAL_XMIT_SIZE - 1);
+		port->icount.tx++;
+	}
+
+	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+		uart_write_wakeup(port);
+
+	if (uart_circ_empty(xmit))
+		owl_uart_stop_tx(port);
+}
+
+static void owl_uart_receive_chars(struct uart_port *port)
+{
+	u32 stat, val;
+
+	val = owl_uart_read(port, OWL_UART_CTL);
+	val &= ~OWL_UART_CTL_TRFS_TX;
+	owl_uart_write(port, val, OWL_UART_CTL);
+
+	stat = owl_uart_read(port, OWL_UART_STAT);
+	while (!(stat & OWL_UART_STAT_RFEM)) {
+		char flag = TTY_NORMAL;
+
+		if (stat & OWL_UART_STAT_RXER)
+			port->icount.overrun++;
+
+		if (stat & OWL_UART_STAT_RXST) {
+			/* We are not able to distinguish the error type. */
+			port->icount.brk++;
+			port->icount.frame++;
+
+			stat &= port->read_status_mask;
+			if (stat & OWL_UART_STAT_RXST)
+				flag = TTY_PARITY;
+		} else
+			port->icount.rx++;
+
+		val = owl_uart_read(port, OWL_UART_RXDAT);
+		val &= 0xff;
+
+		if ((stat & port->ignore_status_mask) == 0)
+			tty_insert_flip_char(&port->state->port, val, flag);
+
+		stat = owl_uart_read(port, OWL_UART_STAT);
+	}
+
+	spin_unlock(&port->lock);
+	tty_flip_buffer_push(&port->state->port);
+	spin_lock(&port->lock);
+}
+
+static irqreturn_t owl_uart_irq(int irq, void *dev_id)
+{
+	struct uart_port *port = (struct uart_port *)dev_id;
+	u32 stat;
+
+	spin_lock(&port->lock);
+
+	stat = owl_uart_read(port, OWL_UART_STAT);
+
+	if (stat & OWL_UART_STAT_RIP)
+		owl_uart_receive_chars(port);
+
+	if (stat & OWL_UART_STAT_TIP)
+		owl_uart_send_chars(port);
+
+	stat = owl_uart_read(port, OWL_UART_STAT);
+	stat |= OWL_UART_STAT_RIP | OWL_UART_STAT_TIP;
+	owl_uart_write(port, stat, OWL_UART_STAT);
+
+	spin_unlock(&port->lock);
+
+	return IRQ_HANDLED;
+}
+
+static void owl_uart_shutdown(struct uart_port *port)
+{
+	u32 val;
+	unsigned long flags;
+
+	spin_lock_irqsave(&port->lock, flags);
+
+	val = owl_uart_read(port, OWL_UART_CTL);
+	val &= ~(OWL_UART_CTL_TXIE | OWL_UART_CTL_RXIE
+		| OWL_UART_CTL_TXDE | OWL_UART_CTL_RXDE | OWL_UART_CTL_EN);
+	owl_uart_write(port, val, OWL_UART_CTL);
+
+	spin_unlock_irqrestore(&port->lock, flags);
+
+	free_irq(port->irq, port);
+}
+
+static int owl_uart_startup(struct uart_port *port)
+{
+	u32 val;
+	unsigned long flags;
+	int ret;
+
+	ret = request_irq(port->irq, owl_uart_irq, IRQF_TRIGGER_HIGH,
+			"owl-uart", port);
+	if (ret)
+		return ret;
+
+	spin_lock_irqsave(&port->lock, flags);
+
+	val = owl_uart_read(port, OWL_UART_STAT);
+	val |= OWL_UART_STAT_RIP | OWL_UART_STAT_TIP
+		| OWL_UART_STAT_RXER | OWL_UART_STAT_TFER | OWL_UART_STAT_RXST;
+	owl_uart_write(port, val, OWL_UART_STAT);
+
+	val = owl_uart_read(port, OWL_UART_CTL);
+	val |= OWL_UART_CTL_RXIE | OWL_UART_CTL_TXIE;
+	val |= OWL_UART_CTL_EN;
+	owl_uart_write(port, val, OWL_UART_CTL);
+
+	spin_unlock_irqrestore(&port->lock, flags);
+
+	return 0;
+}
+
+static void owl_uart_change_baudrate(struct uart_port *port, unsigned long baud)
+{
+}
+
+static void owl_uart_set_termios(struct uart_port *port,
+				 struct ktermios *termios,
+				 struct ktermios *old)
+{
+	unsigned int baud;
+	u32 ctl;
+	unsigned long flags;
+
+	spin_lock_irqsave(&port->lock, flags);
+
+	/* We don't support modem control lines. */
+	termios->c_cflag &= ~(HUPCL | CMSPAR);
+	termios->c_cflag |= CLOCAL;
+
+	/* We don't support BREAK character recognition. */
+	termios->c_iflag &= ~(IGNBRK | BRKINT);
+
+	ctl = owl_uart_read(port, OWL_UART_CTL);
+
+	ctl &= ~OWL_UART_CTL_DWLS_MASK;
+	switch (termios->c_cflag & CSIZE) {
+	case CS5:
+		ctl |= OWL_UART_CTL_DWLS_5BITS;
+		break;
+	case CS6:
+		ctl |= OWL_UART_CTL_DWLS_6BITS;
+		break;
+	case CS7:
+		ctl |= OWL_UART_CTL_DWLS_7BITS;
+		break;
+	case CS8:
+	default:
+		ctl |= OWL_UART_CTL_DWLS_8BITS;
+		break;
+	}
+
+	if (termios->c_cflag & CSTOPB)
+		ctl |= OWL_UART_CTL_STPS_2BITS;
+	else
+		ctl &= ~OWL_UART_CTL_STPS_2BITS;
+
+	ctl &= ~OWL_UART_CTL_PRS_MASK;
+	if (termios->c_cflag & PARENB) {
+		if (termios->c_cflag & CMSPAR) {
+			if (termios->c_cflag & PARODD)
+				ctl |= OWL_UART_CTL_PRS_MARK;
+			else
+				ctl |= OWL_UART_CTL_PRS_SPACE;
+		} else if (termios->c_cflag & PARODD)
+			ctl |= OWL_UART_CTL_PRS_ODD;
+		else
+			ctl |= OWL_UART_CTL_PRS_EVEN;
+	} else
+		ctl |= OWL_UART_CTL_PRS_NONE;
+
+	if (termios->c_cflag & CRTSCTS)
+		ctl |= OWL_UART_CTL_AFE;
+	else
+		ctl &= ~OWL_UART_CTL_AFE;
+
+	owl_uart_write(port, ctl, OWL_UART_CTL);
+
+	baud = uart_get_baud_rate(port, termios, old, 9600, 3200000);
+	owl_uart_change_baudrate(port, baud);
+
+	port->read_status_mask |= OWL_UART_STAT_RXER;
+	if (termios->c_iflag & INPCK)
+		port->read_status_mask |= OWL_UART_STAT_RXST;
+
+	uart_update_timeout(port, termios->c_cflag, baud);
+
+	spin_unlock_irqrestore(&port->lock, flags);
+}
+
+static void owl_uart_release_port(struct uart_port *port)
+{
+	struct platform_device *pdev = to_platform_device(port->dev);
+	struct resource *res;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res)
+		return;
+
+	if (port->flags & UPF_IOREMAP) {
+		devm_release_mem_region(port->dev, port->mapbase,
+			resource_size(res));
+		devm_iounmap(port->dev, port->membase);
+		port->membase = NULL;
+	}
+}
+
+static int owl_uart_request_port(struct uart_port *port)
+{
+	struct platform_device *pdev = to_platform_device(port->dev);
+	struct resource *res;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res)
+		return -ENXIO;
+
+	if (!devm_request_mem_region(port->dev, port->mapbase,
+			resource_size(res), dev_name(port->dev)))
+		return -EBUSY;
+
+	if (port->flags & UPF_IOREMAP) {
+		port->membase = devm_ioremap_nocache(port->dev, port->mapbase,
+				resource_size(res));
+		if (!port->membase)
+			return -EBUSY;
+	}
+
+	return 0;
+}
+
+static const char *owl_uart_type(struct uart_port *port)
+{
+	return (port->type == PORT_OWL) ? "owl-uart" : NULL;
+}
+
+static int owl_uart_verify_port(struct uart_port *port,
+				struct serial_struct *ser)
+{
+	if (port->type != PORT_OWL)
+		return -EINVAL;
+
+	if (port->irq != ser->irq)
+		return -EINVAL;
+
+	return 0;
+}
+
+static void owl_uart_config_port(struct uart_port *port, int flags)
+{
+	if (flags & UART_CONFIG_TYPE) {
+		port->type = PORT_OWL;
+		owl_uart_request_port(port);
+	}
+}
+
+static struct uart_ops owl_uart_ops = {
+	.set_mctrl = owl_uart_set_mctrl,
+	.get_mctrl = owl_uart_get_mctrl,
+	.tx_empty = owl_uart_tx_empty,
+	.start_tx = owl_uart_start_tx,
+	.stop_rx = owl_uart_stop_rx,
+	.stop_tx = owl_uart_stop_tx,
+	.startup = owl_uart_startup,
+	.shutdown = owl_uart_shutdown,
+	.set_termios = owl_uart_set_termios,
+	.type = owl_uart_type,
+	.config_port = owl_uart_config_port,
+	.request_port = owl_uart_request_port,
+	.release_port = owl_uart_release_port,
+	.verify_port = owl_uart_verify_port,
+};
+
 #ifdef CONFIG_SERIAL_OWL_CONSOLE
 
 static void owl_console_putchar(struct uart_port *port, int ch)
@@ -110,6 +512,57 @@ static void owl_uart_port_write(struct uart_port *port, const char *s,
 	local_irq_restore(flags);
 }
 
+static void owl_uart_console_write(struct console *co, const char *s,
+				   u_int count)
+{
+	struct uart_port *port;
+
+	port = owl_uart_ports[co->index];
+	if (!port)
+		return;
+
+	owl_uart_port_write(port, s, count);
+}
+
+static int owl_uart_console_setup(struct console *co, char *options)
+{
+	struct uart_port *port;
+	int baud = 115200;
+	int bits = 8;
+	int parity = 'n';
+	int flow = 'n';
+
+	if (co->index < 0 || co->index >= OWL_UART_PORT_NUM)
+		return -EINVAL;
+
+	port = owl_uart_ports[co->index];
+	if (!port || !port->membase)
+		return -ENODEV;
+
+	if (options)
+		uart_parse_options(options, &baud, &parity, &bits, &flow);
+
+	return uart_set_options(port, co, baud, parity, bits, flow);
+}
+
+static struct console owl_uart_console = {
+	.name = OWL_UART_DEV_NAME,
+	.write = owl_uart_console_write,
+	.device = uart_console_device,
+	.setup = owl_uart_console_setup,
+	.flags = CON_PRINTBUFFER,
+	.index = -1,
+	.data = &owl_uart_driver,
+};
+
+static int __init owl_uart_console_init(void)
+{
+	register_console(&owl_uart_console);
+
+	return 0;
+}
+console_initcall(owl_uart_console_init);
+
 static void owl_uart_early_console_write(struct console *co,
 					 const char *s,
 					 u_int count)
@@ -132,4 +585,123 @@ owl_uart_early_console_setup(struct earlycon_device *device, const char *opt)
 OF_EARLYCON_DECLARE(owl, "actions,owl-uart",
 		    owl_uart_early_console_setup);
 
-#endif /* CONFIG_SERIAL_OWL_CONSOLE */
+#define OWL_UART_CONSOLE (&owl_uart_console)
+#else
+#define OWL_UART_CONSOLE NULL
+#endif
+
+static struct uart_driver owl_uart_driver = {
+	.owner = THIS_MODULE,
+	.driver_name = "owl-uart",
+	.dev_name = OWL_UART_DEV_NAME,
+	.nr = OWL_UART_PORT_NUM,
+	.cons = OWL_UART_CONSOLE,
+};
+
+static int owl_uart_probe(struct platform_device *pdev)
+{
+	struct resource *res_mem, *res_irq;
+	struct uart_port *port;
+	struct clk *clk;
+	int ret;
+
+	if (pdev->dev.of_node)
+		pdev->id = of_alias_get_id(pdev->dev.of_node, "serial");
+
+	if (pdev->id < 0 || pdev->id >= OWL_UART_PORT_NUM)
+		return -EINVAL;
+
+	res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res_mem)
+		return -ENODEV;
+
+	res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (!res_irq)
+		return -ENODEV;
+
+	if (owl_uart_ports[pdev->id]) {
+		dev_err(&pdev->dev, "port %d already allocated\n", pdev->id);
+		return -EBUSY;
+	}
+
+	port = devm_kzalloc(&pdev->dev, sizeof(struct uart_port), GFP_KERNEL);
+	if (!port)
+		return -ENOMEM;
+
+	clk = clk_get(&pdev->dev, NULL);
+	if (IS_ERR(clk))
+		return PTR_ERR(clk);
+
+	port->dev = &pdev->dev;
+	port->line = pdev->id;
+	port->type = PORT_OWL;
+	port->iotype = UPIO_MEM;
+	port->mapbase = res_mem->start;
+	port->irq = res_irq->start;
+	port->uartclk = clk_get_rate(clk);
+	port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_LOW_LATENCY;
+	port->x_char = 0;
+	port->fifosize = 16;
+	port->ops = &owl_uart_ops;
+
+	owl_uart_ports[pdev->id] = port;
+	platform_set_drvdata(pdev, port);
+
+	ret = uart_add_one_port(&owl_uart_driver, port);
+	if (ret)
+		owl_uart_ports[pdev->id] = NULL;
+
+	return ret;
+}
+
+static int owl_uart_remove(struct platform_device *pdev)
+{
+	struct uart_port *port;
+
+	port = platform_get_drvdata(pdev);
+	uart_remove_one_port(&owl_uart_driver, port);
+	owl_uart_ports[pdev->id] = NULL;
+
+	return 0;
+}
+
+static const struct of_device_id owl_uart_dt_matches[] = {
+	{ .compatible = "actions,owl-uart" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, owl_uart_dt_matches);
+
+static struct platform_driver owl_uart_platform_driver = {
+	.probe = owl_uart_probe,
+	.remove = owl_uart_remove,
+	.driver = {
+		.name = "owl-uart",
+		.of_match_table = owl_uart_dt_matches,
+	},
+};
+
+static int __init owl_uart_init(void)
+{
+	int ret;
+
+	ret = uart_register_driver(&owl_uart_driver);
+	if (ret)
+		return ret;
+
+	ret = platform_driver_register(&owl_uart_platform_driver);
+	if (ret)
+		uart_unregister_driver(&owl_uart_driver);
+
+	return ret;
+}
+
+static void __init owl_uart_exit(void)
+{
+	platform_driver_unregister(&owl_uart_platform_driver);
+	uart_unregister_driver(&owl_uart_driver);
+}
+
+module_init(owl_uart_init);
+module_exit(owl_uart_exit);
+
+MODULE_LICENSE("GPL");
diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h
index 9ec741b..5e850e6 100644
--- a/include/uapi/linux/serial_core.h
+++ b/include/uapi/linux/serial_core.h
@@ -271,4 +271,7 @@
 /* MPS2 UART */
 #define PORT_MPS2UART	116
 
+/* Actions Semi Owl UART */
+#define PORT_OWL	117
+
 #endif /* _UAPILINUX_SERIAL_CORE_H */
-- 
2.10.2

[PATCH v2 16/17] ARM64: dts: actions: s900-bubblegum-96: Add fake uart5 clk

[Andreas Färber]

Give the serial driver a fixed-clock as input for baudrate 115200.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 v2: new
 
 arch/arm64/boot/dts/actions/s900-bubblegum-96.dts | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
index a4ab7df..e25f606 100644
--- a/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
+++ b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts
@@ -24,8 +24,15 @@
 		device_type = "memory";
 		reg = <0x0 0x0 0x0 0x80000000>;
 	};
+
+	uart5_clk: uart5-clk {
+		compatible = "fixed-clock";
+		clock-frequency = <921600>;
+		#clock-cells = <0>;
+	};
 };
 
 &uart5 {
 	status = "okay";
+	clocks = <&uart5_clk>;
 };
-- 
2.10.2

[PATCH v2 17/17] ARM: dts: s500-guitar-bb-rev-b: Add fake uart3 clock

[Andreas Färber]

Add a fixed-clock for baudrate 115200.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 v2: new
 
 arch/arm/boot/dts/s500-guitar-bb-rev-b.dts | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/s500-guitar-bb-rev-b.dts b/arch/arm/boot/dts/s500-guitar-bb-rev-b.dts
index 834b71d..f6fd10a 100644
--- a/arch/arm/boot/dts/s500-guitar-bb-rev-b.dts
+++ b/arch/arm/boot/dts/s500-guitar-bb-rev-b.dts
@@ -19,8 +19,15 @@
 	chosen {
 		stdout-path = "serial3:115200n8";
 	};
+
+	uart3_clk: uart3-clk {
+		compatible = "fixed-clock";
+		clock-frequency = <921600>;
+		#clock-cells = <0>;
+	};
 };
 
 &uart3 {
 	status = "okay";
+	clocks = <&uart3_clk>;
 };
-- 
2.10.2