* [PATCH] clk: sunxi-ng: sun5i: Fix mux width for csi clock
@ 2017-03-02 20:55 Priit Laes
2017-03-03 7:12 ` Maxime Ripard
0 siblings, 1 reply; 2+ messages in thread
From: Priit Laes @ 2017-03-02 20:55 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Maxime Ripard, Chen-Yu Tsai
Cc: linux-clk, linux-arm-kernel, linux-kernel, linux-sunxi, Priit Laes
Mux for CSI clock is 3 bits, not 2.
Signed-off-by: Priit Laes <plaes@plaes.org>
---
drivers/clk/sunxi-ng/ccu-sun5i.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun5i.c b/drivers/clk/sunxi-ng/ccu-sun5i.c
index 06edaa5..5c476f9 100644
--- a/drivers/clk/sunxi-ng/ccu-sun5i.c
+++ b/drivers/clk/sunxi-ng/ccu-sun5i.c
@@ -469,7 +469,7 @@ static const char * const csi_parents[] = { "hosc", "pll-video0", "pll-video1",
static const u8 csi_table[] = { 0, 1, 2, 5, 6 };
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_clk, "csi",
csi_parents, csi_table,
- 0x134, 0, 5, 24, 2, BIT(31), 0);
+ 0x134, 0, 5, 24, 3, BIT(31), 0);
static SUNXI_CCU_GATE(ve_clk, "ve", "pll-ve",
0x13c, BIT(31), CLK_SET_RATE_PARENT);
--
2.9.3
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] clk: sunxi-ng: sun5i: Fix mux width for csi clock
2017-03-02 20:55 [PATCH] clk: sunxi-ng: sun5i: Fix mux width for csi clock Priit Laes
@ 2017-03-03 7:12 ` Maxime Ripard
0 siblings, 0 replies; 2+ messages in thread
From: Maxime Ripard @ 2017-03-03 7:12 UTC (permalink / raw)
To: Priit Laes
Cc: Michael Turquette, Stephen Boyd, Chen-Yu Tsai, linux-clk,
linux-arm-kernel, linux-kernel, linux-sunxi
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On Thu, Mar 02, 2017 at 10:55:27PM +0200, Priit Laes wrote:
> Mux for CSI clock is 3 bits, not 2.
>
> Signed-off-by: Priit Laes <plaes@plaes.org>
Applied, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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