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From: Mark Rutland <mark.rutland@arm.com>
To: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
Cc: linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, Will.Deacon@arm.com,
	catalin.marinas@arm.com, acme@kernel.org,
	alexander.shishkin@linux.intel.com, peterz@infradead.org,
	mingo@redhat.com, jnair@caviumnetworks.com, gpkulkarni@gmail.com
Subject: Re: [PATCH 3/3] perf tool, arm64, thunderx2: Add implementation defined events for ThunderX2
Date: Tue, 4 Apr 2017 13:28:29 +0100	[thread overview]
Message-ID: <20170404122828.GB8551@leverpostej> (raw)
In-Reply-To: <1491291403-29893-4-git-send-email-ganapatrao.kulkarni@cavium.com>

On Tue, Apr 04, 2017 at 01:06:43PM +0530, Ganapatrao Kulkarni wrote:
> This is not a full event list, but a short list of useful events.
> 
> Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
> ---
>  tools/perf/pmu-events/arch/arm64/mapfile.csv       |  2 +
>  .../arm64/thunderx2/implementation-defined.json    | 72 ++++++++++++++++++++++
>  2 files changed, 74 insertions(+)
>  create mode 100644 tools/perf/pmu-events/arch/arm64/mapfile.csv
>  create mode 100644 tools/perf/pmu-events/arch/arm64/thunderx2/implementation-defined.json
> 
> diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
> new file mode 100644
> index 0000000..ba30e43
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
> @@ -0,0 +1,2 @@
> +Family-model,Version,Filename,EventType
> +0x00000000420f5161,v1,thunderx2,core
> diff --git a/tools/perf/pmu-events/arch/arm64/thunderx2/implementation-defined.json b/tools/perf/pmu-events/arch/arm64/thunderx2/implementation-defined.json
> new file mode 100644
> index 0000000..360e084
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/arm64/thunderx2/implementation-defined.json
> @@ -0,0 +1,72 @@
> +[
> +    {
> +        "PublicDescription": "Attributable Level 1 data cache access, read",
> +        "EventCode": "0x40",
> +        "EventName": "l1d_cache_access_read",
> +        "BriefDescription": "l1d cache access, read",
> +	"CPU" :"armv8_pmuv3_0"

Please let's not hard-code the name like this. Surely we can get rid of this?

The kernel doesn't currently name PMUs as armv8_pmuv3_*, and as that can
differ across DT/ACPI and in big.LITTLE, I don't think it makes sense to
try to rely one particular string regardless.

Thanks,
Mark.

  reply	other threads:[~2017-04-04 12:28 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-04-04  7:36 [PATCH 0/3] Add support for ThunderX2 pmu events using json files Ganapatrao Kulkarni
2017-04-04  7:36 ` [PATCH 1/3] perf jevents: Add support to use core pmu name other than cpu Ganapatrao Kulkarni
2017-04-04  7:36 ` [PATCH 2/3] perf tools arm64: implement function get_cpuid_str Ganapatrao Kulkarni
2017-04-04 12:25   ` Mark Rutland
2017-04-05  9:18     ` Ganapatrao Kulkarni
2017-04-04  7:36 ` [PATCH 3/3] perf tool, arm64, thunderx2: Add implementation defined events for ThunderX2 Ganapatrao Kulkarni
2017-04-04 12:28   ` Mark Rutland [this message]
2017-04-05  9:12     ` Ganapatrao Kulkarni
2017-04-05 10:05       ` Mark Rutland
2017-04-06  4:20         ` Ganapatrao Kulkarni
2017-04-06  9:55           ` Mark Rutland
2017-04-19 18:07             ` Ganapatrao Kulkarni
2017-04-20  8:53               ` Mark Rutland
2017-04-04 12:29 ` [PATCH 0/3] Add support for ThunderX2 pmu events using json files Mark Rutland

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