* [PATCH 1/3] phy: sun4i-usb: enable PHY0 dual route switching for A64 USB PHY
@ 2017-04-04 18:45 Icenowy Zheng
2017-04-04 18:45 ` [PATCH 2/3] arm64: allwinner: a64: add USB0 OHCI/EHCI related devicetree parts Icenowy Zheng
` (2 more replies)
0 siblings, 3 replies; 11+ messages in thread
From: Icenowy Zheng @ 2017-04-04 18:45 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai, Kishon Vijay Abraham I
Cc: linux-arm-kernel, devicetree, linux-kernel, linux-sunxi, Icenowy Zheng
Allwinner A64 SoC features a switchable PHY0 like the one in H3, which
can switch between a MUSB controller and a pair of OHCI/EHCI controller.
Enable PHY0 route auto switching for A64.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
drivers/phy/phy-sun4i-usb.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
index f86a2574b953..bbf06cfe5898 100644
--- a/drivers/phy/phy-sun4i-usb.c
+++ b/drivers/phy/phy-sun4i-usb.c
@@ -858,6 +858,7 @@ static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
.phyctl_offset = REG_PHYCTL_A33,
.dedicated_clocks = true,
.enable_pmu_unk1 = true,
+ .phy0_dual_route = true,
};
static const struct of_device_id sun4i_usb_phy_of_match[] = {
--
2.12.2
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 2/3] arm64: allwinner: a64: add USB0 OHCI/EHCI related devicetree parts
2017-04-04 18:45 [PATCH 1/3] phy: sun4i-usb: enable PHY0 dual route switching for A64 USB PHY Icenowy Zheng
@ 2017-04-04 18:45 ` Icenowy Zheng
2017-04-05 7:15 ` Maxime Ripard
2017-04-04 18:45 ` [PATCH 3/3] arm64: allwinner: a64: enable EHCI0/OHCI0 controller for Pine64 Icenowy Zheng
2017-04-05 7:03 ` [PATCH 1/3] phy: sun4i-usb: enable PHY0 dual route switching for A64 USB PHY Maxime Ripard
2 siblings, 1 reply; 11+ messages in thread
From: Icenowy Zheng @ 2017-04-04 18:45 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai, Kishon Vijay Abraham I
Cc: linux-arm-kernel, devicetree, linux-kernel, linux-sunxi, Icenowy Zheng
As we added USB0 route auto switching support for A64, add related
device tree parts to the A64 DTSI file (EHCI0/OHCI0 controllers and the
pmu0 memory area for PHY).
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 1c64ea2d23f9..a8916df99048 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -179,8 +179,10 @@
usbphy: phy@01c19400 {
compatible = "allwinner,sun50i-a64-usb-phy";
reg = <0x01c19400 0x14>,
+ <0x01c1a800 0x4>,
<0x01c1b800 0x4>;
reg-names = "phy_ctrl",
+ "pmu0",
"pmu1";
clocks = <&ccu CLK_USB_PHY0>,
<&ccu CLK_USB_PHY1>;
@@ -194,6 +196,28 @@
#phy-cells = <1>;
};
+ ehci0: usb@01c1a000 {
+ compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
+ reg = <0x01c1a000 0x100>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI0>,
+ <&ccu CLK_BUS_EHCI0>,
+ <&ccu CLK_USB_OHCI0>;
+ resets = <&ccu RST_BUS_OHCI0>,
+ <&ccu RST_BUS_EHCI0>;
+ status = "disabled";
+ };
+
+ ohci0: usb@01c1a400 {
+ compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
+ reg = <0x01c1a400 0x100>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI0>,
+ <&ccu CLK_USB_OHCI0>;
+ resets = <&ccu RST_BUS_OHCI0>;
+ status = "disabled";
+ };
+
ehci1: usb@01c1b000 {
compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
reg = <0x01c1b000 0x100>;
--
2.12.2
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH 2/3] arm64: allwinner: a64: add USB0 OHCI/EHCI related devicetree parts
2017-04-04 18:45 ` [PATCH 2/3] arm64: allwinner: a64: add USB0 OHCI/EHCI related devicetree parts Icenowy Zheng
@ 2017-04-05 7:15 ` Maxime Ripard
[not found] ` <7828ffa0-f570-9841-a9e6-fe175f8169ac@aosc.io>
0 siblings, 1 reply; 11+ messages in thread
From: Maxime Ripard @ 2017-04-05 7:15 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Chen-Yu Tsai, Kishon Vijay Abraham I, linux-arm-kernel,
devicetree, linux-kernel, linux-sunxi
[-- Attachment #1: Type: text/plain, Size: 1114 bytes --]
On Wed, Apr 05, 2017 at 02:45:17AM +0800, Icenowy Zheng wrote:
> As we added USB0 route auto switching support for A64, add related
> device tree parts to the A64 DTSI file (EHCI0/OHCI0 controllers and the
> pmu0 memory area for PHY).
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
> arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 24 ++++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> index 1c64ea2d23f9..a8916df99048 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> @@ -179,8 +179,10 @@
> usbphy: phy@01c19400 {
> compatible = "allwinner,sun50i-a64-usb-phy";
> reg = <0x01c19400 0x14>,
> + <0x01c1a800 0x4>,
> <0x01c1b800 0x4>;
> reg-names = "phy_ctrl",
> + "pmu0",
This breaks the older DTs, and that property isn't documented.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 3/3] arm64: allwinner: a64: enable EHCI0/OHCI0 controller for Pine64
2017-04-04 18:45 [PATCH 1/3] phy: sun4i-usb: enable PHY0 dual route switching for A64 USB PHY Icenowy Zheng
2017-04-04 18:45 ` [PATCH 2/3] arm64: allwinner: a64: add USB0 OHCI/EHCI related devicetree parts Icenowy Zheng
@ 2017-04-04 18:45 ` Icenowy Zheng
2017-04-05 7:03 ` [PATCH 1/3] phy: sun4i-usb: enable PHY0 dual route switching for A64 USB PHY Maxime Ripard
2 siblings, 0 replies; 11+ messages in thread
From: Icenowy Zheng @ 2017-04-04 18:45 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai, Kishon Vijay Abraham I
Cc: linux-arm-kernel, devicetree, linux-kernel, linux-sunxi, Icenowy Zheng
The upper USB port of Pine64 board is connected to the SoC's USB0 port,
which can now switch from the MUSB controller to the EHCI/OHCI pair.
Enable the EHCI/OHCI pair in the Pine64 device tree.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
index c680ed385da3..4782add50b94 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
@@ -66,6 +66,10 @@
};
};
+&ehci0 {
+ status = "okay";
+};
+
&ehci1 {
status = "okay";
};
@@ -91,6 +95,10 @@
status = "okay";
};
+&ohci0 {
+ status = "okay";
+};
+
&ohci1 {
status = "okay";
};
--
2.12.2
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH 1/3] phy: sun4i-usb: enable PHY0 dual route switching for A64 USB PHY
2017-04-04 18:45 [PATCH 1/3] phy: sun4i-usb: enable PHY0 dual route switching for A64 USB PHY Icenowy Zheng
2017-04-04 18:45 ` [PATCH 2/3] arm64: allwinner: a64: add USB0 OHCI/EHCI related devicetree parts Icenowy Zheng
2017-04-04 18:45 ` [PATCH 3/3] arm64: allwinner: a64: enable EHCI0/OHCI0 controller for Pine64 Icenowy Zheng
@ 2017-04-05 7:03 ` Maxime Ripard
2017-04-05 9:59 ` Kishon Vijay Abraham I
2 siblings, 1 reply; 11+ messages in thread
From: Maxime Ripard @ 2017-04-05 7:03 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Chen-Yu Tsai, Kishon Vijay Abraham I, linux-arm-kernel,
devicetree, linux-kernel, linux-sunxi
[-- Attachment #1: Type: text/plain, Size: 502 bytes --]
On Wed, Apr 05, 2017 at 02:45:16AM +0800, Icenowy Zheng wrote:
> Allwinner A64 SoC features a switchable PHY0 like the one in H3, which
> can switch between a MUSB controller and a pair of OHCI/EHCI controller.
>
> Enable PHY0 route auto switching for A64.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Thanks,
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/3] phy: sun4i-usb: enable PHY0 dual route switching for A64 USB PHY
2017-04-05 7:03 ` [PATCH 1/3] phy: sun4i-usb: enable PHY0 dual route switching for A64 USB PHY Maxime Ripard
@ 2017-04-05 9:59 ` Kishon Vijay Abraham I
0 siblings, 0 replies; 11+ messages in thread
From: Kishon Vijay Abraham I @ 2017-04-05 9:59 UTC (permalink / raw)
To: Maxime Ripard, Icenowy Zheng
Cc: Chen-Yu Tsai, linux-arm-kernel, devicetree, linux-kernel, linux-sunxi
On Wednesday 05 April 2017 12:33 PM, Maxime Ripard wrote:
> On Wed, Apr 05, 2017 at 02:45:16AM +0800, Icenowy Zheng wrote:
>> Allwinner A64 SoC features a switchable PHY0 like the one in H3, which
>> can switch between a MUSB controller and a pair of OHCI/EHCI controller.
>>
>> Enable PHY0 route auto switching for A64.
>>
>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
>
> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
merged, thanks.
-Kishon
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 0/3] Allwinner A64 EHCI0/OHCI0 devicetree change
@ 2017-04-05 12:50 Icenowy Zheng
2017-04-05 12:50 ` [PATCH 2/3] arm64: allwinner: a64: add USB0 OHCI/EHCI related devicetree parts Icenowy Zheng
0 siblings, 1 reply; 11+ messages in thread
From: Icenowy Zheng @ 2017-04-05 12:50 UTC (permalink / raw)
To: Rob Herring, Maxime Ripard, Chen-Yu Tsai, Kishon Vijay Abraham I
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-sunxi, Icenowy Zheng
This patchset contains devicetree parts of the EHCI0/OHCI0 controllers
on A64 SoC.
The first patch is a devicetree binding change, which has been planned
for 4.12; however, as Maxime Ripard suggested, it should go in 4.11
as it's part of the device's description.
The second patch added pmu0 regs and EHCI/OHCI controllers for USB0.
The third patch enabled EHCI0/OHCI0 for Pine64 board.
This patchset should go in 4.11 as Maxime Ripard suggested.
Icenowy Zheng (3):
dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64
arm64: allwinner: a64: add USB0 OHCI/EHCI related devicetree parts
arm64: allwinner: a64: enable EHCI0/OHCI0 controller for Pine64
.../devicetree/bindings/phy/sun4i-usb-phy.txt | 1 +
.../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 8 ++++++++
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 24 ++++++++++++++++++++++
3 files changed, 33 insertions(+)
--
2.12.2
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 2/3] arm64: allwinner: a64: add USB0 OHCI/EHCI related devicetree parts
2017-04-05 12:50 [PATCH 0/3] Allwinner A64 EHCI0/OHCI0 devicetree change Icenowy Zheng
@ 2017-04-05 12:50 ` Icenowy Zheng
2017-04-05 13:05 ` Maxime Ripard
0 siblings, 1 reply; 11+ messages in thread
From: Icenowy Zheng @ 2017-04-05 12:50 UTC (permalink / raw)
To: Rob Herring, Maxime Ripard, Chen-Yu Tsai, Kishon Vijay Abraham I
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-sunxi, Icenowy Zheng
As we added USB0 route auto switching support for A64, add related
device tree parts to the A64 DTSI file (EHCI0/OHCI0 controllers and the
pmu0 memory area for PHY).
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 1c64ea2d23f9..a8916df99048 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -179,8 +179,10 @@
usbphy: phy@01c19400 {
compatible = "allwinner,sun50i-a64-usb-phy";
reg = <0x01c19400 0x14>,
+ <0x01c1a800 0x4>,
<0x01c1b800 0x4>;
reg-names = "phy_ctrl",
+ "pmu0",
"pmu1";
clocks = <&ccu CLK_USB_PHY0>,
<&ccu CLK_USB_PHY1>;
@@ -194,6 +196,28 @@
#phy-cells = <1>;
};
+ ehci0: usb@01c1a000 {
+ compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
+ reg = <0x01c1a000 0x100>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI0>,
+ <&ccu CLK_BUS_EHCI0>,
+ <&ccu CLK_USB_OHCI0>;
+ resets = <&ccu RST_BUS_OHCI0>,
+ <&ccu RST_BUS_EHCI0>;
+ status = "disabled";
+ };
+
+ ohci0: usb@01c1a400 {
+ compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
+ reg = <0x01c1a400 0x100>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI0>,
+ <&ccu CLK_USB_OHCI0>;
+ resets = <&ccu RST_BUS_OHCI0>;
+ status = "disabled";
+ };
+
ehci1: usb@01c1b000 {
compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
reg = <0x01c1b000 0x100>;
--
2.12.2
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH 2/3] arm64: allwinner: a64: add USB0 OHCI/EHCI related devicetree parts
2017-04-05 12:50 ` [PATCH 2/3] arm64: allwinner: a64: add USB0 OHCI/EHCI related devicetree parts Icenowy Zheng
@ 2017-04-05 13:05 ` Maxime Ripard
0 siblings, 0 replies; 11+ messages in thread
From: Maxime Ripard @ 2017-04-05 13:05 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Rob Herring, Chen-Yu Tsai, Kishon Vijay Abraham I, devicetree,
linux-arm-kernel, linux-kernel, linux-sunxi
[-- Attachment #1: Type: text/plain, Size: 1107 bytes --]
On Wed, Apr 05, 2017 at 08:50:52PM +0800, Icenowy Zheng wrote:
> As we added USB0 route auto switching support for A64, add related
> device tree parts to the A64 DTSI file (EHCI0/OHCI0 controllers and the
> pmu0 memory area for PHY).
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
> arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 24 ++++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> index 1c64ea2d23f9..a8916df99048 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> @@ -179,8 +179,10 @@
> usbphy: phy@01c19400 {
> compatible = "allwinner,sun50i-a64-usb-phy";
> reg = <0x01c19400 0x14>,
> + <0x01c1a800 0x4>,
> <0x01c1b800 0x4>;
> reg-names = "phy_ctrl",
> + "pmu0",
Again, this needs to be split apart, and sent for 4.11.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2017-04-05 13:05 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-04-04 18:45 [PATCH 1/3] phy: sun4i-usb: enable PHY0 dual route switching for A64 USB PHY Icenowy Zheng
2017-04-04 18:45 ` [PATCH 2/3] arm64: allwinner: a64: add USB0 OHCI/EHCI related devicetree parts Icenowy Zheng
2017-04-05 7:15 ` Maxime Ripard
[not found] ` <7828ffa0-f570-9841-a9e6-fe175f8169ac@aosc.io>
2017-04-05 7:26 ` Maxime Ripard
2017-04-05 7:33 ` Icenowy Zheng
2017-04-05 8:13 ` Maxime Ripard
2017-04-04 18:45 ` [PATCH 3/3] arm64: allwinner: a64: enable EHCI0/OHCI0 controller for Pine64 Icenowy Zheng
2017-04-05 7:03 ` [PATCH 1/3] phy: sun4i-usb: enable PHY0 dual route switching for A64 USB PHY Maxime Ripard
2017-04-05 9:59 ` Kishon Vijay Abraham I
2017-04-05 12:50 [PATCH 0/3] Allwinner A64 EHCI0/OHCI0 devicetree change Icenowy Zheng
2017-04-05 12:50 ` [PATCH 2/3] arm64: allwinner: a64: add USB0 OHCI/EHCI related devicetree parts Icenowy Zheng
2017-04-05 13:05 ` Maxime Ripard
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