* [PATCH v5 00/32] x86: Secure Memory Encryption (AMD) @ 2017-04-18 21:14 Tom Lendacky 2017-04-18 21:14 ` [PATCH v5 01/32] x86: Documentation for AMD Secure Memory Encryption (SME) Tom Lendacky ` (5 more replies) 0 siblings, 6 replies; 12+ messages in thread From: Tom Lendacky @ 2017-04-18 21:14 UTC (permalink / raw) To: linux-arch, linux-efi, kvm, linux-doc, x86, kexec, linux-kernel, kasan-dev, linux-mm, iommu Cc: Rik van Riel, Radim Krčmář, Toshimitsu Kani, Arnd Bergmann, Jonathan Corbet, Matt Fleming, Michael S. Tsirkin, Joerg Roedel, Konrad Rzeszutek Wilk, Paolo Bonzini, Larry Woodman, Brijesh Singh, Ingo Molnar, Borislav Petkov, Andy Lutomirski, H. Peter Anvin, Andrey Ryabinin, Alexander Potapenko, Dave Young, Thomas Gleixner, Dmitry Vyukov This patch series provides support for AMD's new Secure Memory Encryption (SME) feature. SME can be used to mark individual pages of memory as encrypted through the page tables. A page of memory that is marked encrypted will be automatically decrypted when read from DRAM and will be automatically encrypted when written to DRAM. Details on SME can found in the links below. The SME feature is identified through a CPUID function and enabled through the SYSCFG MSR. Once enabled, page table entries will determine how the memory is accessed. If a page table entry has the memory encryption mask set, then that memory will be accessed as encrypted memory. The memory encryption mask (as well as other related information) is determined from settings returned through the same CPUID function that identifies the presence of the feature. The approach that this patch series takes is to encrypt everything possible starting early in the boot where the kernel is encrypted. Using the page table macros the encryption mask can be incorporated into all page table entries and page allocations. By updating the protection map, userspace allocations are also marked encrypted. Certain data must be accounted for as having been placed in memory before SME was enabled (EFI, initrd, etc.) and accessed accordingly. This patch series is a pre-cursor to another AMD processor feature called Secure Encrypted Virtualization (SEV). The support for SEV will build upon the SME support and will be submitted later. Details on SEV can be found in the links below. The following links provide additional detail: AMD Memory Encryption whitepaper: http://amd-dev.wpengine.netdna-cdn.com/wordpress/media/2013/12/AMD_Memory_Encryption_Whitepaper_v7-Public.pdf AMD64 Architecture Programmer's Manual: http://support.amd.com/TechDocs/24593.pdf SME is section 7.10 SEV is section 15.34 This patch series is based off of the master branch of tip. Commit d36d99770e40 ("Merge branch 'timers/core'") --- Still to do: - IOMMU enablement support - Investigate using memremap() instead of ioremap_cache() for kdump Changes since v4: - Re-worked mapping of setup data to not use a fixed list. Rather, check dynamically whether the requested early_memremap()/memremap() call needs to be mapped decrypted. - Moved SME cpu feature into scattered features - Moved some declarations into header files - Cleared the encryption mask from the __PHYSICAL_MASK so that users of macros such as pmd_pfn_mask() don't have to worry/know about the encryption mask - Updated some return types and values related to EFI and e820 functions so that an error could be returned - During cpu shutdown, removed cache disabling and added a check for kexec in progress to use wbinvd followed immediately by halt in order to avoid any memory corruption - Update how persistent memory is identified - Added a function to find command line arguments and their values - Added sysfs support - General code cleanup based on feedback - General cleanup of patch subjects and descriptions Changes since v3: - Broke out some of the patches into smaller individual patches - Updated Documentation - Added a message to indicate why the IOMMU was disabled - Updated CPU feature support for SME by taking into account whether BIOS has enabled SME - Eliminated redundant functions - Added some warning messages for DMA usage of bounce buffers when SME is active - Added support for persistent memory - Added support to determine when setup data is being mapped and be sure to map it un-encrypted - Added CONFIG support to set the default action of whether to activate SME if it is supported/enabled - Added support for (re)booting with kexec Changes since v2: - Updated Documentation - Make the encryption mask available outside of arch/x86 through a standard include file - Conversion of assembler routines to C where possible (not everything could be converted, e.g. the routine that does the actual encryption needs to be copied into a safe location and it is difficult to determine the actual length of the function in order to copy it) - Fix SME feature use of scattered CPUID feature - Creation of SME specific functions for things like encrypting the setup data, ramdisk, etc. - New take on early_memremap / memremap encryption support - Additional support for accessing video buffers (fbdev/gpu) as un-encrypted - Disable IOMMU for now - need to investigate further in relation to how it needs to be programmed relative to accessing physical memory Changes since v1: - Added Documentation. - Removed AMD vendor check for setting the PAT write protect mode - Updated naming of trampoline flag for SME as well as moving of the SME check to before paging is enabled. - Change to early_memremap to identify the data being mapped as either boot data or kernel data. The idea being that boot data will have been placed in memory as un-encrypted data and would need to be accessed as such. - Updated debugfs support for the bootparams to access the data properly. - Do not set the SYSCFG[MEME] bit, only check it. The setting of the MemEncryptionModeEn bit results in a reduction of physical address size of the processor. It is possible that BIOS could have configured resources resources into a range that will now not be addressable. To prevent this, rely on BIOS to set the SYSCFG[MEME] bit and only then enable memory encryption support in the kernel. Tom Lendacky (32): x86: Documentation for AMD Secure Memory Encryption (SME) x86/mm/pat: Set write-protect cache mode for full PAT support x86, mpparse, x86/acpi, x86/PCI, SFI: Use memremap for RAM mappings x86/CPU/AMD: Add the Secure Memory Encryption CPU feature x86/CPU/AMD: Handle SME reduction in physical address size x86/mm: Add Secure Memory Encryption (SME) support x86/mm: Add support to enable SME in early boot processing x86/mm: Simplify p[g4um]d_page() macros x86/mm: Provide general kernel support for memory encryption x86/mm: Extend early_memremap() support with additional attrs x86/mm: Add support for early encrypt/decrypt of memory x86/mm: Insure that boot memory areas are mapped properly x86/boot/e820: Add support to determine the E820 type of an address efi: Add an EFI table address match function efi: Update efi_mem_type() to return an error rather than 0 x86/efi: Update EFI pagetable creation to work with SME x86/mm: Add support to access boot related data in the clear x86, mpparse: Use memremap to map the mpf and mpc data x86/mm: Add support to access persistent memory in the clear x86/mm: Add support for changing the memory encryption attribute x86, realmode: Decrypt trampoline area if memory encryption is active x86, swiotlb: DMA support for memory encryption swiotlb: Add warnings for use of bounce buffers with SME iommu/amd: Disable AMD IOMMU if memory encryption is active x86, realmode: Check for memory encryption on the APs x86, drm, fbdev: Do not specify encrypted memory for video mappings kvm: x86: svm: Enable Secure Memory Encryption within KVM x86/mm, kexec: Allow kexec to be used with SME x86/mm: Add support to encrypt the kernel in-place x86/boot: Add early cmdline parsing for options with arguments x86: Add sysfs support for Secure Memory Encryption x86/mm: Add support to make use of Secure Memory Encryption Documentation/admin-guide/kernel-parameters.txt | 11 Documentation/x86/amd-memory-encryption.txt | 60 ++ arch/ia64/kernel/efi.c | 4 arch/x86/Kconfig | 26 + arch/x86/boot/compressed/pagetable.c | 7 arch/x86/include/asm/cacheflush.h | 3 arch/x86/include/asm/cmdline.h | 2 arch/x86/include/asm/cpufeatures.h | 1 arch/x86/include/asm/dma-mapping.h | 5 arch/x86/include/asm/e820/api.h | 2 arch/x86/include/asm/fixmap.h | 20 + arch/x86/include/asm/init.h | 1 arch/x86/include/asm/io.h | 4 arch/x86/include/asm/irqflags.h | 5 arch/x86/include/asm/kexec.h | 8 arch/x86/include/asm/kvm_host.h | 2 arch/x86/include/asm/mem_encrypt.h | 115 ++++ arch/x86/include/asm/msr-index.h | 2 arch/x86/include/asm/page.h | 4 arch/x86/include/asm/page_types.h | 2 arch/x86/include/asm/pgtable.h | 28 + arch/x86/include/asm/pgtable_types.h | 54 +- arch/x86/include/asm/processor.h | 3 arch/x86/include/asm/realmode.h | 12 arch/x86/include/asm/vga.h | 13 arch/x86/kernel/acpi/boot.c | 6 arch/x86/kernel/cpu/amd.c | 23 + arch/x86/kernel/cpu/scattered.c | 1 arch/x86/kernel/e820.c | 26 + arch/x86/kernel/espfix_64.c | 2 arch/x86/kernel/head64.c | 42 +- arch/x86/kernel/head_64.S | 80 +++ arch/x86/kernel/kdebugfs.c | 34 - arch/x86/kernel/ksysfs.c | 28 + arch/x86/kernel/machine_kexec_64.c | 35 + arch/x86/kernel/mpparse.c | 106 +++- arch/x86/kernel/pci-dma.c | 11 arch/x86/kernel/pci-nommu.c | 2 arch/x86/kernel/pci-swiotlb.c | 8 arch/x86/kernel/process.c | 26 + arch/x86/kernel/setup.c | 10 arch/x86/kvm/mmu.c | 12 arch/x86/kvm/mmu.h | 2 arch/x86/kvm/svm.c | 35 + arch/x86/kvm/vmx.c | 3 arch/x86/kvm/x86.c | 3 arch/x86/lib/cmdline.c | 105 ++++ arch/x86/mm/Makefile | 3 arch/x86/mm/ident_map.c | 11 arch/x86/mm/ioremap.c | 255 +++++++++ arch/x86/mm/kasan_init_64.c | 4 arch/x86/mm/mem_encrypt.c | 626 +++++++++++++++++++++++ arch/x86/mm/mem_encrypt_boot.S | 151 ++++++ arch/x86/mm/pageattr.c | 67 ++ arch/x86/mm/pat.c | 6 arch/x86/pci/common.c | 4 arch/x86/platform/efi/efi.c | 6 arch/x86/platform/efi/efi_64.c | 15 - arch/x86/realmode/init.c | 16 + arch/x86/realmode/rm/trampoline_64.S | 24 + drivers/firmware/efi/efi.c | 33 + drivers/gpu/drm/drm_gem.c | 2 drivers/gpu/drm/drm_vm.c | 4 drivers/gpu/drm/ttm/ttm_bo_vm.c | 7 drivers/gpu/drm/udl/udl_fb.c | 4 drivers/iommu/amd_iommu_init.c | 7 drivers/sfi/sfi_core.c | 22 - drivers/video/fbdev/core/fbmem.c | 12 include/asm-generic/early_ioremap.h | 2 include/asm-generic/pgtable.h | 8 include/linux/dma-mapping.h | 11 include/linux/efi.h | 9 include/linux/io.h | 2 include/linux/kexec.h | 14 + include/linux/mem_encrypt.h | 53 ++ include/linux/swiotlb.h | 1 init/main.c | 13 kernel/kexec_core.c | 7 kernel/memremap.c | 20 + lib/swiotlb.c | 59 ++ mm/early_ioremap.c | 28 + 81 files changed, 2293 insertions(+), 207 deletions(-) create mode 100644 Documentation/x86/amd-memory-encryption.txt create mode 100644 arch/x86/include/asm/mem_encrypt.h create mode 100644 arch/x86/mm/mem_encrypt.c create mode 100644 arch/x86/mm/mem_encrypt_boot.S create mode 100644 include/linux/mem_encrypt.h -- Tom Lendacky ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v5 01/32] x86: Documentation for AMD Secure Memory Encryption (SME) 2017-04-18 21:14 [PATCH v5 00/32] x86: Secure Memory Encryption (AMD) Tom Lendacky @ 2017-04-18 21:14 ` Tom Lendacky 2017-04-18 21:14 ` [PATCH v5 02/32] x86/mm/pat: Set write-protect cache mode for full PAT support Tom Lendacky ` (4 subsequent siblings) 5 siblings, 0 replies; 12+ messages in thread From: Tom Lendacky @ 2017-04-18 21:14 UTC (permalink / raw) To: linux-arch, linux-efi, kvm, linux-doc, x86, kexec, linux-kernel, kasan-dev, linux-mm, iommu Cc: Rik van Riel, Radim Krčmář, Toshimitsu Kani, Arnd Bergmann, Jonathan Corbet, Matt Fleming, Michael S. Tsirkin, Joerg Roedel, Konrad Rzeszutek Wilk, Paolo Bonzini, Larry Woodman, Brijesh Singh, Ingo Molnar, Borislav Petkov, Andy Lutomirski, H. Peter Anvin, Andrey Ryabinin, Alexander Potapenko, Dave Young, Thomas Gleixner, Dmitry Vyukov Create a Documentation entry to describe the AMD Secure Memory Encryption (SME) feature and add documentation for the mem_encrypt= kernel parameter. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> --- Documentation/admin-guide/kernel-parameters.txt | 11 ++++ Documentation/x86/amd-memory-encryption.txt | 60 +++++++++++++++++++++++ 2 files changed, 71 insertions(+) create mode 100644 Documentation/x86/amd-memory-encryption.txt diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 3dd6d5d..84c5787 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -2165,6 +2165,17 @@ memory contents and reserves bad memory regions that are detected. + mem_encrypt= [X86-64] AMD Secure Memory Encryption (SME) control + Valid arguments: on, off + Default (depends on kernel configuration option): + on (CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT=y) + off (CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT=n) + mem_encrypt=on: Activate SME + mem_encrypt=off: Do not activate SME + + Refer to Documentation/x86/amd-memory-encryption.txt + for details on when memory encryption can be activated. + mem_sleep_default= [SUSPEND] Default system suspend mode: s2idle - Suspend-To-Idle shallow - Power-On Suspend or equivalent (if supported) diff --git a/Documentation/x86/amd-memory-encryption.txt b/Documentation/x86/amd-memory-encryption.txt new file mode 100644 index 0000000..0b72ff2 --- /dev/null +++ b/Documentation/x86/amd-memory-encryption.txt @@ -0,0 +1,60 @@ +Secure Memory Encryption (SME) is a feature found on AMD processors. + +SME provides the ability to mark individual pages of memory as encrypted using +the standard x86 page tables. A page that is marked encrypted will be +automatically decrypted when read from DRAM and encrypted when written to +DRAM. SME can therefore be used to protect the contents of DRAM from physical +attacks on the system. + +A page is encrypted when a page table entry has the encryption bit set (see +below on how to determine its position). The encryption bit can be specified +in the cr3 register, allowing the PGD table to be encrypted. Each successive +level of page tables can also be encrypted. + +Support for SME can be determined through the CPUID instruction. The CPUID +function 0x8000001f reports information related to SME: + + 0x8000001f[eax]: + Bit[0] indicates support for SME + 0x8000001f[ebx]: + Bits[5:0] pagetable bit number used to activate memory + encryption + Bits[11:6] reduction in physical address space, in bits, when + memory encryption is enabled (this only affects + system physical addresses, not guest physical + addresses) + +If support for SME is present, MSR 0xc00100010 (MSR_K8_SYSCFG) can be used to +determine if SME is enabled and/or to enable memory encryption: + + 0xc0010010: + Bit[23] 0 = memory encryption features are disabled + 1 = memory encryption features are enabled + +Linux relies on BIOS to set this bit if BIOS has determined that the reduction +in the physical address space as a result of enabling memory encryption (see +CPUID information above) will not conflict with the address space resource +requirements for the system. If this bit is not set upon Linux startup then +Linux itself will not set it and memory encryption will not be possible. + +The state of SME in the Linux kernel can be documented as follows: + - Supported: + The CPU supports SME (determined through CPUID instruction). + + - Enabled: + Supported and bit 23 of MSR_K8_SYSCFG is set. + + - Active: + Supported, Enabled and the Linux kernel is actively applying + the encryption bit to page table entries (the SME mask in the + kernel is non-zero). + +SME can also be enabled and activated in the BIOS. If SME is enabled and +activated in the BIOS, then all memory accesses will be encrypted and it will +not be necessary to activate the Linux memory encryption support. If the BIOS +merely enables SME (sets bit 23 of the MSR_K8_SYSCFG), then Linux can activate +memory encryption by default (CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT=y) or +by supplying mem_encrypt=on on the kernel command line. However, if BIOS does +not enable SME, then Linux will not be able to activate memory encryption, even +if configured to do so by default or the mem_encrypt=on command line parameter +is specified. ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v5 02/32] x86/mm/pat: Set write-protect cache mode for full PAT support 2017-04-18 21:14 [PATCH v5 00/32] x86: Secure Memory Encryption (AMD) Tom Lendacky 2017-04-18 21:14 ` [PATCH v5 01/32] x86: Documentation for AMD Secure Memory Encryption (SME) Tom Lendacky @ 2017-04-18 21:14 ` Tom Lendacky 2017-04-18 21:14 ` [PATCH v5 03/32] x86, mpparse, x86/acpi, x86/PCI, SFI: Use memremap for RAM mappings Tom Lendacky ` (3 subsequent siblings) 5 siblings, 0 replies; 12+ messages in thread From: Tom Lendacky @ 2017-04-18 21:14 UTC (permalink / raw) To: linux-arch, linux-efi, kvm, linux-doc, x86, kexec, linux-kernel, kasan-dev, linux-mm, iommu Cc: Rik van Riel, Radim Krčmář, Toshimitsu Kani, Arnd Bergmann, Jonathan Corbet, Matt Fleming, Michael S. Tsirkin, Joerg Roedel, Konrad Rzeszutek Wilk, Paolo Bonzini, Larry Woodman, Brijesh Singh, Ingo Molnar, Borislav Petkov, Andy Lutomirski, H. Peter Anvin, Andrey Ryabinin, Alexander Potapenko, Dave Young, Thomas Gleixner, Dmitry Vyukov For processors that support PAT, set the write-protect cache mode (_PAGE_CACHE_MODE_WP) entry to the actual write-protect value (x05). Acked-by: Borislav Petkov <bp@suse.de> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> --- arch/x86/mm/pat.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/x86/mm/pat.c b/arch/x86/mm/pat.c index 9b78685..6753d9c 100644 --- a/arch/x86/mm/pat.c +++ b/arch/x86/mm/pat.c @@ -295,7 +295,7 @@ static void init_cache_modes(void) * pat_init - Initialize PAT MSR and PAT table * * This function initializes PAT MSR and PAT table with an OS-defined value - * to enable additional cache attributes, WC and WT. + * to enable additional cache attributes, WC, WT and WP. * * This function must be called on all CPUs using the specific sequence of * operations defined in Intel SDM. mtrr_rendezvous_handler() provides this @@ -356,7 +356,7 @@ void pat_init(void) * 010 2 UC-: _PAGE_CACHE_MODE_UC_MINUS * 011 3 UC : _PAGE_CACHE_MODE_UC * 100 4 WB : Reserved - * 101 5 WC : Reserved + * 101 5 WP : _PAGE_CACHE_MODE_WP * 110 6 UC-: Reserved * 111 7 WT : _PAGE_CACHE_MODE_WT * @@ -364,7 +364,7 @@ void pat_init(void) * corresponding types in the presence of PAT errata. */ pat = PAT(0, WB) | PAT(1, WC) | PAT(2, UC_MINUS) | PAT(3, UC) | - PAT(4, WB) | PAT(5, WC) | PAT(6, UC_MINUS) | PAT(7, WT); + PAT(4, WB) | PAT(5, WP) | PAT(6, UC_MINUS) | PAT(7, WT); } if (!boot_cpu_done) { ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v5 03/32] x86, mpparse, x86/acpi, x86/PCI, SFI: Use memremap for RAM mappings 2017-04-18 21:14 [PATCH v5 00/32] x86: Secure Memory Encryption (AMD) Tom Lendacky 2017-04-18 21:14 ` [PATCH v5 01/32] x86: Documentation for AMD Secure Memory Encryption (SME) Tom Lendacky 2017-04-18 21:14 ` [PATCH v5 02/32] x86/mm/pat: Set write-protect cache mode for full PAT support Tom Lendacky @ 2017-04-18 21:14 ` Tom Lendacky 2017-04-18 21:14 ` [PATCH v5 04/32] x86/CPU/AMD: Add the Secure Memory Encryption CPU feature Tom Lendacky ` (2 subsequent siblings) 5 siblings, 0 replies; 12+ messages in thread From: Tom Lendacky @ 2017-04-18 21:14 UTC (permalink / raw) To: linux-arch, linux-efi, kvm, linux-doc, x86, kexec, linux-kernel, kasan-dev, linux-mm, iommu Cc: Rik van Riel, Radim Krčmář, Toshimitsu Kani, Arnd Bergmann, Jonathan Corbet, Matt Fleming, Michael S. Tsirkin, Joerg Roedel, Konrad Rzeszutek Wilk, Paolo Bonzini, Larry Woodman, Brijesh Singh, Ingo Molnar, Borislav Petkov, Andy Lutomirski, H. Peter Anvin, Andrey Ryabinin, Alexander Potapenko, Dave Young, Thomas Gleixner, Dmitry Vyukov The ioremap() function is intended for mapping MMIO. For RAM, the memremap() function can be used. Convert calls from ioremap() to memremap() when re-mapping RAM. This will be used later by SME to control how the encryption mask is applied to memory mappings, with certain memory locations being mapped decrypted vs encrypted. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> --- arch/x86/kernel/acpi/boot.c | 6 +++--- arch/x86/kernel/kdebugfs.c | 34 +++++++++++----------------------- arch/x86/kernel/ksysfs.c | 28 ++++++++++++++-------------- arch/x86/kernel/mpparse.c | 10 +++++----- arch/x86/pci/common.c | 4 ++-- drivers/sfi/sfi_core.c | 22 +++++++++++----------- 6 files changed, 46 insertions(+), 58 deletions(-) diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c index 6bb6806..850160a 100644 --- a/arch/x86/kernel/acpi/boot.c +++ b/arch/x86/kernel/acpi/boot.c @@ -115,7 +115,7 @@ #define ACPI_INVALID_GSI INT_MIN /* - * This is just a simple wrapper around early_ioremap(), + * This is just a simple wrapper around early_memremap(), * with sanity checks for phys == 0 and size == 0. */ char *__init __acpi_map_table(unsigned long phys, unsigned long size) @@ -124,7 +124,7 @@ char *__init __acpi_map_table(unsigned long phys, unsigned long size) if (!phys || !size) return NULL; - return early_ioremap(phys, size); + return early_memremap(phys, size); } void __init __acpi_unmap_table(char *map, unsigned long size) @@ -132,7 +132,7 @@ void __init __acpi_unmap_table(char *map, unsigned long size) if (!map || !size) return; - early_iounmap(map, size); + early_memunmap(map, size); } #ifdef CONFIG_X86_LOCAL_APIC diff --git a/arch/x86/kernel/kdebugfs.c b/arch/x86/kernel/kdebugfs.c index 38b6458..fd6f8fb 100644 --- a/arch/x86/kernel/kdebugfs.c +++ b/arch/x86/kernel/kdebugfs.c @@ -33,7 +33,6 @@ static ssize_t setup_data_read(struct file *file, char __user *user_buf, struct setup_data_node *node = file->private_data; unsigned long remain; loff_t pos = *ppos; - struct page *pg; void *p; u64 pa; @@ -47,18 +46,13 @@ static ssize_t setup_data_read(struct file *file, char __user *user_buf, count = node->len - pos; pa = node->paddr + sizeof(struct setup_data) + pos; - pg = pfn_to_page((pa + count - 1) >> PAGE_SHIFT); - if (PageHighMem(pg)) { - p = ioremap_cache(pa, count); - if (!p) - return -ENXIO; - } else - p = __va(pa); + p = memremap(pa, count, MEMREMAP_WB); + if (!p) + return -ENOMEM; remain = copy_to_user(user_buf, p, count); - if (PageHighMem(pg)) - iounmap(p); + memunmap(p); if (remain) return -EFAULT; @@ -109,7 +103,6 @@ static int __init create_setup_data_nodes(struct dentry *parent) struct setup_data *data; int error; struct dentry *d; - struct page *pg; u64 pa_data; int no = 0; @@ -126,16 +119,12 @@ static int __init create_setup_data_nodes(struct dentry *parent) goto err_dir; } - pg = pfn_to_page((pa_data+sizeof(*data)-1) >> PAGE_SHIFT); - if (PageHighMem(pg)) { - data = ioremap_cache(pa_data, sizeof(*data)); - if (!data) { - kfree(node); - error = -ENXIO; - goto err_dir; - } - } else - data = __va(pa_data); + data = memremap(pa_data, sizeof(*data), MEMREMAP_WB); + if (!data) { + kfree(node); + error = -ENOMEM; + goto err_dir; + } node->paddr = pa_data; node->type = data->type; @@ -143,8 +132,7 @@ static int __init create_setup_data_nodes(struct dentry *parent) error = create_setup_data_node(d, no, node); pa_data = data->next; - if (PageHighMem(pg)) - iounmap(data); + memunmap(data); if (error) goto err_dir; no++; diff --git a/arch/x86/kernel/ksysfs.c b/arch/x86/kernel/ksysfs.c index 4afc67f..ee51db9 100644 --- a/arch/x86/kernel/ksysfs.c +++ b/arch/x86/kernel/ksysfs.c @@ -16,8 +16,8 @@ #include <linux/stat.h> #include <linux/slab.h> #include <linux/mm.h> +#include <linux/io.h> -#include <asm/io.h> #include <asm/setup.h> static ssize_t version_show(struct kobject *kobj, @@ -79,12 +79,12 @@ static int get_setup_data_paddr(int nr, u64 *paddr) *paddr = pa_data; return 0; } - data = ioremap_cache(pa_data, sizeof(*data)); + data = memremap(pa_data, sizeof(*data), MEMREMAP_WB); if (!data) return -ENOMEM; pa_data = data->next; - iounmap(data); + memunmap(data); i++; } return -EINVAL; @@ -97,17 +97,17 @@ static int __init get_setup_data_size(int nr, size_t *size) u64 pa_data = boot_params.hdr.setup_data; while (pa_data) { - data = ioremap_cache(pa_data, sizeof(*data)); + data = memremap(pa_data, sizeof(*data), MEMREMAP_WB); if (!data) return -ENOMEM; if (nr == i) { *size = data->len; - iounmap(data); + memunmap(data); return 0; } pa_data = data->next; - iounmap(data); + memunmap(data); i++; } return -EINVAL; @@ -127,12 +127,12 @@ static ssize_t type_show(struct kobject *kobj, ret = get_setup_data_paddr(nr, &paddr); if (ret) return ret; - data = ioremap_cache(paddr, sizeof(*data)); + data = memremap(paddr, sizeof(*data), MEMREMAP_WB); if (!data) return -ENOMEM; ret = sprintf(buf, "0x%x\n", data->type); - iounmap(data); + memunmap(data); return ret; } @@ -154,7 +154,7 @@ static ssize_t setup_data_data_read(struct file *fp, ret = get_setup_data_paddr(nr, &paddr); if (ret) return ret; - data = ioremap_cache(paddr, sizeof(*data)); + data = memremap(paddr, sizeof(*data), MEMREMAP_WB); if (!data) return -ENOMEM; @@ -170,15 +170,15 @@ static ssize_t setup_data_data_read(struct file *fp, goto out; ret = count; - p = ioremap_cache(paddr + sizeof(*data), data->len); + p = memremap(paddr + sizeof(*data), data->len, MEMREMAP_WB); if (!p) { ret = -ENOMEM; goto out; } memcpy(buf, p + off, count); - iounmap(p); + memunmap(p); out: - iounmap(data); + memunmap(data); return ret; } @@ -250,13 +250,13 @@ static int __init get_setup_data_total_num(u64 pa_data, int *nr) *nr = 0; while (pa_data) { *nr += 1; - data = ioremap_cache(pa_data, sizeof(*data)); + data = memremap(pa_data, sizeof(*data), MEMREMAP_WB); if (!data) { ret = -ENOMEM; goto out; } pa_data = data->next; - iounmap(data); + memunmap(data); } out: diff --git a/arch/x86/kernel/mpparse.c b/arch/x86/kernel/mpparse.c index 0d904d7..fd37f39 100644 --- a/arch/x86/kernel/mpparse.c +++ b/arch/x86/kernel/mpparse.c @@ -436,9 +436,9 @@ static unsigned long __init get_mpc_size(unsigned long physptr) struct mpc_table *mpc; unsigned long size; - mpc = early_ioremap(physptr, PAGE_SIZE); + mpc = early_memremap(physptr, PAGE_SIZE); size = mpc->length; - early_iounmap(mpc, PAGE_SIZE); + early_memunmap(mpc, PAGE_SIZE); apic_printk(APIC_VERBOSE, " mpc: %lx-%lx\n", physptr, physptr + size); return size; @@ -450,7 +450,7 @@ static int __init check_physptr(struct mpf_intel *mpf, unsigned int early) unsigned long size; size = get_mpc_size(mpf->physptr); - mpc = early_ioremap(mpf->physptr, size); + mpc = early_memremap(mpf->physptr, size); /* * Read the physical hardware table. Anything here will * override the defaults. @@ -461,10 +461,10 @@ static int __init check_physptr(struct mpf_intel *mpf, unsigned int early) #endif pr_err("BIOS bug, MP table errors detected!...\n"); pr_cont("... disabling SMP support. (tell your hw vendor)\n"); - early_iounmap(mpc, size); + early_memunmap(mpc, size); return -1; } - early_iounmap(mpc, size); + early_memunmap(mpc, size); if (early) return -1; diff --git a/arch/x86/pci/common.c b/arch/x86/pci/common.c index 190e718..08cf71c 100644 --- a/arch/x86/pci/common.c +++ b/arch/x86/pci/common.c @@ -691,7 +691,7 @@ int pcibios_add_device(struct pci_dev *dev) pa_data = boot_params.hdr.setup_data; while (pa_data) { - data = ioremap(pa_data, sizeof(*rom)); + data = memremap(pa_data, sizeof(*rom), MEMREMAP_WB); if (!data) return -ENOMEM; @@ -710,7 +710,7 @@ int pcibios_add_device(struct pci_dev *dev) } } pa_data = data->next; - iounmap(data); + memunmap(data); } set_dma_domain_ops(dev); set_dev_domain_options(dev); diff --git a/drivers/sfi/sfi_core.c b/drivers/sfi/sfi_core.c index 296db7a..d5ce534 100644 --- a/drivers/sfi/sfi_core.c +++ b/drivers/sfi/sfi_core.c @@ -86,13 +86,13 @@ /* * FW creates and saves the SFI tables in memory. When these tables get * used, they may need to be mapped to virtual address space, and the mapping - * can happen before or after the ioremap() is ready, so a flag is needed + * can happen before or after the memremap() is ready, so a flag is needed * to indicating this */ -static u32 sfi_use_ioremap __read_mostly; +static u32 sfi_use_memremap __read_mostly; /* - * sfi_un/map_memory calls early_ioremap/iounmap which is a __init function + * sfi_un/map_memory calls early_memremap/memunmap which is a __init function * and introduces section mismatch. So use __ref to make it calm. */ static void __iomem * __ref sfi_map_memory(u64 phys, u32 size) @@ -100,10 +100,10 @@ static void __iomem * __ref sfi_map_memory(u64 phys, u32 size) if (!phys || !size) return NULL; - if (sfi_use_ioremap) - return ioremap_cache(phys, size); + if (sfi_use_memremap) + return memremap(phys, size, MEMREMAP_WB); else - return early_ioremap(phys, size); + return early_memremap(phys, size); } static void __ref sfi_unmap_memory(void __iomem *virt, u32 size) @@ -111,10 +111,10 @@ static void __ref sfi_unmap_memory(void __iomem *virt, u32 size) if (!virt || !size) return; - if (sfi_use_ioremap) - iounmap(virt); + if (sfi_use_memremap) + memunmap(virt); else - early_iounmap(virt, size); + early_memunmap(virt, size); } static void sfi_print_table_header(unsigned long long pa, @@ -507,8 +507,8 @@ void __init sfi_init_late(void) length = syst_va->header.len; sfi_unmap_memory(syst_va, sizeof(struct sfi_table_simple)); - /* Use ioremap now after it is ready */ - sfi_use_ioremap = 1; + /* Use memremap now after it is ready */ + sfi_use_memremap = 1; syst_va = sfi_map_memory(syst_pa, length); sfi_acpi_init(); ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v5 04/32] x86/CPU/AMD: Add the Secure Memory Encryption CPU feature 2017-04-18 21:14 [PATCH v5 00/32] x86: Secure Memory Encryption (AMD) Tom Lendacky ` (2 preceding siblings ...) 2017-04-18 21:14 ` [PATCH v5 03/32] x86, mpparse, x86/acpi, x86/PCI, SFI: Use memremap for RAM mappings Tom Lendacky @ 2017-04-18 21:14 ` Tom Lendacky 2017-04-18 21:14 ` [PATCH v5 05/32] x86/CPU/AMD: Handle SME reduction in physical address size Tom Lendacky 2017-04-18 21:15 ` [PATCH v5 06/32] x86/mm: Add Secure Memory Encryption (SME) support Tom Lendacky 5 siblings, 0 replies; 12+ messages in thread From: Tom Lendacky @ 2017-04-18 21:14 UTC (permalink / raw) To: linux-arch, linux-efi, kvm, linux-doc, x86, kexec, linux-kernel, kasan-dev, linux-mm, iommu Cc: Rik van Riel, Radim Krčmář, Toshimitsu Kani, Arnd Bergmann, Jonathan Corbet, Matt Fleming, Michael S. Tsirkin, Joerg Roedel, Konrad Rzeszutek Wilk, Paolo Bonzini, Larry Woodman, Brijesh Singh, Ingo Molnar, Borislav Petkov, Andy Lutomirski, H. Peter Anvin, Andrey Ryabinin, Alexander Potapenko, Dave Young, Thomas Gleixner, Dmitry Vyukov Update the CPU features to include identifying and reporting on the Secure Memory Encryption (SME) feature. SME is identified by CPUID 0x8000001f, but requires BIOS support to enable it (set bit 23 of MSR_K8_SYSCFG). Only show the SME feature as available if reported by CPUID and enabled by BIOS. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/msr-index.h | 2 ++ arch/x86/kernel/cpu/amd.c | 15 +++++++++++++++ arch/x86/kernel/cpu/scattered.c | 1 + 4 files changed, 19 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 2701e5f..2b692df 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -196,6 +196,7 @@ #define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */ #define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */ +#define X86_FEATURE_SME ( 7*32+10) /* AMD Secure Memory Encryption */ #define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */ #define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */ diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 673f9ac..8ff4aaa 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -350,6 +350,8 @@ #define MSR_K8_TOP_MEM1 0xc001001a #define MSR_K8_TOP_MEM2 0xc001001d #define MSR_K8_SYSCFG 0xc0010010 +#define MSR_K8_SYSCFG_MEM_ENCRYPT_BIT 23 +#define MSR_K8_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_K8_SYSCFG_MEM_ENCRYPT_BIT) #define MSR_K8_INT_PENDING_MSG 0xc0010055 /* C1E active bits in int pending message */ #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index c36140d..5fc5232 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -611,6 +611,21 @@ static void early_init_amd(struct cpuinfo_x86 *c) */ if (cpu_has_amd_erratum(c, amd_erratum_400)) set_cpu_bug(c, X86_BUG_AMD_E400); + + /* + * BIOS support is required for SME. If BIOS has not enabled SME + * then don't advertise the feature (set in scattered.c) + */ + if (c->extended_cpuid_level >= 0x8000001f) { + if (cpu_has(c, X86_FEATURE_SME)) { + u64 msr; + + /* Check if SME is enabled */ + rdmsrl(MSR_K8_SYSCFG, msr); + if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT)) + clear_cpu_cap(c, X86_FEATURE_SME); + } + } } static void init_amd_k8(struct cpuinfo_x86 *c) diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c index 23c2350..05459ad 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -31,6 +31,7 @@ struct cpuid_bit { { X86_FEATURE_HW_PSTATE, CPUID_EDX, 7, 0x80000007, 0 }, { X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 }, { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 }, + { X86_FEATURE_SME, CPUID_EAX, 0, 0x8000001f, 0 }, { 0, 0, 0, 0, 0 } }; ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v5 05/32] x86/CPU/AMD: Handle SME reduction in physical address size 2017-04-18 21:14 [PATCH v5 00/32] x86: Secure Memory Encryption (AMD) Tom Lendacky ` (3 preceding siblings ...) 2017-04-18 21:14 ` [PATCH v5 04/32] x86/CPU/AMD: Add the Secure Memory Encryption CPU feature Tom Lendacky @ 2017-04-18 21:14 ` Tom Lendacky 2017-04-18 21:15 ` [PATCH v5 06/32] x86/mm: Add Secure Memory Encryption (SME) support Tom Lendacky 5 siblings, 0 replies; 12+ messages in thread From: Tom Lendacky @ 2017-04-18 21:14 UTC (permalink / raw) To: linux-arch, linux-efi, kvm, linux-doc, x86, kexec, linux-kernel, kasan-dev, linux-mm, iommu Cc: Rik van Riel, Radim Krčmář, Toshimitsu Kani, Arnd Bergmann, Jonathan Corbet, Matt Fleming, Michael S. Tsirkin, Joerg Roedel, Konrad Rzeszutek Wilk, Paolo Bonzini, Larry Woodman, Brijesh Singh, Ingo Molnar, Borislav Petkov, Andy Lutomirski, H. Peter Anvin, Andrey Ryabinin, Alexander Potapenko, Dave Young, Thomas Gleixner, Dmitry Vyukov When System Memory Encryption (SME) is enabled, the physical address space is reduced. Adjust the x86_phys_bits value to reflect this reduction. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> --- arch/x86/kernel/cpu/amd.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 5fc5232..35eeeb1 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -613,8 +613,10 @@ static void early_init_amd(struct cpuinfo_x86 *c) set_cpu_bug(c, X86_BUG_AMD_E400); /* - * BIOS support is required for SME. If BIOS has not enabled SME - * then don't advertise the feature (set in scattered.c) + * BIOS support is required for SME. If BIOS has enabld SME then + * adjust x86_phys_bits by the SME physical address space reduction + * value. If BIOS has not enabled SME then don't advertise the + * feature (set in scattered.c). */ if (c->extended_cpuid_level >= 0x8000001f) { if (cpu_has(c, X86_FEATURE_SME)) { @@ -622,8 +624,14 @@ static void early_init_amd(struct cpuinfo_x86 *c) /* Check if SME is enabled */ rdmsrl(MSR_K8_SYSCFG, msr); - if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT)) + if (msr & MSR_K8_SYSCFG_MEM_ENCRYPT) { + unsigned int ebx; + + ebx = cpuid_ebx(0x8000001f); + c->x86_phys_bits -= (ebx >> 6) & 0x3f; + } else { clear_cpu_cap(c, X86_FEATURE_SME); + } } } } ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v5 06/32] x86/mm: Add Secure Memory Encryption (SME) support 2017-04-18 21:14 [PATCH v5 00/32] x86: Secure Memory Encryption (AMD) Tom Lendacky ` (4 preceding siblings ...) 2017-04-18 21:14 ` [PATCH v5 05/32] x86/CPU/AMD: Handle SME reduction in physical address size Tom Lendacky @ 2017-04-18 21:15 ` Tom Lendacky 5 siblings, 0 replies; 12+ messages in thread From: Tom Lendacky @ 2017-04-18 21:15 UTC (permalink / raw) To: linux-arch, linux-efi, kvm, linux-doc, x86, kexec, linux-kernel, kasan-dev, linux-mm, iommu Cc: Rik van Riel, Radim Krčmář, Toshimitsu Kani, Arnd Bergmann, Jonathan Corbet, Matt Fleming, Michael S. Tsirkin, Joerg Roedel, Konrad Rzeszutek Wilk, Paolo Bonzini, Larry Woodman, Brijesh Singh, Ingo Molnar, Borislav Petkov, Andy Lutomirski, H. Peter Anvin, Andrey Ryabinin, Alexander Potapenko, Dave Young, Thomas Gleixner, Dmitry Vyukov Add support for Secure Memory Encryption (SME). This initial support provides a Kconfig entry to build the SME support into the kernel and defines the memory encryption mask that will be used in subsequent patches to mark pages as encrypted. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> --- arch/x86/Kconfig | 22 +++++++++++++++++++ arch/x86/include/asm/mem_encrypt.h | 42 ++++++++++++++++++++++++++++++++++++ arch/x86/mm/Makefile | 1 + arch/x86/mm/mem_encrypt.c | 21 ++++++++++++++++++ include/linux/mem_encrypt.h | 37 ++++++++++++++++++++++++++++++++ 5 files changed, 123 insertions(+) create mode 100644 arch/x86/include/asm/mem_encrypt.h create mode 100644 arch/x86/mm/mem_encrypt.c create mode 100644 include/linux/mem_encrypt.h diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 4e153e9..cf0cbe8 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1407,6 +1407,28 @@ config X86_DIRECT_GBPAGES supports them), so don't confuse the user by printing that we have them enabled. +config AMD_MEM_ENCRYPT + bool "AMD Secure Memory Encryption (SME) support" + depends on X86_64 && CPU_SUP_AMD + ---help--- + Say yes to enable support for the encryption of system memory. + This requires an AMD processor that supports Secure Memory + Encryption (SME). + +config AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT + bool "Activate AMD Secure Memory Encryption (SME) by default" + default y + depends on AMD_MEM_ENCRYPT + ---help--- + Say yes to have system memory encrypted by default if running on + an AMD processor that supports Secure Memory Encryption (SME). + + If set to Y, then the encryption of system memory can be + deactivated with the mem_encrypt=off command line option. + + If set to N, then the encryption of system memory can be + activated with the mem_encrypt=on command line option. + # Common NUMA Features config NUMA bool "Numa Memory Allocation and Scheduler Support" diff --git a/arch/x86/include/asm/mem_encrypt.h b/arch/x86/include/asm/mem_encrypt.h new file mode 100644 index 0000000..d5c4a2b --- /dev/null +++ b/arch/x86/include/asm/mem_encrypt.h @@ -0,0 +1,42 @@ +/* + * AMD Memory Encryption Support + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Author: Tom Lendacky <thomas.lendacky@amd.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __X86_MEM_ENCRYPT_H__ +#define __X86_MEM_ENCRYPT_H__ + +#ifndef __ASSEMBLY__ + +#ifdef CONFIG_AMD_MEM_ENCRYPT + +extern unsigned long sme_me_mask; + +static inline bool sme_active(void) +{ + return !!sme_me_mask; +} + +#else /* !CONFIG_AMD_MEM_ENCRYPT */ + +#ifndef sme_me_mask +#define sme_me_mask 0UL + +static inline bool sme_active(void) +{ + return false; +} +#endif + +#endif /* CONFIG_AMD_MEM_ENCRYPT */ + +#endif /* __ASSEMBLY__ */ + +#endif /* __X86_MEM_ENCRYPT_H__ */ diff --git a/arch/x86/mm/Makefile b/arch/x86/mm/Makefile index 0fbdcb6..a94a7b6 100644 --- a/arch/x86/mm/Makefile +++ b/arch/x86/mm/Makefile @@ -39,3 +39,4 @@ obj-$(CONFIG_X86_INTEL_MPX) += mpx.o obj-$(CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS) += pkeys.o obj-$(CONFIG_RANDOMIZE_MEMORY) += kaslr.o +obj-$(CONFIG_AMD_MEM_ENCRYPT) += mem_encrypt.o diff --git a/arch/x86/mm/mem_encrypt.c b/arch/x86/mm/mem_encrypt.c new file mode 100644 index 0000000..b99d469 --- /dev/null +++ b/arch/x86/mm/mem_encrypt.c @@ -0,0 +1,21 @@ +/* + * AMD Memory Encryption Support + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Author: Tom Lendacky <thomas.lendacky@amd.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/linkage.h> + +/* + * Since SME related variables are set early in the boot process they must + * reside in the .data section so as not to be zeroed out when the .bss + * section is later cleared. + */ +unsigned long sme_me_mask __section(.data) = 0; +EXPORT_SYMBOL_GPL(sme_me_mask); diff --git a/include/linux/mem_encrypt.h b/include/linux/mem_encrypt.h new file mode 100644 index 0000000..14a7b9f --- /dev/null +++ b/include/linux/mem_encrypt.h @@ -0,0 +1,37 @@ +/* + * AMD Memory Encryption Support + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Author: Tom Lendacky <thomas.lendacky@amd.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __MEM_ENCRYPT_H__ +#define __MEM_ENCRYPT_H__ + +#ifndef __ASSEMBLY__ + +#ifdef CONFIG_AMD_MEM_ENCRYPT + +#include <asm/mem_encrypt.h> + +#else /* !CONFIG_AMD_MEM_ENCRYPT */ + +#ifndef sme_me_mask +#define sme_me_mask 0UL + +static inline bool sme_active(void) +{ + return false; +} +#endif + +#endif /* CONFIG_AMD_MEM_ENCRYPT */ + +#endif /* __ASSEMBLY__ */ + +#endif /* __MEM_ENCRYPT_H__ */ ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v5 00/32] x86: Secure Memory Encryption (AMD) @ 2017-04-18 21:16 Tom Lendacky 2017-04-18 21:16 ` [PATCH v5 01/32] x86: Documentation for AMD Secure Memory Encryption (SME) Tom Lendacky 0 siblings, 1 reply; 12+ messages in thread From: Tom Lendacky @ 2017-04-18 21:16 UTC (permalink / raw) To: linux-arch, linux-efi, kvm, linux-doc, x86, kexec, linux-kernel, kasan-dev, linux-mm, iommu Cc: Rik van Riel, Radim Krčmář, Toshimitsu Kani, Arnd Bergmann, Jonathan Corbet, Matt Fleming, Michael S. Tsirkin, Joerg Roedel, Konrad Rzeszutek Wilk, Paolo Bonzini, Larry Woodman, Brijesh Singh, Ingo Molnar, Borislav Petkov, Andy Lutomirski, H. Peter Anvin, Andrey Ryabinin, Alexander Potapenko, Dave Young, Thomas Gleixner, Dmitry Vyukov This patch series provides support for AMD's new Secure Memory Encryption (SME) feature. SME can be used to mark individual pages of memory as encrypted through the page tables. A page of memory that is marked encrypted will be automatically decrypted when read from DRAM and will be automatically encrypted when written to DRAM. Details on SME can found in the links below. The SME feature is identified through a CPUID function and enabled through the SYSCFG MSR. Once enabled, page table entries will determine how the memory is accessed. If a page table entry has the memory encryption mask set, then that memory will be accessed as encrypted memory. The memory encryption mask (as well as other related information) is determined from settings returned through the same CPUID function that identifies the presence of the feature. The approach that this patch series takes is to encrypt everything possible starting early in the boot where the kernel is encrypted. Using the page table macros the encryption mask can be incorporated into all page table entries and page allocations. By updating the protection map, userspace allocations are also marked encrypted. Certain data must be accounted for as having been placed in memory before SME was enabled (EFI, initrd, etc.) and accessed accordingly. This patch series is a pre-cursor to another AMD processor feature called Secure Encrypted Virtualization (SEV). The support for SEV will build upon the SME support and will be submitted later. Details on SEV can be found in the links below. The following links provide additional detail: AMD Memory Encryption whitepaper: http://amd-dev.wpengine.netdna-cdn.com/wordpress/media/2013/12/AMD_Memory_Encryption_Whitepaper_v7-Public.pdf AMD64 Architecture Programmer's Manual: http://support.amd.com/TechDocs/24593.pdf SME is section 7.10 SEV is section 15.34 This patch series is based off of the master branch of tip. Commit d36d99770e40 ("Merge branch 'timers/core'") --- Still to do: - IOMMU enablement support - Investigate using memremap() instead of ioremap_cache() for kdump Changes since v4: - Re-worked mapping of setup data to not use a fixed list. Rather, check dynamically whether the requested early_memremap()/memremap() call needs to be mapped decrypted. - Moved SME cpu feature into scattered features - Moved some declarations into header files - Cleared the encryption mask from the __PHYSICAL_MASK so that users of macros such as pmd_pfn_mask() don't have to worry/know about the encryption mask - Updated some return types and values related to EFI and e820 functions so that an error could be returned - During cpu shutdown, removed cache disabling and added a check for kexec in progress to use wbinvd followed immediately by halt in order to avoid any memory corruption - Update how persistent memory is identified - Added a function to find command line arguments and their values - Added sysfs support - General code cleanup based on feedback - General cleanup of patch subjects and descriptions Changes since v3: - Broke out some of the patches into smaller individual patches - Updated Documentation - Added a message to indicate why the IOMMU was disabled - Updated CPU feature support for SME by taking into account whether BIOS has enabled SME - Eliminated redundant functions - Added some warning messages for DMA usage of bounce buffers when SME is active - Added support for persistent memory - Added support to determine when setup data is being mapped and be sure to map it un-encrypted - Added CONFIG support to set the default action of whether to activate SME if it is supported/enabled - Added support for (re)booting with kexec Changes since v2: - Updated Documentation - Make the encryption mask available outside of arch/x86 through a standard include file - Conversion of assembler routines to C where possible (not everything could be converted, e.g. the routine that does the actual encryption needs to be copied into a safe location and it is difficult to determine the actual length of the function in order to copy it) - Fix SME feature use of scattered CPUID feature - Creation of SME specific functions for things like encrypting the setup data, ramdisk, etc. - New take on early_memremap / memremap encryption support - Additional support for accessing video buffers (fbdev/gpu) as un-encrypted - Disable IOMMU for now - need to investigate further in relation to how it needs to be programmed relative to accessing physical memory Changes since v1: - Added Documentation. - Removed AMD vendor check for setting the PAT write protect mode - Updated naming of trampoline flag for SME as well as moving of the SME check to before paging is enabled. - Change to early_memremap to identify the data being mapped as either boot data or kernel data. The idea being that boot data will have been placed in memory as un-encrypted data and would need to be accessed as such. - Updated debugfs support for the bootparams to access the data properly. - Do not set the SYSCFG[MEME] bit, only check it. The setting of the MemEncryptionModeEn bit results in a reduction of physical address size of the processor. It is possible that BIOS could have configured resources resources into a range that will now not be addressable. To prevent this, rely on BIOS to set the SYSCFG[MEME] bit and only then enable memory encryption support in the kernel. Tom Lendacky (32): x86: Documentation for AMD Secure Memory Encryption (SME) x86/mm/pat: Set write-protect cache mode for full PAT support x86, mpparse, x86/acpi, x86/PCI, SFI: Use memremap for RAM mappings x86/CPU/AMD: Add the Secure Memory Encryption CPU feature x86/CPU/AMD: Handle SME reduction in physical address size x86/mm: Add Secure Memory Encryption (SME) support x86/mm: Add support to enable SME in early boot processing x86/mm: Simplify p[g4um]d_page() macros x86/mm: Provide general kernel support for memory encryption x86/mm: Extend early_memremap() support with additional attrs x86/mm: Add support for early encrypt/decrypt of memory x86/mm: Insure that boot memory areas are mapped properly x86/boot/e820: Add support to determine the E820 type of an address efi: Add an EFI table address match function efi: Update efi_mem_type() to return an error rather than 0 x86/efi: Update EFI pagetable creation to work with SME x86/mm: Add support to access boot related data in the clear x86, mpparse: Use memremap to map the mpf and mpc data x86/mm: Add support to access persistent memory in the clear x86/mm: Add support for changing the memory encryption attribute x86, realmode: Decrypt trampoline area if memory encryption is active x86, swiotlb: DMA support for memory encryption swiotlb: Add warnings for use of bounce buffers with SME iommu/amd: Disable AMD IOMMU if memory encryption is active x86, realmode: Check for memory encryption on the APs x86, drm, fbdev: Do not specify encrypted memory for video mappings kvm: x86: svm: Enable Secure Memory Encryption within KVM x86/mm, kexec: Allow kexec to be used with SME x86/mm: Add support to encrypt the kernel in-place x86/boot: Add early cmdline parsing for options with arguments x86: Add sysfs support for Secure Memory Encryption x86/mm: Add support to make use of Secure Memory Encryption Documentation/admin-guide/kernel-parameters.txt | 11 Documentation/x86/amd-memory-encryption.txt | 60 ++ arch/ia64/kernel/efi.c | 4 arch/x86/Kconfig | 26 + arch/x86/boot/compressed/pagetable.c | 7 arch/x86/include/asm/cacheflush.h | 3 arch/x86/include/asm/cmdline.h | 2 arch/x86/include/asm/cpufeatures.h | 1 arch/x86/include/asm/dma-mapping.h | 5 arch/x86/include/asm/e820/api.h | 2 arch/x86/include/asm/fixmap.h | 20 + arch/x86/include/asm/init.h | 1 arch/x86/include/asm/io.h | 4 arch/x86/include/asm/irqflags.h | 5 arch/x86/include/asm/kexec.h | 8 arch/x86/include/asm/kvm_host.h | 2 arch/x86/include/asm/mem_encrypt.h | 115 ++++ arch/x86/include/asm/msr-index.h | 2 arch/x86/include/asm/page.h | 4 arch/x86/include/asm/page_types.h | 2 arch/x86/include/asm/pgtable.h | 28 + arch/x86/include/asm/pgtable_types.h | 54 +- arch/x86/include/asm/processor.h | 3 arch/x86/include/asm/realmode.h | 12 arch/x86/include/asm/vga.h | 13 arch/x86/kernel/acpi/boot.c | 6 arch/x86/kernel/cpu/amd.c | 23 + arch/x86/kernel/cpu/scattered.c | 1 arch/x86/kernel/e820.c | 26 + arch/x86/kernel/espfix_64.c | 2 arch/x86/kernel/head64.c | 42 +- arch/x86/kernel/head_64.S | 80 +++ arch/x86/kernel/kdebugfs.c | 34 - arch/x86/kernel/ksysfs.c | 28 + arch/x86/kernel/machine_kexec_64.c | 35 + arch/x86/kernel/mpparse.c | 106 +++- arch/x86/kernel/pci-dma.c | 11 arch/x86/kernel/pci-nommu.c | 2 arch/x86/kernel/pci-swiotlb.c | 8 arch/x86/kernel/process.c | 26 + arch/x86/kernel/setup.c | 10 arch/x86/kvm/mmu.c | 12 arch/x86/kvm/mmu.h | 2 arch/x86/kvm/svm.c | 35 + arch/x86/kvm/vmx.c | 3 arch/x86/kvm/x86.c | 3 arch/x86/lib/cmdline.c | 105 ++++ arch/x86/mm/Makefile | 3 arch/x86/mm/ident_map.c | 11 arch/x86/mm/ioremap.c | 255 +++++++++ arch/x86/mm/kasan_init_64.c | 4 arch/x86/mm/mem_encrypt.c | 626 +++++++++++++++++++++++ arch/x86/mm/mem_encrypt_boot.S | 151 ++++++ arch/x86/mm/pageattr.c | 67 ++ arch/x86/mm/pat.c | 6 arch/x86/pci/common.c | 4 arch/x86/platform/efi/efi.c | 6 arch/x86/platform/efi/efi_64.c | 15 - arch/x86/realmode/init.c | 16 + arch/x86/realmode/rm/trampoline_64.S | 24 + drivers/firmware/efi/efi.c | 33 + drivers/gpu/drm/drm_gem.c | 2 drivers/gpu/drm/drm_vm.c | 4 drivers/gpu/drm/ttm/ttm_bo_vm.c | 7 drivers/gpu/drm/udl/udl_fb.c | 4 drivers/iommu/amd_iommu_init.c | 7 drivers/sfi/sfi_core.c | 22 - drivers/video/fbdev/core/fbmem.c | 12 include/asm-generic/early_ioremap.h | 2 include/asm-generic/pgtable.h | 8 include/linux/dma-mapping.h | 11 include/linux/efi.h | 9 include/linux/io.h | 2 include/linux/kexec.h | 14 + include/linux/mem_encrypt.h | 53 ++ include/linux/swiotlb.h | 1 init/main.c | 13 kernel/kexec_core.c | 7 kernel/memremap.c | 20 + lib/swiotlb.c | 59 ++ mm/early_ioremap.c | 28 + 81 files changed, 2293 insertions(+), 207 deletions(-) create mode 100644 Documentation/x86/amd-memory-encryption.txt create mode 100644 arch/x86/include/asm/mem_encrypt.h create mode 100644 arch/x86/mm/mem_encrypt.c create mode 100644 arch/x86/mm/mem_encrypt_boot.S create mode 100644 include/linux/mem_encrypt.h -- Tom Lendacky ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v5 01/32] x86: Documentation for AMD Secure Memory Encryption (SME) 2017-04-18 21:16 [PATCH v5 00/32] x86: Secure Memory Encryption (AMD) Tom Lendacky @ 2017-04-18 21:16 ` Tom Lendacky 2017-04-19 9:02 ` Borislav Petkov 2017-04-19 9:52 ` David Howells 0 siblings, 2 replies; 12+ messages in thread From: Tom Lendacky @ 2017-04-18 21:16 UTC (permalink / raw) To: linux-arch, linux-efi, kvm, linux-doc, x86, kexec, linux-kernel, kasan-dev, linux-mm, iommu Cc: Rik van Riel, Radim Krčmář, Toshimitsu Kani, Arnd Bergmann, Jonathan Corbet, Matt Fleming, Michael S. Tsirkin, Joerg Roedel, Konrad Rzeszutek Wilk, Paolo Bonzini, Larry Woodman, Brijesh Singh, Ingo Molnar, Borislav Petkov, Andy Lutomirski, H. Peter Anvin, Andrey Ryabinin, Alexander Potapenko, Dave Young, Thomas Gleixner, Dmitry Vyukov Create a Documentation entry to describe the AMD Secure Memory Encryption (SME) feature and add documentation for the mem_encrypt= kernel parameter. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> --- Documentation/admin-guide/kernel-parameters.txt | 11 ++++ Documentation/x86/amd-memory-encryption.txt | 60 +++++++++++++++++++++++ 2 files changed, 71 insertions(+) create mode 100644 Documentation/x86/amd-memory-encryption.txt diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 3dd6d5d..84c5787 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -2165,6 +2165,17 @@ memory contents and reserves bad memory regions that are detected. + mem_encrypt= [X86-64] AMD Secure Memory Encryption (SME) control + Valid arguments: on, off + Default (depends on kernel configuration option): + on (CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT=y) + off (CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT=n) + mem_encrypt=on: Activate SME + mem_encrypt=off: Do not activate SME + + Refer to Documentation/x86/amd-memory-encryption.txt + for details on when memory encryption can be activated. + mem_sleep_default= [SUSPEND] Default system suspend mode: s2idle - Suspend-To-Idle shallow - Power-On Suspend or equivalent (if supported) diff --git a/Documentation/x86/amd-memory-encryption.txt b/Documentation/x86/amd-memory-encryption.txt new file mode 100644 index 0000000..0b72ff2 --- /dev/null +++ b/Documentation/x86/amd-memory-encryption.txt @@ -0,0 +1,60 @@ +Secure Memory Encryption (SME) is a feature found on AMD processors. + +SME provides the ability to mark individual pages of memory as encrypted using +the standard x86 page tables. A page that is marked encrypted will be +automatically decrypted when read from DRAM and encrypted when written to +DRAM. SME can therefore be used to protect the contents of DRAM from physical +attacks on the system. + +A page is encrypted when a page table entry has the encryption bit set (see +below on how to determine its position). The encryption bit can be specified +in the cr3 register, allowing the PGD table to be encrypted. Each successive +level of page tables can also be encrypted. + +Support for SME can be determined through the CPUID instruction. The CPUID +function 0x8000001f reports information related to SME: + + 0x8000001f[eax]: + Bit[0] indicates support for SME + 0x8000001f[ebx]: + Bits[5:0] pagetable bit number used to activate memory + encryption + Bits[11:6] reduction in physical address space, in bits, when + memory encryption is enabled (this only affects + system physical addresses, not guest physical + addresses) + +If support for SME is present, MSR 0xc00100010 (MSR_K8_SYSCFG) can be used to +determine if SME is enabled and/or to enable memory encryption: + + 0xc0010010: + Bit[23] 0 = memory encryption features are disabled + 1 = memory encryption features are enabled + +Linux relies on BIOS to set this bit if BIOS has determined that the reduction +in the physical address space as a result of enabling memory encryption (see +CPUID information above) will not conflict with the address space resource +requirements for the system. If this bit is not set upon Linux startup then +Linux itself will not set it and memory encryption will not be possible. + +The state of SME in the Linux kernel can be documented as follows: + - Supported: + The CPU supports SME (determined through CPUID instruction). + + - Enabled: + Supported and bit 23 of MSR_K8_SYSCFG is set. + + - Active: + Supported, Enabled and the Linux kernel is actively applying + the encryption bit to page table entries (the SME mask in the + kernel is non-zero). + +SME can also be enabled and activated in the BIOS. If SME is enabled and +activated in the BIOS, then all memory accesses will be encrypted and it will +not be necessary to activate the Linux memory encryption support. If the BIOS +merely enables SME (sets bit 23 of the MSR_K8_SYSCFG), then Linux can activate +memory encryption by default (CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT=y) or +by supplying mem_encrypt=on on the kernel command line. However, if BIOS does +not enable SME, then Linux will not be able to activate memory encryption, even +if configured to do so by default or the mem_encrypt=on command line parameter +is specified. ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v5 01/32] x86: Documentation for AMD Secure Memory Encryption (SME) 2017-04-18 21:16 ` [PATCH v5 01/32] x86: Documentation for AMD Secure Memory Encryption (SME) Tom Lendacky @ 2017-04-19 9:02 ` Borislav Petkov 2017-04-19 14:23 ` Tom Lendacky 2017-04-19 9:52 ` David Howells 1 sibling, 1 reply; 12+ messages in thread From: Borislav Petkov @ 2017-04-19 9:02 UTC (permalink / raw) To: Tom Lendacky Cc: linux-arch, linux-efi, kvm, linux-doc, x86, kexec, linux-kernel, kasan-dev, linux-mm, iommu, Rik van Riel, Radim Krčmář, Toshimitsu Kani, Arnd Bergmann, Jonathan Corbet, Matt Fleming, Michael S. Tsirkin, Joerg Roedel, Konrad Rzeszutek Wilk, Paolo Bonzini, Larry Woodman, Brijesh Singh, Ingo Molnar, Andy Lutomirski, H. Peter Anvin, Andrey Ryabinin, Alexander Potapenko, Dave Young, Thomas Gleixner, Dmitry Vyukov Always have a verb in the Subject to form a "do this" or "do that" sentence to better explain what the patch does: "Subject: [PATCH v5 01/32] x86: Add documentation for AMD Secure Memory Encryption (SME)" On Tue, Apr 18, 2017 at 04:16:25PM -0500, Tom Lendacky wrote: > Create a Documentation entry to describe the AMD Secure Memory > Encryption (SME) feature and add documentation for the mem_encrypt= > kernel parameter. > > Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> > --- > Documentation/admin-guide/kernel-parameters.txt | 11 ++++ > Documentation/x86/amd-memory-encryption.txt | 60 +++++++++++++++++++++++ > 2 files changed, 71 insertions(+) > create mode 100644 Documentation/x86/amd-memory-encryption.txt > > diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt > index 3dd6d5d..84c5787 100644 > --- a/Documentation/admin-guide/kernel-parameters.txt > +++ b/Documentation/admin-guide/kernel-parameters.txt > @@ -2165,6 +2165,17 @@ > memory contents and reserves bad memory > regions that are detected. > > + mem_encrypt= [X86-64] AMD Secure Memory Encryption (SME) control > + Valid arguments: on, off > + Default (depends on kernel configuration option): > + on (CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT=y) > + off (CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT=n) > + mem_encrypt=on: Activate SME > + mem_encrypt=off: Do not activate SME > + > + Refer to Documentation/x86/amd-memory-encryption.txt > + for details on when memory encryption can be activated. > + > mem_sleep_default= [SUSPEND] Default system suspend mode: > s2idle - Suspend-To-Idle > shallow - Power-On Suspend or equivalent (if supported) > diff --git a/Documentation/x86/amd-memory-encryption.txt b/Documentation/x86/amd-memory-encryption.txt > new file mode 100644 > index 0000000..0b72ff2 > --- /dev/null > +++ b/Documentation/x86/amd-memory-encryption.txt > @@ -0,0 +1,60 @@ > +Secure Memory Encryption (SME) is a feature found on AMD processors. > + > +SME provides the ability to mark individual pages of memory as encrypted using > +the standard x86 page tables. A page that is marked encrypted will be > +automatically decrypted when read from DRAM and encrypted when written to > +DRAM. SME can therefore be used to protect the contents of DRAM from physical > +attacks on the system. > + > +A page is encrypted when a page table entry has the encryption bit set (see > +below on how to determine its position). The encryption bit can be specified > +in the cr3 register, allowing the PGD table to be encrypted. Each successive I missed that the last time: do you mean here, "The encryption bit can be specified in the %cr3 register allowing for the page table hierarchy itself to be encrypted."? > +level of page tables can also be encrypted. Right, judging by the next sentence, it looks like it. The rest looks and reads really nice to me, so feel free to add: Reviewed-by: Borislav Petkov <bp@suse.de> after addressing those minor nitpicks on your next submission. Thanks. -- Regards/Gruss, Boris. Good mailing practices for 400: avoid top-posting and trim the reply. ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v5 01/32] x86: Documentation for AMD Secure Memory Encryption (SME) 2017-04-19 9:02 ` Borislav Petkov @ 2017-04-19 14:23 ` Tom Lendacky 2017-04-19 15:38 ` Borislav Petkov 0 siblings, 1 reply; 12+ messages in thread From: Tom Lendacky @ 2017-04-19 14:23 UTC (permalink / raw) To: Borislav Petkov Cc: linux-arch, linux-efi, kvm, linux-doc, x86, kexec, linux-kernel, kasan-dev, linux-mm, iommu, Rik van Riel, Radim Krčmář, Toshimitsu Kani, Arnd Bergmann, Jonathan Corbet, Matt Fleming, Michael S. Tsirkin, Joerg Roedel, Konrad Rzeszutek Wilk, Paolo Bonzini, Larry Woodman, Brijesh Singh, Ingo Molnar, Andy Lutomirski, H. Peter Anvin, Andrey Ryabinin, Alexander Potapenko, Dave Young, Thomas Gleixner, Dmitry Vyukov On 4/19/2017 4:02 AM, Borislav Petkov wrote: > Always have a verb in the Subject to form a "do this" or "do that" > sentence to better explain what the patch does: > > "Subject: [PATCH v5 01/32] x86: Add documentation for AMD Secure Memory Encryption (SME)" Will do. Btw, I tried to update all the subjects and descriptions to be more descriptive but I'm sure there is still room for improvement so keep the comments on them coming. > > On Tue, Apr 18, 2017 at 04:16:25PM -0500, Tom Lendacky wrote: >> Create a Documentation entry to describe the AMD Secure Memory >> Encryption (SME) feature and add documentation for the mem_encrypt= >> kernel parameter. >> >> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> >> --- >> Documentation/admin-guide/kernel-parameters.txt | 11 ++++ >> Documentation/x86/amd-memory-encryption.txt | 60 +++++++++++++++++++++++ >> 2 files changed, 71 insertions(+) >> create mode 100644 Documentation/x86/amd-memory-encryption.txt >> >> diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt >> index 3dd6d5d..84c5787 100644 >> --- a/Documentation/admin-guide/kernel-parameters.txt >> +++ b/Documentation/admin-guide/kernel-parameters.txt >> @@ -2165,6 +2165,17 @@ >> memory contents and reserves bad memory >> regions that are detected. >> >> + mem_encrypt= [X86-64] AMD Secure Memory Encryption (SME) control >> + Valid arguments: on, off >> + Default (depends on kernel configuration option): >> + on (CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT=y) >> + off (CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT=n) >> + mem_encrypt=on: Activate SME >> + mem_encrypt=off: Do not activate SME >> + >> + Refer to Documentation/x86/amd-memory-encryption.txt >> + for details on when memory encryption can be activated. >> + >> mem_sleep_default= [SUSPEND] Default system suspend mode: >> s2idle - Suspend-To-Idle >> shallow - Power-On Suspend or equivalent (if supported) >> diff --git a/Documentation/x86/amd-memory-encryption.txt b/Documentation/x86/amd-memory-encryption.txt >> new file mode 100644 >> index 0000000..0b72ff2 >> --- /dev/null >> +++ b/Documentation/x86/amd-memory-encryption.txt >> @@ -0,0 +1,60 @@ >> +Secure Memory Encryption (SME) is a feature found on AMD processors. >> + >> +SME provides the ability to mark individual pages of memory as encrypted using >> +the standard x86 page tables. A page that is marked encrypted will be >> +automatically decrypted when read from DRAM and encrypted when written to >> +DRAM. SME can therefore be used to protect the contents of DRAM from physical >> +attacks on the system. >> + >> +A page is encrypted when a page table entry has the encryption bit set (see >> +below on how to determine its position). The encryption bit can be specified >> +in the cr3 register, allowing the PGD table to be encrypted. Each successive > > I missed that the last time: do you mean here, "The encryption bit can > be specified in the %cr3 register allowing for the page table hierarchy > itself to be encrypted."? > >> +level of page tables can also be encrypted. > > Right, judging by the next sentence, it looks like it. Correct. I like the hierarchy term so I'll add that to the text. Note, just because the bit is set in %cr3 doesn't mean the full hierarchy is encrypted. Each level in the hierarchy needs to have the encryption bit set. So, theoretically, you could have the encryption bit set in %cr3 so that the PGD is encrypted, but not set the encryption bit in the PGD entry for a PUD and so the PUD pointed to by that entry would not be encrypted. Thanks, Tom > > The rest looks and reads really nice to me, so feel free to add: > > Reviewed-by: Borislav Petkov <bp@suse.de> > > after addressing those minor nitpicks on your next submission. > > Thanks. > ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v5 01/32] x86: Documentation for AMD Secure Memory Encryption (SME) 2017-04-19 14:23 ` Tom Lendacky @ 2017-04-19 15:38 ` Borislav Petkov 0 siblings, 0 replies; 12+ messages in thread From: Borislav Petkov @ 2017-04-19 15:38 UTC (permalink / raw) To: Tom Lendacky Cc: linux-arch, linux-efi, kvm, linux-doc, x86, kexec, linux-kernel, kasan-dev, linux-mm, iommu, Rik van Riel, Radim Krčmář, Toshimitsu Kani, Arnd Bergmann, Jonathan Corbet, Matt Fleming, Michael S. Tsirkin, Joerg Roedel, Konrad Rzeszutek Wilk, Paolo Bonzini, Larry Woodman, Brijesh Singh, Ingo Molnar, Andy Lutomirski, H. Peter Anvin, Andrey Ryabinin, Alexander Potapenko, Dave Young, Thomas Gleixner, Dmitry Vyukov On Wed, Apr 19, 2017 at 09:23:47AM -0500, Tom Lendacky wrote: > Btw, I tried to update all the subjects and descriptions to be > more descriptive but I'm sure there is still room for improvement > so keep the comments on them coming. No worries there :) > Note, just because the bit is set in %cr3 doesn't mean the full > hierarchy is encrypted. Each level in the hierarchy needs to have the > encryption bit set. So, theoretically, you could have the encryption > bit set in %cr3 so that the PGD is encrypted, but not set the encryption > bit in the PGD entry for a PUD and so the PUD pointed to by that entry > would not be encrypted. Ha, that is a nice detail I didn't realize. You could add it to the text. Thanks. -- Regards/Gruss, Boris. Good mailing practices for 400: avoid top-posting and trim the reply. ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v5 01/32] x86: Documentation for AMD Secure Memory Encryption (SME) 2017-04-18 21:16 ` [PATCH v5 01/32] x86: Documentation for AMD Secure Memory Encryption (SME) Tom Lendacky 2017-04-19 9:02 ` Borislav Petkov @ 2017-04-19 9:52 ` David Howells 1 sibling, 0 replies; 12+ messages in thread From: David Howells @ 2017-04-19 9:52 UTC (permalink / raw) To: Borislav Petkov Cc: dhowells, Tom Lendacky, linux-arch, linux-efi, kvm, linux-doc, x86, kexec, linux-kernel, kasan-dev, linux-mm, iommu, Rik van Riel, Radim Krčmář, Toshimitsu Kani, Arnd Bergmann, Jonathan Corbet, Matt Fleming, Michael S. Tsirkin, Joerg Roedel, Konrad Rzeszutek Wilk, Paolo Bonzini, Larry Woodman, Brijesh Singh, Ingo Molnar, Andy Lutomirski, H. Peter Anvin, Andrey Ryabinin, Alexander Potapenko, Dave Young, Thomas Gleixner, Dmitry Vyukov Borislav Petkov <bp@alien8.de> wrote: > "Subject: [PATCH v5 01/32] x86: Add documentation for AMD Secure Memory Encryption (SME)" Or: x86: Document AMD Secure Memory Encryption (SME) support David ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2017-04-19 15:38 UTC | newest] Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2017-04-18 21:14 [PATCH v5 00/32] x86: Secure Memory Encryption (AMD) Tom Lendacky 2017-04-18 21:14 ` [PATCH v5 01/32] x86: Documentation for AMD Secure Memory Encryption (SME) Tom Lendacky 2017-04-18 21:14 ` [PATCH v5 02/32] x86/mm/pat: Set write-protect cache mode for full PAT support Tom Lendacky 2017-04-18 21:14 ` [PATCH v5 03/32] x86, mpparse, x86/acpi, x86/PCI, SFI: Use memremap for RAM mappings Tom Lendacky 2017-04-18 21:14 ` [PATCH v5 04/32] x86/CPU/AMD: Add the Secure Memory Encryption CPU feature Tom Lendacky 2017-04-18 21:14 ` [PATCH v5 05/32] x86/CPU/AMD: Handle SME reduction in physical address size Tom Lendacky 2017-04-18 21:15 ` [PATCH v5 06/32] x86/mm: Add Secure Memory Encryption (SME) support Tom Lendacky 2017-04-18 21:16 [PATCH v5 00/32] x86: Secure Memory Encryption (AMD) Tom Lendacky 2017-04-18 21:16 ` [PATCH v5 01/32] x86: Documentation for AMD Secure Memory Encryption (SME) Tom Lendacky 2017-04-19 9:02 ` Borislav Petkov 2017-04-19 14:23 ` Tom Lendacky 2017-04-19 15:38 ` Borislav Petkov 2017-04-19 9:52 ` David Howells
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