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* [PATCH 1/6] perf/x86: Move Nehalem PEBS code to flag
@ 2017-06-02 20:12 Andi Kleen
  2017-06-02 20:12 ` [PATCH 2/6] perf/x86: Fix data source decoding for Skylake Andi Kleen
                   ` (4 more replies)
  0 siblings, 5 replies; 10+ messages in thread
From: Andi Kleen @ 2017-06-02 20:12 UTC (permalink / raw)
  To: peterz, acme; +Cc: eranian, jolsa, linux-kernel, Andi Kleen

From: Andi Kleen <ak@linux.intel.com>

Minor cleanup: use an explicit x86_pmu flag to handle the
missing Lock / TLB information on Nehalem, instead of always
checking the model number for each PEBS sample.

Signed-off-by: Andi Kleen <ak@linux.intel.com>
---
 arch/x86/events/intel/core.c | 1 +
 arch/x86/events/intel/ds.c   | 5 +----
 arch/x86/events/perf_event.h | 3 ++-
 3 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index a6d91d4e37a1..59933105d0ea 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -3712,6 +3712,7 @@ __init int intel_pmu_init(void)
 
 		intel_pmu_pebs_data_source_nhm();
 		x86_add_quirk(intel_nehalem_quirk);
+		x86_pmu.pebs_no_tlb = 1;
 
 		pr_cont("Nehalem events, ");
 		break;
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index c6d23ffe422d..7732999f5e2a 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -149,8 +149,6 @@ static u64 load_latency_data(u64 status)
 {
 	union intel_x86_pebs_dse dse;
 	u64 val;
-	int model = boot_cpu_data.x86_model;
-	int fam = boot_cpu_data.x86;
 
 	dse.val = status;
 
@@ -162,8 +160,7 @@ static u64 load_latency_data(u64 status)
 	/*
 	 * Nehalem models do not support TLB, Lock infos
 	 */
-	if (fam == 0x6 && (model == 26 || model == 30
-	    || model == 31 || model == 46)) {
+	if (x86_pmu.pebs_no_tlb) {
 		val |= P(TLB, NA) | P(LOCK, NA);
 		return val;
 	}
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index be3d36254040..6f5461fe582b 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -588,7 +588,8 @@ struct x86_pmu {
 			pebs		:1,
 			pebs_active	:1,
 			pebs_broken	:1,
-			pebs_prec_dist	:1;
+			pebs_prec_dist	:1,
+			pebs_no_tlb	:1;
 	int		pebs_record_size;
 	int		pebs_buffer_size;
 	void		(*drain_pebs)(struct pt_regs *regs);
-- 
2.9.4

^ permalink raw reply related	[flat|nested] 10+ messages in thread
* [PATCH 1/6] perf/x86: Move Nehalem PEBS code to flag
@ 2017-06-05 22:48 Andi Kleen
  2017-06-05 22:48 ` [PATCH 4/6] perf/x86: Add support for PEBS sampling persistent RAM on Skylake Andi Kleen
  0 siblings, 1 reply; 10+ messages in thread
From: Andi Kleen @ 2017-06-05 22:48 UTC (permalink / raw)
  To: peterz, acme; +Cc: linux-kernel, jolsa, Andi Kleen

From: Andi Kleen <ak@linux.intel.com>

Minor cleanup: use an explicit x86_pmu flag to handle the
missing Lock / TLB information on Nehalem, instead of always
checking the model number for each PEBS sample.

Signed-off-by: Andi Kleen <ak@linux.intel.com>
---
 arch/x86/events/intel/core.c | 1 +
 arch/x86/events/intel/ds.c   | 5 +----
 arch/x86/events/perf_event.h | 3 ++-
 3 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index a6d91d4e37a1..59933105d0ea 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -3712,6 +3712,7 @@ __init int intel_pmu_init(void)
 
 		intel_pmu_pebs_data_source_nhm();
 		x86_add_quirk(intel_nehalem_quirk);
+		x86_pmu.pebs_no_tlb = 1;
 
 		pr_cont("Nehalem events, ");
 		break;
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index c6d23ffe422d..7732999f5e2a 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -149,8 +149,6 @@ static u64 load_latency_data(u64 status)
 {
 	union intel_x86_pebs_dse dse;
 	u64 val;
-	int model = boot_cpu_data.x86_model;
-	int fam = boot_cpu_data.x86;
 
 	dse.val = status;
 
@@ -162,8 +160,7 @@ static u64 load_latency_data(u64 status)
 	/*
 	 * Nehalem models do not support TLB, Lock infos
 	 */
-	if (fam == 0x6 && (model == 26 || model == 30
-	    || model == 31 || model == 46)) {
+	if (x86_pmu.pebs_no_tlb) {
 		val |= P(TLB, NA) | P(LOCK, NA);
 		return val;
 	}
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index be3d36254040..6f5461fe582b 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -588,7 +588,8 @@ struct x86_pmu {
 			pebs		:1,
 			pebs_active	:1,
 			pebs_broken	:1,
-			pebs_prec_dist	:1;
+			pebs_prec_dist	:1,
+			pebs_no_tlb	:1;
 	int		pebs_record_size;
 	int		pebs_buffer_size;
 	void		(*drain_pebs)(struct pt_regs *regs);
-- 
2.9.4

^ permalink raw reply related	[flat|nested] 10+ messages in thread

end of thread, other threads:[~2017-06-07  2:11 UTC | newest]

Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-06-02 20:12 [PATCH 1/6] perf/x86: Move Nehalem PEBS code to flag Andi Kleen
2017-06-02 20:12 ` [PATCH 2/6] perf/x86: Fix data source decoding for Skylake Andi Kleen
2017-06-02 20:12 ` [PATCH 3/6] perf, tools: Add support for printing new mem_info encodings Andi Kleen
2017-06-02 20:12 ` [PATCH 4/6] perf/x86: Add support for PEBS sampling persistent RAM on Skylake Andi Kleen
2017-06-02 20:12 ` [PATCH 5/6] perf, tools: Support persistent memory encoding Andi Kleen
2017-06-02 20:12 ` [PATCH 6/6] perf, tools: Add test cases for new data source encoding Andi Kleen
2017-06-05 10:33   ` Jiri Olsa
2017-06-05 22:49     ` Andi Kleen
2017-06-07  2:08   ` [lkp-robot] [perf, tools] d03bd7bd14: perf-sanity-tests.Test_data_source_output.fail kernel test robot
2017-06-05 22:48 [PATCH 1/6] perf/x86: Move Nehalem PEBS code to flag Andi Kleen
2017-06-05 22:48 ` [PATCH 4/6] perf/x86: Add support for PEBS sampling persistent RAM on Skylake Andi Kleen

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