[PATCH 00/10] irqchip: sunxi-nmi: Cleanups and fix A31 R_INTC register offset

[PATCH 00/10] irqchip: sunxi-nmi: Cleanups and fix A31 R_INTC register offset

[Chen-Yu Tsai]

Hi everyone,

This is an alternative to Icenowy's recent A64 R_INTC patches.

This is a two part series. The first four patches clean up the existing
sunxi-nmi driver. Patches five and six add a new "sun6i-a31-r-intc"
compatible, which mainly adjusts or removes the awkward register region
offset the old "sun6i-a31-sc-nmi" compatible needed. The remaining
patches fix or add device nodes for SoC's having this hardware.

Using "sun6i-a31-r-intc" introduced in this series, instead of Icenowy's
"sun50i-a64-r-intc" is preferred. This follows our policy of naming
hardware blocks and compatibles after their first occurrence.

The first six patches should go through the irqchip tree, while we
(sunxi) can take the device tree changes after the driver has been
merged, to avoid breaking linux-next as a whole.


Regards
ChenYu


Chen-Yu Tsai (9):
  irqchip: sunxi-nmi: Convert magic numbers to defines
  irqchip: sunxi-nmi: Document interrupt disabling and clearing at probe
    time
  irqchip: sunxi-nmi: Reorder sunxi_sc_nmi_reg_offs' in ascending order
  irqchip: sunxi-nmi: const-ify sunxi_sc_nmi_reg_offs structures
  dt-bindings: interrupt-controller: sunxi-nmi: Add compatible for A31
    R_INTC
  irqchip: sunxi-nmi: Support sun6i-a31-r-intc compatible
  ARM: sun6i: a31: Use new sun6i-a31-r-intc compatible for NMI/R_INTC
  ARM: sun8i: a23/a33: Use new sun6i-a31-r-intc compatible for
    NMI/R_INTC
  ARM: sun8i: a83t: Add device node for R_INTC interrupt controller

Icenowy Zheng (1):
  arm64: allwinner: a64: add NMI (R_INTC) controller on A64

 .../interrupt-controller/allwinner,sunxi-nmi.txt   |  7 ++-
 arch/arm/boot/dts/sun6i-a31.dtsi                   |  6 +-
 arch/arm/boot/dts/sun8i-a23-a33.dtsi               |  6 +-
 arch/arm/boot/dts/sun8i-a83t.dtsi                  |  9 +++
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi      |  9 +++
 drivers/irqchip/irq-sunxi-nmi.c                    | 68 +++++++++++++++++-----
 6 files changed, 83 insertions(+), 22 deletions(-)

-- 
2.11.0

[PATCH 01/10] irqchip: sunxi-nmi: Convert magic numbers to defines

[Chen-Yu Tsai]

The sunxi-nmi driver has a bunch of raw register offsets and bit values.

Convert them into define macros for better readability.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 drivers/irqchip/irq-sunxi-nmi.c | 34 ++++++++++++++++++++++++----------
 1 file changed, 24 insertions(+), 10 deletions(-)

diff --git a/drivers/irqchip/irq-sunxi-nmi.c b/drivers/irqchip/irq-sunxi-nmi.c
index 668730c5cb66..177efb473c7d 100644
--- a/drivers/irqchip/irq-sunxi-nmi.c
+++ b/drivers/irqchip/irq-sunxi-nmi.c
@@ -25,6 +25,20 @@
 
 #define SUNXI_NMI_SRC_TYPE_MASK	0x00000003
 
+#define SUNXI_NMI_IRQ_BIT	BIT(0)
+
+#define SUN6I_NMI_CTRL		0x00
+#define SUN6I_NMI_PENDING	0x04
+#define SUN6I_NMI_ENABLE	0x34
+
+#define SUN7I_NMI_CTRL		0x00
+#define SUN7I_NMI_PENDING	0x04
+#define SUN7I_NMI_ENABLE	0x08
+
+#define SUN9I_NMI_CTRL		0x00
+#define SUN9I_NMI_ENABLE	0x04
+#define SUN9I_NMI_PENDING	0x08
+
 enum {
 	SUNXI_SRC_TYPE_LEVEL_LOW = 0,
 	SUNXI_SRC_TYPE_EDGE_FALLING,
@@ -39,21 +53,21 @@ struct sunxi_sc_nmi_reg_offs {
 };
 
 static struct sunxi_sc_nmi_reg_offs sun7i_reg_offs = {
-	.ctrl	= 0x00,
-	.pend	= 0x04,
-	.enable	= 0x08,
+	.ctrl	= SUN7I_NMI_CTRL,
+	.pend	= SUN7I_NMI_PENDING,
+	.enable	= SUN7I_NMI_ENABLE,
 };
 
 static struct sunxi_sc_nmi_reg_offs sun6i_reg_offs = {
-	.ctrl	= 0x00,
-	.pend	= 0x04,
-	.enable	= 0x34,
+	.ctrl	= SUN6I_NMI_CTRL,
+	.pend	= SUN6I_NMI_PENDING,
+	.enable	= SUN6I_NMI_ENABLE,
 };
 
 static struct sunxi_sc_nmi_reg_offs sun9i_reg_offs = {
-	.ctrl	= 0x00,
-	.pend	= 0x08,
-	.enable	= 0x04,
+	.ctrl	= SUN9I_NMI_CTRL,
+	.pend	= SUN9I_NMI_PENDING,
+	.enable	= SUN9I_NMI_ENABLE,
 };
 
 static inline void sunxi_sc_nmi_write(struct irq_chip_generic *gc, u32 off,
@@ -188,7 +202,7 @@ static int __init sunxi_sc_nmi_irq_init(struct device_node *node,
 	gc->chip_types[1].handler		= handle_edge_irq;
 
 	sunxi_sc_nmi_write(gc, reg_offs->enable, 0);
-	sunxi_sc_nmi_write(gc, reg_offs->pend, 0x1);
+	sunxi_sc_nmi_write(gc, reg_offs->pend, SUNXI_NMI_IRQ_BIT);
 
 	irq_set_chained_handler_and_data(irq, sunxi_sc_nmi_handle_irq, domain);
 
-- 
2.11.0

[PATCH 02/10] irqchip: sunxi-nmi: Document interrupt disabling and clearing at probe time

[Chen-Yu Tsai]

The sunxi-nmi disables all its interrupts and clears any pending
interrupts at probe time.

Add comments documenting it, just to make it clear.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 drivers/irqchip/irq-sunxi-nmi.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/irqchip/irq-sunxi-nmi.c b/drivers/irqchip/irq-sunxi-nmi.c
index 177efb473c7d..9a7f6971cc3a 100644
--- a/drivers/irqchip/irq-sunxi-nmi.c
+++ b/drivers/irqchip/irq-sunxi-nmi.c
@@ -201,7 +201,10 @@ static int __init sunxi_sc_nmi_irq_init(struct device_node *node,
 	gc->chip_types[1].regs.type		= reg_offs->ctrl;
 	gc->chip_types[1].handler		= handle_edge_irq;
 
+	/* Disable any active interrupts */
 	sunxi_sc_nmi_write(gc, reg_offs->enable, 0);
+
+	/* Clear any pending NMI interrupts */
 	sunxi_sc_nmi_write(gc, reg_offs->pend, SUNXI_NMI_IRQ_BIT);
 
 	irq_set_chained_handler_and_data(irq, sunxi_sc_nmi_handle_irq, domain);
-- 
2.11.0

[PATCH 03/10] irqchip: sunxi-nmi: Reorder sunxi_sc_nmi_reg_offs' in ascending order

[Chen-Yu Tsai]

This is a pure code move to reorder the various sunxi_sc_nmi_reg_offs'
by family and alphabetical order. No functionality changes.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 drivers/irqchip/irq-sunxi-nmi.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/irqchip/irq-sunxi-nmi.c b/drivers/irqchip/irq-sunxi-nmi.c
index 9a7f6971cc3a..76f2431b6b7b 100644
--- a/drivers/irqchip/irq-sunxi-nmi.c
+++ b/drivers/irqchip/irq-sunxi-nmi.c
@@ -52,18 +52,18 @@ struct sunxi_sc_nmi_reg_offs {
 	u32 enable;
 };
 
-static struct sunxi_sc_nmi_reg_offs sun7i_reg_offs = {
-	.ctrl	= SUN7I_NMI_CTRL,
-	.pend	= SUN7I_NMI_PENDING,
-	.enable	= SUN7I_NMI_ENABLE,
-};
-
 static struct sunxi_sc_nmi_reg_offs sun6i_reg_offs = {
 	.ctrl	= SUN6I_NMI_CTRL,
 	.pend	= SUN6I_NMI_PENDING,
 	.enable	= SUN6I_NMI_ENABLE,
 };
 
+static struct sunxi_sc_nmi_reg_offs sun7i_reg_offs = {
+	.ctrl	= SUN7I_NMI_CTRL,
+	.pend	= SUN7I_NMI_PENDING,
+	.enable	= SUN7I_NMI_ENABLE,
+};
+
 static struct sunxi_sc_nmi_reg_offs sun9i_reg_offs = {
 	.ctrl	= SUN9I_NMI_CTRL,
 	.pend	= SUN9I_NMI_PENDING,
-- 
2.11.0

[PATCH 04/10] irqchip: sunxi-nmi: const-ify sunxi_sc_nmi_reg_offs structures

[Chen-Yu Tsai]

The sunxi_sc_nmi_reg_offs, which hold the register offsets for the
various variants, is never modified, and only used at init time within
the init functions referenced by IRQCHIP_DECLARE, which themselves are
tagged __init.

Const-ify the sunxi_sc_nmi_reg_offs structures, and tag them as
__initconst.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 drivers/irqchip/irq-sunxi-nmi.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/irqchip/irq-sunxi-nmi.c b/drivers/irqchip/irq-sunxi-nmi.c
index 76f2431b6b7b..e713ec66322b 100644
--- a/drivers/irqchip/irq-sunxi-nmi.c
+++ b/drivers/irqchip/irq-sunxi-nmi.c
@@ -52,19 +52,19 @@ struct sunxi_sc_nmi_reg_offs {
 	u32 enable;
 };
 
-static struct sunxi_sc_nmi_reg_offs sun6i_reg_offs = {
+static const struct sunxi_sc_nmi_reg_offs sun6i_reg_offs __initconst = {
 	.ctrl	= SUN6I_NMI_CTRL,
 	.pend	= SUN6I_NMI_PENDING,
 	.enable	= SUN6I_NMI_ENABLE,
 };
 
-static struct sunxi_sc_nmi_reg_offs sun7i_reg_offs = {
+static const struct sunxi_sc_nmi_reg_offs sun7i_reg_offs __initconst = {
 	.ctrl	= SUN7I_NMI_CTRL,
 	.pend	= SUN7I_NMI_PENDING,
 	.enable	= SUN7I_NMI_ENABLE,
 };
 
-static struct sunxi_sc_nmi_reg_offs sun9i_reg_offs = {
+static const struct sunxi_sc_nmi_reg_offs sun9i_reg_offs __initconst = {
 	.ctrl	= SUN9I_NMI_CTRL,
 	.pend	= SUN9I_NMI_PENDING,
 	.enable	= SUN9I_NMI_ENABLE,
@@ -142,7 +142,7 @@ static int sunxi_sc_nmi_set_type(struct irq_data *data, unsigned int flow_type)
 }
 
 static int __init sunxi_sc_nmi_irq_init(struct device_node *node,
-					struct sunxi_sc_nmi_reg_offs *reg_offs)
+					const struct sunxi_sc_nmi_reg_offs *reg_offs)
 {
 	struct irq_domain *domain;
 	struct irq_chip_generic *gc;
-- 
2.11.0

[PATCH 05/10] dt-bindings: interrupt-controller: sunxi-nmi: Add compatible for A31 R_INTC

[Chen-Yu Tsai]

The A31 and later have an R_INTC block which handles the NMI interrupt
pin on the SoC. This interrupt pin is used by the external PMIC to
signal interrupts to the SoC.

While this hardware block is undocumented, the interrupt offsets
combined with the register regions for the existing "sun6i-a31-sc-nmi"
compatible line up with the old interrupt controller found on the A10.
Experiments show that only the first 32 interrupt lines can be enabled,
and only the first (NMI) interrupt is actually connected.

This patch adds a new, properly named compatible for the A31 R_INTC
block, which requires the register region to be properly aligned to
the block boundary. For comparison, the old "sun6i-a31-sc-nmi"
compatible had its register region aligned with the first used
register. This didn't match up with the memory map in the SoC's
datasheet/user manual.

Since the new compatible supercedes the old one, deprecate the old one.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 .../bindings/interrupt-controller/allwinner,sunxi-nmi.txt          | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt
index 81cd3692405e..4ae553eb333d 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt
@@ -3,8 +3,11 @@ Allwinner Sunxi NMI Controller
 
 Required properties:
 
-- compatible : should be "allwinner,sun7i-a20-sc-nmi" or
-  "allwinner,sun6i-a31-sc-nmi" or "allwinner,sun9i-a80-nmi"
+- compatible : should be one of the following:
+  - "allwinner,sun7i-a20-sc-nmi"
+  - "allwinner,sun6i-a31-sc-nmi" (deprecated)
+  - "allwinner,sun6i-a31-r-intc"
+  - "allwinner,sun9i-a80-nmi"
 - reg : Specifies base physical address and size of the registers.
 - interrupt-controller : Identifies the node as an interrupt controller
 - #interrupt-cells : Specifies the number of cells needed to encode an
-- 
2.11.0

[PATCH 06/10] irqchip: sunxi-nmi: Support sun6i-a31-r-intc compatible

[Chen-Yu Tsai]

The R_INTC on the A31 is undocumented. It was previously supported
by the sun6i-a31-sc-nmi compatible. This compatible however required
the register region to start at the first used register, rather than
the boundaries laid out in the SoC's memory map. The new compatible
fixes the alignment, while also naming it properly.

Since the only difference between the old and new compatibles are
a fixed offset for the registers, and since the old one is deprecated,
this patch adds a set of register defines for the new compatible,
while modifying the old set to reference the new set minus a fixed
offset.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 drivers/irqchip/irq-sunxi-nmi.c | 29 ++++++++++++++++++++++++++---
 1 file changed, 26 insertions(+), 3 deletions(-)

diff --git a/drivers/irqchip/irq-sunxi-nmi.c b/drivers/irqchip/irq-sunxi-nmi.c
index e713ec66322b..a412b5d5d0fa 100644
--- a/drivers/irqchip/irq-sunxi-nmi.c
+++ b/drivers/irqchip/irq-sunxi-nmi.c
@@ -27,9 +27,18 @@
 
 #define SUNXI_NMI_IRQ_BIT	BIT(0)
 
-#define SUN6I_NMI_CTRL		0x00
-#define SUN6I_NMI_PENDING	0x04
-#define SUN6I_NMI_ENABLE	0x34
+#define SUN6I_R_INTC_CTRL	0x0c
+#define SUN6I_R_INTC_PENDING	0x10
+#define SUN6I_R_INTC_ENABLE	0x40
+
+/*
+ * For deprecated sun6i-a31-sc-nmi compatible.
+ * Registers are offset by 0x0c.
+ */
+#define SUN6I_R_INTC_NMI_OFFSET	0x0c
+#define SUN6I_NMI_CTRL		(SUN6I_R_INTC_CTRL - SUN6I_R_INTC_NMI_OFFSET)
+#define SUN6I_NMI_PENDING	(SUN6I_R_INTC_PENDING - SUN6I_R_INTC_NMI_OFFSET)
+#define SUN6I_NMI_ENABLE	(SUN6I_R_INTC_ENABLE - SUN6I_R_INTC_NMI_OFFSET)
 
 #define SUN7I_NMI_CTRL		0x00
 #define SUN7I_NMI_PENDING	0x04
@@ -52,6 +61,12 @@ struct sunxi_sc_nmi_reg_offs {
 	u32 enable;
 };
 
+static const struct sunxi_sc_nmi_reg_offs sun6i_r_intc_reg_offs __initconst = {
+	.ctrl	= SUN6I_R_INTC_CTRL,
+	.pend	= SUN6I_R_INTC_PENDING,
+	.enable	= SUN6I_R_INTC_ENABLE,
+};
+
 static const struct sunxi_sc_nmi_reg_offs sun6i_reg_offs __initconst = {
 	.ctrl	= SUN6I_NMI_CTRL,
 	.pend	= SUN6I_NMI_PENDING,
@@ -217,6 +232,14 @@ static int __init sunxi_sc_nmi_irq_init(struct device_node *node,
 	return ret;
 }
 
+static int __init sun6i_r_intc_irq_init(struct device_node *node,
+					struct device_node *parent)
+{
+	return sunxi_sc_nmi_irq_init(node, &sun6i_r_intc_reg_offs);
+}
+IRQCHIP_DECLARE(sun6i_r_intc, "allwinner,sun6i-a31-r-intc",
+		sun6i_r_intc_irq_init);
+
 static int __init sun6i_sc_nmi_irq_init(struct device_node *node,
 					struct device_node *parent)
 {
-- 
2.11.0

[PATCH 07/10] ARM: sun6i: a31: Use new sun6i-a31-r-intc compatible for NMI/R_INTC

[Chen-Yu Tsai]

We introduced a new compatible for the NMI or R_INTC interrupt
controller. This new compatible has the register region aligned
to the boundary listed in the SoC's memory map.

This patch converts the NMI/R_INTC node to using the new compatible,
and fixes up the register region and device node name.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun6i-a31.dtsi | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index d0cede5aaeb5..d36211ceb950 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -1154,11 +1154,11 @@
 				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
-		nmi_intc: interrupt-controller@01f00c0c {
-			compatible = "allwinner,sun6i-a31-sc-nmi";
+		nmi_intc: interrupt-controller@1f00c00 {
+			compatible = "allwinner,sun6i-a31-r-intc";
 			interrupt-controller;
 			#interrupt-cells = <2>;
-			reg = <0x01f00c0c 0x38>;
+			reg = <0x01f00c00 0x400>;
 			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
-- 
2.11.0

[PATCH 08/10] ARM: sun8i: a23/a33: Use new sun6i-a31-r-intc compatible for NMI/R_INTC

[Chen-Yu Tsai]

We introduced a new compatible for the NMI or R_INTC interrupt
controller. This new compatible has the register region aligned
to the boundary listed in the SoC's memory map.

This patch converts the NMI/R_INTC node to using the new compatible,
and fixes up the register region and device node name.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun8i-a23-a33.dtsi | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index a8b978d0f35b..ea50dda75adc 100644
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -519,11 +519,11 @@
 			#clock-cells = <1>;
 		};
 
-		nmi_intc: interrupt-controller@01f00c0c {
-			compatible = "allwinner,sun6i-a31-sc-nmi";
+		nmi_intc: interrupt-controller@1f00c00 {
+			compatible = "allwinner,sun6i-a31-r-intc";
 			interrupt-controller;
 			#interrupt-cells = <2>;
-			reg = <0x01f00c0c 0x38>;
+			reg = <0x01f00c00 0x400>;
 			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
-- 
2.11.0

[PATCH 09/10] ARM: sun8i: a83t: Add device node for R_INTC interrupt controller

[Chen-Yu Tsai]

The R_INTC interrupt controller handles the NMI interrupt pin for the
SoC. While there is no documentation or code from the vendor for this
device on the A83T, existing mainline kernel drivers and bindings show
this to be similar to the old Allwinner interrupt controller found on
the A10 SoC, but with only the NMI interrupt wired. Register poking
experiments confirm this.

The device seems to be the same across all recent Allwinner SoCs, apart
from the A20 and A80, which have a separate set of registers to handle
the NMI interrupt. We already have a set of bindings supporting this
on the A31.

Add a device node for it, with an SoC specific compatible.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 49aeb56970ba..4d64dfdc10d3 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -271,6 +271,15 @@
 			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 		};
 
+		r_intc: interrupt-controller@1f00c00 {
+			compatible = "allwinner,sun8i-a83t-r-intc",
+				     "allwinner,sun6i-a31-r-intc";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			reg = <0x01f00c00 0x400>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
 		r_ccu: clock@1f01400 {
 			compatible = "allwinner,sun8i-a83t-r-ccu";
 			reg = <0x01f01400 0x400>;
-- 
2.11.0

[PATCH 10/10] arm64: allwinner: a64: add NMI (R_INTC) controller on A64

[Chen-Yu Tsai]

From: Icenowy Zheng <icenowy@aosc.io>

Allwinner A64 SoC features a R_INTC controller, which controls the NMI
line, and this interrupt line is usually connected to the AXP PMIC.

Add support for it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
[wens@csie.org: Add fallback sun6i-a31-r-intc compatible]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 4eb2f3ca602a..1865bc01d89e 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -445,6 +445,15 @@
 				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		r_intc: interrupt-controller@1f00c00 {
+			compatible = "allwinner,sun50i-a64-r-intc",
+				     "allwinner,sun6i-a31-r-intc";
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			reg = <0x01f00c00 0x400>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
 		r_ccu: clock@1f01400 {
 			compatible = "allwinner,sun50i-a64-r-ccu";
 			reg = <0x01f01400 0x100>;
-- 
2.11.0

Re: [PATCH 00/10] irqchip: sunxi-nmi: Cleanups and fix A31 R_INTC register offset

[Marc Zyngier]

On 06/06/17 06:59, Chen-Yu Tsai wrote:
> Hi everyone,
> 
> This is an alternative to Icenowy's recent A64 R_INTC patches.
> 
> This is a two part series. The first four patches clean up the existing
> sunxi-nmi driver. Patches five and six add a new "sun6i-a31-r-intc"
> compatible, which mainly adjusts or removes the awkward register region
> offset the old "sun6i-a31-sc-nmi" compatible needed. The remaining
> patches fix or add device nodes for SoC's having this hardware.
> 
> Using "sun6i-a31-r-intc" introduced in this series, instead of Icenowy's
> "sun50i-a64-r-intc" is preferred. This follows our policy of naming
> hardware blocks and compatibles after their first occurrence.
> 
> The first six patches should go through the irqchip tree, while we
> (sunxi) can take the device tree changes after the driver has been
> merged, to avoid breaking linux-next as a whole.

So should I drop the original two patches and take those six instead?

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

Re: [PATCH 00/10] irqchip: sunxi-nmi: Cleanups and fix A31 R_INTC register offset

[Icenowy Zheng]

于 2017年6月6日 GMT+08:00 下午11:32:12, Marc Zyngier <marc.zyngier@arm.com> 写到:
>On 06/06/17 06:59, Chen-Yu Tsai wrote:
>> Hi everyone,
>> 
>> This is an alternative to Icenowy's recent A64 R_INTC patches.
>> 
>> This is a two part series. The first four patches clean up the
>existing
>> sunxi-nmi driver. Patches five and six add a new "sun6i-a31-r-intc"
>> compatible, which mainly adjusts or removes the awkward register
>region
>> offset the old "sun6i-a31-sc-nmi" compatible needed. The remaining
>> patches fix or add device nodes for SoC's having this hardware.
>> 
>> Using "sun6i-a31-r-intc" introduced in this series, instead of
>Icenowy's
>> "sun50i-a64-r-intc" is preferred. This follows our policy of naming
>> hardware blocks and compatibles after their first occurrence.
>> 
>> The first six patches should go through the irqchip tree, while we
>> (sunxi) can take the device tree changes after the driver has been
>> merged, to avoid breaking linux-next as a whole.
>
>So should I drop the original two patches and take those six instead?

Yes, please.

>
>Thanks,
>
>	M.

Re: [PATCH 00/10] irqchip: sunxi-nmi: Cleanups and fix A31 R_INTC register offset

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 1130 bytes --]

On Tue, Jun 06, 2017 at 01:59:22PM +0800, Chen-Yu Tsai wrote:
> Hi everyone,
> 
> This is an alternative to Icenowy's recent A64 R_INTC patches.
> 
> This is a two part series. The first four patches clean up the existing
> sunxi-nmi driver. Patches five and six add a new "sun6i-a31-r-intc"
> compatible, which mainly adjusts or removes the awkward register region
> offset the old "sun6i-a31-sc-nmi" compatible needed. The remaining
> patches fix or add device nodes for SoC's having this hardware.
> 
> Using "sun6i-a31-r-intc" introduced in this series, instead of Icenowy's
> "sun50i-a64-r-intc" is preferred. This follows our policy of naming
> hardware blocks and compatibles after their first occurrence.
> 
> The first six patches should go through the irqchip tree, while we
> (sunxi) can take the device tree changes after the driver has been
> merged, to avoid breaking linux-next as a whole.

For the whole serie:
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 801 bytes --]

Re: [PATCH 05/10] dt-bindings: interrupt-controller: sunxi-nmi: Add compatible for A31 R_INTC

[Rob Herring]

On Tue, Jun 06, 2017 at 01:59:27PM +0800, Chen-Yu Tsai wrote:
> The A31 and later have an R_INTC block which handles the NMI interrupt
> pin on the SoC. This interrupt pin is used by the external PMIC to
> signal interrupts to the SoC.
> 
> While this hardware block is undocumented, the interrupt offsets
> combined with the register regions for the existing "sun6i-a31-sc-nmi"
> compatible line up with the old interrupt controller found on the A10.
> Experiments show that only the first 32 interrupt lines can be enabled,
> and only the first (NMI) interrupt is actually connected.
> 
> This patch adds a new, properly named compatible for the A31 R_INTC
> block, which requires the register region to be properly aligned to
> the block boundary. For comparison, the old "sun6i-a31-sc-nmi"
> compatible had its register region aligned with the first used
> register. This didn't match up with the memory map in the SoC's
> datasheet/user manual.
> 
> Since the new compatible supercedes the old one, deprecate the old one.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
>  .../bindings/interrupt-controller/allwinner,sunxi-nmi.txt          | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH 00/10] irqchip: sunxi-nmi: Cleanups and fix A31 R_INTC register offset

[Chen-Yu Tsai]

On Wed, Jun 7, 2017 at 2:47 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> On Tue, Jun 06, 2017 at 01:59:22PM +0800, Chen-Yu Tsai wrote:
>> Hi everyone,
>>
>> This is an alternative to Icenowy's recent A64 R_INTC patches.
>>
>> This is a two part series. The first four patches clean up the existing
>> sunxi-nmi driver. Patches five and six add a new "sun6i-a31-r-intc"
>> compatible, which mainly adjusts or removes the awkward register region
>> offset the old "sun6i-a31-sc-nmi" compatible needed. The remaining
>> patches fix or add device nodes for SoC's having this hardware.
>>
>> Using "sun6i-a31-r-intc" introduced in this series, instead of Icenowy's
>> "sun50i-a64-r-intc" is preferred. This follows our policy of naming
>> hardware blocks and compatibles after their first occurrence.
>>
>> The first six patches should go through the irqchip tree, while we
>> (sunxi) can take the device tree changes after the driver has been
>> merged, to avoid breaking linux-next as a whole.
>
> For the whole serie:
> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Queued the remaining 4 device tree patches for 4.14.

ChenYu