[PATCH 0/3] OMAP4: crypto support

[PATCH 0/3] OMAP4: crypto support

[Sebastian Reichel]

Hi,

This adds crypto support for OMAP4, which was missing for some reason.
This fixes error about missing hwmod on Droid 4. IP-Cores for AES and
DES are working according to selftest.

-- Sebastian

Sebastian Reichel (3):
  ARM: dts: omap4: add missing des_fck
  ARM: OMAP4: hwmod data: add aes
  ARM: OMAP4: hwmod data: add des

 arch/arm/boot/dts/omap44xx-clocks.dtsi     |  8 +++
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 78 ++++++++++++++++++++++++++++++
 2 files changed, 86 insertions(+)

-- 
2.11.0

[PATCH 1/3] ARM: dts: omap4: add missing des_fck

[Sebastian Reichel]

Add missing functional clock for DES3DES IP core. This is
documented in the TRM as CM_L4SEC_DES3DES_CLKCTRL.

Signed-off-by: Sebastian Reichel <sre@kernel.org>
---
 arch/arm/boot/dts/omap44xx-clocks.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi
index 9573b37fbaa7..e997265460d4 100644
--- a/arch/arm/boot/dts/omap44xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi
@@ -985,6 +985,14 @@
 		reg = <0x15a8>;
 	};
 
+	des_fck: des_fck@15b0 {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&l3_div_ck>;
+		ti,bit-shift = <1>;
+		reg = <0x15b0>;
+	};
+
 	dss_sys_clk: dss_sys_clk@1120 {
 		#clock-cells = <0>;
 		compatible = "ti,gate-clock";
-- 
2.11.0

[PATCH 2/3] ARM: OMAP4: hwmod data: add aes

[Sebastian Reichel]

This fixes the following error during kernel boot:

platform 4b501000.aes: Cannot lookup hwmod 'aes'

Unfortunately the AES module is only documented partly
in the OMAP4430 TRM. I found an old patch from Joel,
which I took over and updated for currently mainline.

Signed-off-by: Joel Fernandes <joelf@ti.com>
Signed-off-by: Sebastian Reichel <sre@kernel.org>
---
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 41 ++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 94f09c720f29..18feb49e813b 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -953,6 +953,46 @@ static struct omap_hwmod omap44xx_emif2_hwmod = {
 };
 
 /*
+    Crypto modules AES0/1 belong to:
+	PD_L4_PER power domain
+	CD_L4_SEC clock domain
+	On the L3, the AES modules are mapped to
+	L3_CLK2: Peripherals and multimedia sub clock domain
+*/
+static struct omap_hwmod_class_sysconfig omap44xx_aes1_sysc = {
+	.rev_offs	= 0x80,
+	.sysc_offs	= 0x84,
+	.syss_offs	= 0x88,
+	.sysc_flags	= SYSS_HAS_RESET_STATUS,
+};
+
+static struct omap_hwmod_class omap44xx_aes1_hwmod_class = {
+	.name		= "aes1",
+	.sysc		= &omap44xx_aes1_sysc,
+};
+
+static struct omap_hwmod omap44xx_aes1_hwmod = {
+	.name		= "aes",
+	.class		= &omap44xx_aes1_hwmod_class,
+	.clkdm_name	= "l4_secure_clkdm",
+	.main_clk	= "aes1_fck",
+	.prcm		= {
+		.omap4	= {
+			.context_offs	= OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET,
+			.clkctrl_offs	= OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes1 = {
+	.master		= &omap44xx_l4_per_hwmod,
+	.slave		= &omap44xx_aes1_hwmod,
+	.clk		= "l4_div_ck",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/*
  * 'fdif' class
  * face detection hw accelerator module
  */
@@ -4793,6 +4833,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
 	&omap44xx_l4_abe__wd_timer3_dma,
 	&omap44xx_mpu__emif1,
 	&omap44xx_mpu__emif2,
+	&omap44xx_l3_main_2__aes1,
 	NULL,
 };
 
-- 
2.11.0

[PATCH 3/3] ARM: OMAP4: hwmod data: add des

[Sebastian Reichel]

This fixes the following error during kernel boot:

platform 480a5000.des: Cannot lookup hwmod 'des'

Unfortunately the DES module is only documented partly
in the OMAP4430 TRM. I found an old patch from Joel,
which I took over and updated for currently mainline.

Signed-off-by: Joel Fernandes <joelf@ti.com>
Signed-off-by: Sebastian Reichel <sre@kernel.org>
---
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 37 ++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 18feb49e813b..f2f13c678cfb 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -993,6 +993,42 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes1 = {
 };
 
 /*
+ * 'des' class for DES3DES module
+ */
+static struct omap_hwmod_class_sysconfig omap44xx_des_sysc = {
+	.rev_offs	= 0x30,
+	.sysc_offs	= 0x34,
+	.syss_offs	= 0x38,
+	.sysc_flags	= SYSS_HAS_RESET_STATUS,
+};
+
+static struct omap_hwmod_class omap44xx_des_hwmod_class = {
+	.name		= "des",
+	.sysc		= &omap44xx_des_sysc,
+};
+
+static struct omap_hwmod omap44xx_des_hwmod = {
+	.name		= "des",
+	.class		= &omap44xx_des_hwmod_class,
+	.clkdm_name	= "l4_secure_clkdm",
+	.main_clk	= "des_fck",
+	.prcm		= {
+		.omap4	= {
+			.context_offs	= OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
+			.clkctrl_offs	= OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
+			.modulemode	= MODULEMODE_SWCTRL,
+		},
+	},
+};
+
+struct omap_hwmod_ocp_if omap44xx_l4_per__des = {
+	.master		= &omap44xx_l4_per_hwmod,
+	.slave		= &omap44xx_des_hwmod,
+	.clk		= "des_fck",
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/*
  * 'fdif' class
  * face detection hw accelerator module
  */
@@ -4834,6 +4870,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
 	&omap44xx_mpu__emif1,
 	&omap44xx_mpu__emif2,
 	&omap44xx_l3_main_2__aes1,
+	&omap44xx_l4_per__des,
 	NULL,
 };
 
-- 
2.11.0

Re: [PATCH 1/3] ARM: dts: omap4: add missing des_fck

[Tony Lindgren]

* Sebastian Reichel <sre@kernel.org> [170609 16:16]:
> Add missing functional clock for DES3DES IP core. This is
> documented in the TRM as CM_L4SEC_DES3DES_CLKCTRL.

Tero care to ack? Also, see the other two hwmod patches
in this series for your clkctrl changes.

Regards,

Tony

> Signed-off-by: Sebastian Reichel <sre@kernel.org>
> ---
>  arch/arm/boot/dts/omap44xx-clocks.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi
> index 9573b37fbaa7..e997265460d4 100644
> --- a/arch/arm/boot/dts/omap44xx-clocks.dtsi
> +++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi
> @@ -985,6 +985,14 @@
>  		reg = <0x15a8>;
>  	};
>  
> +	des_fck: des_fck@15b0 {
> +		#clock-cells = <0>;
> +		compatible = "ti,gate-clock";
> +		clocks = <&l3_div_ck>;
> +		ti,bit-shift = <1>;
> +		reg = <0x15b0>;
> +	};
> +
>  	dss_sys_clk: dss_sys_clk@1120 {
>  		#clock-cells = <0>;
>  		compatible = "ti,gate-clock";
> -- 
> 2.11.0
> 

Re: [PATCH 1/3] ARM: dts: omap4: add missing des_fck

[Tero Kristo]

On 10/06/17 02:12, Sebastian Reichel wrote:
> Add missing functional clock for DES3DES IP core. This is
> documented in the TRM as CM_L4SEC_DES3DES_CLKCTRL.
> 
> Signed-off-by: Sebastian Reichel <sre@kernel.org>
> ---
>   arch/arm/boot/dts/omap44xx-clocks.dtsi | 8 ++++++++
>   1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi
> index 9573b37fbaa7..e997265460d4 100644
> --- a/arch/arm/boot/dts/omap44xx-clocks.dtsi
> +++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi
> @@ -985,6 +985,14 @@
>   		reg = <0x15a8>;
>   	};
>   
> +	des_fck: des_fck@15b0 {
> +		#clock-cells = <0>;
> +		compatible = "ti,gate-clock";
> +		clocks = <&l3_div_ck>;
> +		ti,bit-shift = <1>;
> +		reg = <0x15b0>;
> +	};
> +
>   	dss_sys_clk: dss_sys_clk@1120 {
>   		#clock-cells = <0>;
>   		compatible = "ti,gate-clock";
> 

NAK. Don't add a duplicate entry for the hwmod clkctrl clock. You are 
adding control to the exact same bit via the hwmod data entry also 
causing a possibility for race condition.

-Tero

Re: [PATCH 3/3] ARM: OMAP4: hwmod data: add des

[Tero Kristo]

On 10/06/17 02:12, Sebastian Reichel wrote:
> This fixes the following error during kernel boot:
> 
> platform 480a5000.des: Cannot lookup hwmod 'des'
> 
> Unfortunately the DES module is only documented partly
> in the OMAP4430 TRM. I found an old patch from Joel,
> which I took over and updated for currently mainline.
> 
> Signed-off-by: Joel Fernandes <joelf@ti.com>
> Signed-off-by: Sebastian Reichel <sre@kernel.org>
> ---
>   arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 37 ++++++++++++++++++++++++++++++
>   1 file changed, 37 insertions(+)
> 
> diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> index 18feb49e813b..f2f13c678cfb 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> @@ -993,6 +993,42 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes1 = {
>   };
>   
>   /*
> + * 'des' class for DES3DES module
> + */
> +static struct omap_hwmod_class_sysconfig omap44xx_des_sysc = {
> +	.rev_offs	= 0x30,
> +	.sysc_offs	= 0x34,
> +	.syss_offs	= 0x38,
> +	.sysc_flags	= SYSS_HAS_RESET_STATUS,
> +};
> +
> +static struct omap_hwmod_class omap44xx_des_hwmod_class = {
> +	.name		= "des",
> +	.sysc		= &omap44xx_des_sysc,
> +};
> +
> +static struct omap_hwmod omap44xx_des_hwmod = {
> +	.name		= "des",
> +	.class		= &omap44xx_des_hwmod_class,
> +	.clkdm_name	= "l4_secure_clkdm",
> +	.main_clk	= "des_fck",

Change the above to l3_div_ck.

> +	.prcm		= {
> +		.omap4	= {
> +			.context_offs	= OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
> +			.clkctrl_offs	= OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
> +			.modulemode	= MODULEMODE_SWCTRL,
> +		},
> +	},
> +};
> +
> +struct omap_hwmod_ocp_if omap44xx_l4_per__des = {
> +	.master		= &omap44xx_l4_per_hwmod,
> +	.slave		= &omap44xx_des_hwmod,
> +	.clk		= "des_fck",

l3_div_ck.

> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
> +};

l4_per is wrong interconnect for this module. It is actually connected 
to l3_main_2.

> +
> +/*
>    * 'fdif' class
>    * face detection hw accelerator module
>    */
> @@ -4834,6 +4870,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
>   	&omap44xx_mpu__emif1,
>   	&omap44xx_mpu__emif2,
>   	&omap44xx_l3_main_2__aes1,
> +	&omap44xx_l4_per__des,
>   	NULL,
>   };
>   
> 

Re: [PATCH 2/3] ARM: OMAP4: hwmod data: add aes

[Tero Kristo]

On 10/06/17 02:12, Sebastian Reichel wrote:
> This fixes the following error during kernel boot:
> 
> platform 4b501000.aes: Cannot lookup hwmod 'aes'
> 
> Unfortunately the AES module is only documented partly
> in the OMAP4430 TRM. I found an old patch from Joel,
> which I took over and updated for currently mainline.
> 
> Signed-off-by: Joel Fernandes <joelf@ti.com>
> Signed-off-by: Sebastian Reichel <sre@kernel.org>
> ---
>   arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 41 ++++++++++++++++++++++++++++++
>   1 file changed, 41 insertions(+)
> 
> diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> index 94f09c720f29..18feb49e813b 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> @@ -953,6 +953,46 @@ static struct omap_hwmod omap44xx_emif2_hwmod = {
>   };
>   
>   /*
> +    Crypto modules AES0/1 belong to:
> +	PD_L4_PER power domain
> +	CD_L4_SEC clock domain
> +	On the L3, the AES modules are mapped to
> +	L3_CLK2: Peripherals and multimedia sub clock domain
> +*/
> +static struct omap_hwmod_class_sysconfig omap44xx_aes1_sysc = {
> +	.rev_offs	= 0x80,
> +	.sysc_offs	= 0x84,
> +	.syss_offs	= 0x88,
> +	.sysc_flags	= SYSS_HAS_RESET_STATUS,
> +};
> +
> +static struct omap_hwmod_class omap44xx_aes1_hwmod_class = {
> +	.name		= "aes1",
> +	.sysc		= &omap44xx_aes1_sysc,
> +};

Change the names of above from aes1 to aes, the parameters are common 
for both aes instances.

> +
> +static struct omap_hwmod omap44xx_aes1_hwmod = {
> +	.name		= "aes",

This should be aes1.

> +	.class		= &omap44xx_aes1_hwmod_class,
> +	.clkdm_name	= "l4_secure_clkdm",
> +	.main_clk	= "aes1_fck",

Change the aes1_fck to l3_div_ck. aes{1,2}_fck should be removed from 
the dts clock data also to avoid conflicts.

> +	.prcm		= {
> +		.omap4	= {
> +			.context_offs	= OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET,
> +			.clkctrl_offs	= OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET,
> +			.modulemode	= MODULEMODE_SWCTRL,
> +		},
> +	},
> +};
> +
> +static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes1 = {
> +	.master		= &omap44xx_l4_per_hwmod,
> +	.slave		= &omap44xx_aes1_hwmod,
> +	.clk		= "l4_div_ck",

l3_div_ck.

> +	.user		= OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/*
>    * 'fdif' class
>    * face detection hw accelerator module
>    */
> @@ -4793,6 +4833,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
>   	&omap44xx_l4_abe__wd_timer3_dma,
>   	&omap44xx_mpu__emif1,
>   	&omap44xx_mpu__emif2,
> +	&omap44xx_l3_main_2__aes1,
>   	NULL,
>   };
>   
> 

How about aes2 instance? Please note that the DTS data should be fixed 
also (I have patch available for this I can post if you want to pick it 
up as part of this series.)

-Tero