* [PATCH v4 00/20] arm64: dts: hi3660: add device nodes
@ 2017-06-15 3:03 Guodong Xu
2017-06-15 3:03 ` [PATCH v4 01/20] dt-bindings: arm: hisilicon: add bindings for HiKey960 board Guodong Xu
` (20 more replies)
0 siblings, 21 replies; 24+ messages in thread
From: Guodong Xu @ 2017-06-15 3:03 UTC (permalink / raw)
To: lee.jones, robh+dt, mark.rutland, xuwei5, catalin.marinas,
will.deacon, lgirdwood, broonie, khilman, arnd, gregory.clement,
horms+renesas, olof, thomas.petazzoni, yamada.masahiro,
riku.voipio, treding, krzk, eric, damm+renesas, ard.biesheuvel,
linus.walleij, geert+renesas
Cc: devicetree, linux-kernel, linux-arm-kernel, hw.wangxiaoyin, Guodong Xu
This patchset adds various devices nodes for hi3660 and hikey960.
HiKey960 is one of 96boards. For details information about it, please
refer to [1].
In v4, I removed cpuidle patch
* (v3-0014-arm64-dts-hi3660-enable-idle-states.patch)
, since we are not sure yet whether the corresponding driver can get
into mainline. Sorry about the noise.
* Other patches are not changed.
In v3,
* nothing is changed for patches already exists in v2.
* added 9 more dts patches. Most of them already were reviewed with their
corresponding driver patchset. For purpose of easy integration for
platform maintainer, I copied them here, including threads [2], [3],
and [4].
* four patches, this is the first time they are sent out for review.
v3-0014-arm64-dts-hi3660-enable-idle-states.patch
v3-0019-dt-bindings-mmc-dw_mmc-k3-add-document-of-hi3660-.patch
v3-0020-arm64-dts-hi3660-add-sd-sdio-device-nodes.patch
v3-0021-arm64-dts-hi3660-hikey960-add-nodes-for-WiFi.patch
mmc driver is under review in [5].
In v2, incorporated review comments from Rob Herring <robh@kernel.org>
* uart4: max-speed should be in slave device bluetooth node
* LEDs: - bt_active triggered by 'hci0-power'
- move out of SoC level
* pinctrl: update dts to use #pinctrl-cells
* uart: add pinctrl information into uart nodes; add label strings.
* chosen: update stdout-path. serial6 is used.
* i2c: add label strings. change reg address to lower case.
* remove unnecessary status="ok"
* gpio-keys: move out of SoC level.
[1] https://github.com/96boards/documentation/tree/master/ConsumerEdition/HiKey960
[2] sp804 timer: https://www.spinics.net/lists/kernel/msg2513025.html
[3] PCIe: https://www.spinics.net/lists/kernel/msg2520677.html
[4] mfd and regulator: https://www.spinics.net/lists/arm-kernel/msg586147.html
[5] mmc: https://patchwork.kernel.org/patch/9783273/
Chen Feng (2):
arm64: dts: hi3660: Add uarts nodes
arm64: dts: hi3660: Add pl031 rtc node
Chen Jun (1):
arm64: dts: hi3660: add power key dts node
Guodong Xu (7):
dt-bindings: arm: hisilicon: add bindings for HiKey960 board
arm64: dts: hisilicon: update compatible string for hikey960
arm64: dts: hikey960: add WL1837 Bluetooth device node
arm64: dts: hikey960: add LED nodes
dt-bindings: mfd: hi6421: Add hi6421v530 compatible string
dt-bindings: mmc: dw_mmc-k3: add document of hi3660 mmc
arm64: dts: hi3660-hikey960: add nodes for WiFi
Leo Yan (1):
arm64: dts: hi3660: add sp804 timer node
Li Wei (1):
arm64: dts: hi3660: add sd/sdio device nodes
Wang Xiaoyin (4):
arm64: dts: hikey960: pinctrl: add more pinmux and pinconfig
arm64: dts: hi3660: add gpio dtsi file for Hisilicon Hi3660 SOC
arm64: dts: hi3660: add spi device nodes
arm64: dts: hikey960: add device node for pmic and regulators
Xiaowei Song (2):
dt-bindings: PCI: hisi: Add document for PCIe of Kirin SoCs
arm64: dts: hisi: add kirin pcie node
Zhangfei Gao (2):
arm64: dts: hi3660: add resources for clock and reset
arm64: dts: Add I2C nodes for Hi3660
.../bindings/arm/hisilicon/hisilicon.txt | 4 +
Documentation/devicetree/bindings/mfd/hi6421.txt | 4 +-
.../devicetree/bindings/mmc/k3-dw-mshc.txt | 1 +
.../devicetree/bindings/pci/kirin-pcie.txt | 50 ++
arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 217 +++++-
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 702 ++++++++++++++++++-
.../arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi | 778 +++++++++++++++++++--
7 files changed, 1681 insertions(+), 75 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txt
--
2.10.2
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v4 01/20] dt-bindings: arm: hisilicon: add bindings for HiKey960 board
2017-06-15 3:03 [PATCH v4 00/20] arm64: dts: hi3660: add device nodes Guodong Xu
@ 2017-06-15 3:03 ` Guodong Xu
2017-06-15 3:03 ` [PATCH v4 02/20] arm64: dts: hisilicon: update compatible string for hikey960 Guodong Xu
` (19 subsequent siblings)
20 siblings, 0 replies; 24+ messages in thread
From: Guodong Xu @ 2017-06-15 3:03 UTC (permalink / raw)
To: lee.jones, robh+dt, mark.rutland, xuwei5, catalin.marinas,
will.deacon, lgirdwood, broonie, khilman, arnd, gregory.clement,
horms+renesas, olof, thomas.petazzoni, yamada.masahiro,
riku.voipio, treding, krzk, eric, damm+renesas, ard.biesheuvel,
linus.walleij, geert+renesas
Cc: devicetree, linux-kernel, linux-arm-kernel, hw.wangxiaoyin, Guodong Xu
Add bindings for HiKey960 Board.
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index 2e73215..7111fbc8 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -4,6 +4,10 @@ Hi3660 SoC
Required root node properties:
- compatible = "hisilicon,hi3660";
+HiKey960 Board
+Required root node properties:
+ - compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
+
Hi3798cv200 SoC
Required root node properties:
- compatible = "hisilicon,hi3798cv200";
--
2.10.2
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v4 02/20] arm64: dts: hisilicon: update compatible string for hikey960
2017-06-15 3:03 [PATCH v4 00/20] arm64: dts: hi3660: add device nodes Guodong Xu
2017-06-15 3:03 ` [PATCH v4 01/20] dt-bindings: arm: hisilicon: add bindings for HiKey960 board Guodong Xu
@ 2017-06-15 3:03 ` Guodong Xu
2017-06-15 3:04 ` [PATCH v4 03/20] arm64: dts: hikey960: pinctrl: add more pinmux and pinconfig Guodong Xu
` (18 subsequent siblings)
20 siblings, 0 replies; 24+ messages in thread
From: Guodong Xu @ 2017-06-15 3:03 UTC (permalink / raw)
To: lee.jones, robh+dt, mark.rutland, xuwei5, catalin.marinas,
will.deacon, lgirdwood, broonie, khilman, arnd, gregory.clement,
horms+renesas, olof, thomas.petazzoni, yamada.masahiro,
riku.voipio, treding, krzk, eric, damm+renesas, ard.biesheuvel,
linus.walleij, geert+renesas
Cc: devicetree, linux-kernel, linux-arm-kernel, hw.wangxiaoyin,
Guodong Xu, Chen Feng
Update compatible string for hikey960. HiKey960 is a develpment board built
with SoC Hi3660.
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
Acked-by: Rob Herring <robh@kernel.org>
---
arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
index 186251f..64875a5 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
@@ -12,7 +12,7 @@
/ {
model = "HiKey960";
- compatible = "hisilicon,hi3660";
+ compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
aliases {
serial5 = &uart5; /* console UART */
--
2.10.2
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v4 03/20] arm64: dts: hikey960: pinctrl: add more pinmux and pinconfig
2017-06-15 3:03 [PATCH v4 00/20] arm64: dts: hi3660: add device nodes Guodong Xu
2017-06-15 3:03 ` [PATCH v4 01/20] dt-bindings: arm: hisilicon: add bindings for HiKey960 board Guodong Xu
2017-06-15 3:03 ` [PATCH v4 02/20] arm64: dts: hisilicon: update compatible string for hikey960 Guodong Xu
@ 2017-06-15 3:04 ` Guodong Xu
2017-06-15 3:04 ` [PATCH v4 04/20] arm64: dts: hi3660: add resources for clock and reset Guodong Xu
` (17 subsequent siblings)
20 siblings, 0 replies; 24+ messages in thread
From: Guodong Xu @ 2017-06-15 3:04 UTC (permalink / raw)
To: lee.jones, robh+dt, mark.rutland, xuwei5, catalin.marinas,
will.deacon, lgirdwood, broonie, khilman, arnd, gregory.clement,
horms+renesas, olof, thomas.petazzoni, yamada.masahiro,
riku.voipio, treding, krzk, eric, damm+renesas, ard.biesheuvel,
linus.walleij, geert+renesas
Cc: devicetree, linux-kernel, linux-arm-kernel, hw.wangxiaoyin,
Chen Jun, Guodong Xu
From: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com>
This commit adds more pinmux and pinctrl information for devices
on HiKey960, including i2c, spi, cam, uart, ufs, pcie, csi, pwr_key,
isp, sd/sdio, i2s, and usb.
Signed-off-by: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com>
Signed-off-by: Chen Jun <chenjun14@huawei.com>
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
---
.../arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi | 778 +++++++++++++++++++--
1 file changed, 715 insertions(+), 63 deletions(-)
diff --git a/arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi b/arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi
index 719c4bc..7e542d2 100644
--- a/arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi
@@ -24,6 +24,27 @@
&range 0 7 0
&range 8 116 0>;
+ pmu_pmx_func: pmu_pmx_func {
+ pinctrl-single,pins = <
+ 0x008 MUX_M1 /* PMU1_SSI */
+ 0x00c MUX_M1 /* PMU2_SSI */
+ 0x010 MUX_M1 /* PMU_CLKOUT */
+ 0x100 MUX_M1 /* PMU_HKADC_SSI */
+ >;
+ };
+
+ csi0_pwd_n_pmx_func: csi0_pwd_n_pmx_func {
+ pinctrl-single,pins = <
+ 0x044 MUX_M0 /* CSI0_PWD_N */
+ >;
+ };
+
+ csi1_pwd_n_pmx_func: csi1_pwd_n_pmx_func {
+ pinctrl-single,pins = <
+ 0x04c MUX_M0 /* CSI1_PWD_N */
+ >;
+ };
+
isp0_pmx_func: isp0_pmx_func {
pinctrl-single,pins = <
0x058 MUX_M1 /* ISP_CLK0 */
@@ -40,6 +61,12 @@
>;
};
+ pwr_key_pmx_func: pwr_key_pmx_func {
+ pinctrl-single,pins = <
+ 0x080 MUX_M0 /* GPIO_034 */
+ >;
+ };
+
i2c3_pmx_func: i2c3_pmx_func {
pinctrl-single,pins = <
0x02c MUX_M1 /* I2C3_SCL */
@@ -67,21 +94,10 @@
>;
};
- spi1_pmx_func: spi1_pmx_func {
- pinctrl-single,pins = <
- 0x034 MUX_M1 /* SPI1_CLK */
- 0x038 MUX_M1 /* SPI1_DI */
- 0x03c MUX_M1 /* SPI1_DO */
- 0x040 MUX_M1 /* SPI1_CS_N */
- >;
- };
-
uart0_pmx_func: uart0_pmx_func {
pinctrl-single,pins = <
0x0cc MUX_M2 /* UART0_RXD */
0x0d0 MUX_M2 /* UART0_TXD */
- 0x0d4 MUX_M2 /* UART0_RXD_M */
- 0x0d8 MUX_M2 /* UART0_TXD_M */
>;
};
@@ -138,6 +154,18 @@
0x0d8 MUX_M1 /* UART6_TXD */
>;
};
+
+ cam0_rst_pmx_func: cam0_rst_pmx_func {
+ pinctrl-single,pins = <
+ 0x0c8 MUX_M0 /* CAM0_RST */
+ >;
+ };
+
+ cam1_rst_pmx_func: cam1_rst_pmx_func {
+ pinctrl-single,pins = <
+ 0x124 MUX_M0 /* CAM1_RST */
+ >;
+ };
};
/* [IOMG_MMC0_000, IOMG_MMC0_005] */
@@ -174,6 +202,13 @@
/* pin base, nr pins & gpio function */
pinctrl-single,gpio-range = <&range 0 12 0>;
+ ufs_pmx_func: ufs_pmx_func {
+ pinctrl-single,pins = <
+ 0x000 MUX_M1 /* UFS_REF_CLK */
+ 0x004 MUX_M1 /* UFS_RST_N */
+ >;
+ };
+
spi3_pmx_func: spi3_pmx_func {
pinctrl-single,pins = <
0x008 MUX_M1 /* SPI3_CLK */
@@ -248,17 +283,17 @@
>;
};
- i2c2_pmx_func: i2c2_pmx_func {
+ i2c7_pmx_func: i2c7_pmx_func {
pinctrl-single,pins = <
- 0x024 MUX_M1 /* I2C2_SCL */
- 0x028 MUX_M1 /* I2C2_SDA */
+ 0x024 MUX_M3 /* I2C7_SCL */
+ 0x028 MUX_M3 /* I2C7_SDA */
>;
};
- i2c7_pmx_func: i2c7_pmx_func {
+ pcie_pmx_func: pcie_pmx_func {
pinctrl-single,pins = <
- 0x024 MUX_M3 /* I2C7_SCL */
- 0x028 MUX_M3 /* I2C7_SDA */
+ 0x084 MUX_M1 /* PCIE_CLKREQ_N */
+ 0x088 MUX_M1 /* PCIE_WAKE_N */
>;
};
@@ -271,15 +306,6 @@
>;
};
- spi4_pmx_func: spi4_pmx_func {
- pinctrl-single,pins = <
- 0x08c MUX_M4 /* SPI4_CLK */
- 0x090 MUX_M4 /* SPI4_DI */
- 0x094 MUX_M4 /* SPI4_DO */
- 0x098 MUX_M4 /* SPI4_CS0_N */
- >;
- };
-
i2s0_pmx_func: i2s0_pmx_func {
pinctrl-single,pins = <
0x034 MUX_M1 /* I2S0_DI */
@@ -290,17 +316,18 @@
};
};
- pmx5: pinmux@ff3fd800 {
+ pmx5: pinmux@e896c800 {
compatible = "pinconf-single";
- reg = <0x0 0xff3fd800 0x0 0x18>;
+ reg = <0x0 0xe896c800 0x0 0x200>;
#pinctrl-cells = <1>;
- #address-cells = <1>;
- #size-cells = <1>;
- pinctrl-single,register-width = <32>;
+ pinctrl-single,register-width = <0x20>;
- sdio_clk_cfg_func: sdio_clk_cfg_func {
+ pmu_cfg_func: pmu_cfg_func {
pinctrl-single,pins = <
- 0x000 0x0 /* SDIO_CLK */
+ 0x010 0x0 /* PMU1_SSI */
+ 0x014 0x0 /* PMU2_SSI */
+ 0x018 0x0 /* PMU_CLKOUT */
+ 0x10c 0x0 /* PMU_HKADC_SSI */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
@@ -315,18 +342,35 @@
PULL_UP
>;
pinctrl-single,drive-strength = <
- DRIVE6_32MA
- DRIVE6_MASK
+ DRIVE7_06MA DRIVE6_MASK
>;
};
- sdio_cfg_func: sdio_cfg_func {
+ i2c3_cfg_func: i2c3_cfg_func {
pinctrl-single,pins = <
- 0x004 0x0 /* SDIO_CMD */
- 0x008 0x0 /* SDIO_DATA0 */
- 0x00c 0x0 /* SDIO_DATA1 */
- 0x010 0x0 /* SDIO_DATA2 */
- 0x014 0x0 /* SDIO_DATA3 */
+ 0x038 0x0 /* I2C3_SCL */
+ 0x03c 0x0 /* I2C3_SDA */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ csi0_pwd_n_cfg_func: csi0_pwd_n_cfg_func {
+ pinctrl-single,pins = <
+ 0x050 0x0 /* CSI0_PWD_N */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
@@ -335,29 +379,64 @@
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_04MA DRIVE6_MASK
+ >;
+ };
+
+ csi1_pwd_n_cfg_func: csi1_pwd_n_cfg_func {
+ pinctrl-single,pins = <
+ 0x058 0x0 /* CSI1_PWD_N */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
- DRIVE6_19MA
- DRIVE6_MASK
+ DRIVE7_04MA DRIVE6_MASK
>;
};
- };
- pmx6: pinmux@ff37e800 {
- compatible = "pinconf-single";
- reg = <0x0 0xff37e800 0x0 0x18>;
- #pinctrl-cells = <1>;
- #address-cells = <1>;
- #size-cells = <1>;
- pinctrl-single,register-width = <32>;
+ isp0_cfg_func: isp0_cfg_func {
+ pinctrl-single,pins = <
+ 0x064 0x0 /* ISP_CLK0 */
+ 0x070 0x0 /* ISP_SCL0 */
+ 0x074 0x0 /* ISP_SDA0 */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_04MA DRIVE6_MASK>;
+ };
- sd_clk_cfg_func: sd_clk_cfg_func {
+ isp1_cfg_func: isp1_cfg_func {
pinctrl-single,pins = <
- 0x000 0x0 /* SD_CLK */
+ 0x068 0x0 /* ISP_CLK1 */
+ 0x078 0x0 /* ISP_SCL1 */
+ 0x07c 0x0 /* ISP_SDA1 */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
@@ -372,18 +451,37 @@
PULL_UP
>;
pinctrl-single,drive-strength = <
- DRIVE6_32MA
- DRIVE6_MASK
+ DRIVE7_04MA DRIVE6_MASK
>;
};
- sd_cfg_func: sd_cfg_func {
+ pwr_key_cfg_func: pwr_key_cfg_func {
pinctrl-single,pins = <
- 0x004 0x0 /* SD_CMD */
- 0x008 0x0 /* SD_DATA0 */
- 0x00c 0x0 /* SD_DATA1 */
- 0x010 0x0 /* SD_DATA2 */
- 0x014 0x0 /* SD_DATA3 */
+ 0x08c 0x0 /* GPIO_034 */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ uart1_cfg_func: uart1_cfg_func {
+ pinctrl-single,pins = <
+ 0x0b4 0x0 /* UART1_RXD */
+ 0x0b8 0x0 /* UART1_TXD */
+ 0x0bc 0x0 /* UART1_CTS_N */
+ 0x0c0 0x0 /* UART1_RTS_N */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
@@ -392,14 +490,568 @@
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ uart2_cfg_func: uart2_cfg_func {
+ pinctrl-single,pins = <
+ 0x0c8 0x0 /* UART2_CTS_N */
+ 0x0cc 0x0 /* UART2_RTS_N */
+ 0x0d0 0x0 /* UART2_TXD */
+ 0x0d4 0x0 /* UART2_RXD */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
- DRIVE6_19MA
- DRIVE6_MASK
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ uart5_cfg_func: uart5_cfg_func {
+ pinctrl-single,pins = <
+ 0x0c8 0x0 /* UART5_RXD */
+ 0x0cc 0x0 /* UART5_TXD */
+ 0x0d0 0x0 /* UART5_CTS_N */
+ 0x0d4 0x0 /* UART5_RTS_N */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ cam0_rst_cfg_func: cam0_rst_cfg_func {
+ pinctrl-single,pins = <
+ 0x0d4 0x0 /* CAM0_RST */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_04MA DRIVE6_MASK
+ >;
+ };
+
+ uart0_cfg_func: uart0_cfg_func {
+ pinctrl-single,pins = <
+ 0x0d8 0x0 /* UART0_RXD */
+ 0x0dc 0x0 /* UART0_TXD */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ uart6_cfg_func: uart6_cfg_func {
+ pinctrl-single,pins = <
+ 0x0d8 0x0 /* UART6_CTS_N */
+ 0x0dc 0x0 /* UART6_RTS_N */
+ 0x0e0 0x0 /* UART6_RXD */
+ 0x0e4 0x0 /* UART6_TXD */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ uart3_cfg_func: uart3_cfg_func {
+ pinctrl-single,pins = <
+ 0x0e8 0x0 /* UART3_CTS_N */
+ 0x0ec 0x0 /* UART3_RTS_N */
+ 0x0f0 0x0 /* UART3_RXD */
+ 0x0f4 0x0 /* UART3_TXD */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ uart4_cfg_func: uart4_cfg_func {
+ pinctrl-single,pins = <
+ 0x0f8 0x0 /* UART4_CTS_N */
+ 0x0fc 0x0 /* UART4_RTS_N */
+ 0x100 0x0 /* UART4_RXD */
+ 0x104 0x0 /* UART4_TXD */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ cam1_rst_cfg_func: cam1_rst_cfg_func {
+ pinctrl-single,pins = <
+ 0x130 0x0 /* CAM1_RST */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_04MA DRIVE6_MASK
+ >;
+ };
+ };
+
+ pmx6: pinmux@ff3b6800 {
+ compatible = "pinconf-single";
+ reg = <0x0 0xff3b6800 0x0 0x18>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <0x20>;
+
+ ufs_cfg_func: ufs_cfg_func {
+ pinctrl-single,pins = <
+ 0x000 0x0 /* UFS_REF_CLK */
+ 0x004 0x0 /* UFS_RST_N */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_08MA DRIVE6_MASK
+ >;
+ };
+
+ spi3_cfg_func: spi3_cfg_func {
+ pinctrl-single,pins = <
+ 0x008 0x0 /* SPI3_CLK */
+ 0x0 /* SPI3_DI */
+ 0x010 0x0 /* SPI3_DO */
+ 0x014 0x0 /* SPI3_CS0_N */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+ };
+
+ pmx7: pinmux@ff3fd800 {
+ compatible = "pinconf-single";
+ reg = <0x0 0xff3fd800 0x0 0x18>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <0x20>;
+
+ sdio_clk_cfg_func: sdio_clk_cfg_func {
+ pinctrl-single,pins = <
+ 0x000 0x0 /* SDIO_CLK */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE6_32MA DRIVE6_MASK
+ >;
+ };
+
+ sdio_cfg_func: sdio_cfg_func {
+ pinctrl-single,pins = <
+ 0x004 0x0 /* SDIO_CMD */
+ 0x008 0x0 /* SDIO_DATA0 */
+ 0x00c 0x0 /* SDIO_DATA1 */
+ 0x010 0x0 /* SDIO_DATA2 */
+ 0x014 0x0 /* SDIO_DATA3 */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_UP
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE6_19MA DRIVE6_MASK
+ >;
+ };
+ };
+
+ pmx8: pinmux@ff37e800 {
+ compatible = "pinconf-single";
+ reg = <0x0 0xff37e800 0x0 0x18>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <0x20>;
+
+ sd_clk_cfg_func: sd_clk_cfg_func {
+ pinctrl-single,pins = <
+ 0x000 0x0 /* SD_CLK */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_DIS
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE6_32MA
+ DRIVE6_MASK
+ >;
+ };
+
+ sd_cfg_func: sd_cfg_func {
+ pinctrl-single,pins = <
+ 0x004 0x0 /* SD_CMD */
+ 0x008 0x0 /* SD_DATA0 */
+ 0x00c 0x0 /* SD_DATA1 */
+ 0x010 0x0 /* SD_DATA2 */
+ 0x014 0x0 /* SD_DATA3 */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_UP
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE6_19MA
+ DRIVE6_MASK
+ >;
+ };
+ };
+
+ pmx9: pinmux@fff11800 {
+ compatible = "pinconf-single";
+ reg = <0x0 0xfff11800 0x0 0xbc>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <0x20>;
+
+ i2c0_cfg_func: i2c0_cfg_func {
+ pinctrl-single,pins = <
+ 0x01c 0x0 /* I2C0_SCL */
+ 0x020 0x0 /* I2C0_SDA */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_UP
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ i2c1_cfg_func: i2c1_cfg_func {
+ pinctrl-single,pins = <
+ 0x024 0x0 /* I2C1_SCL */
+ 0x028 0x0 /* I2C1_SDA */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_UP
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ i2c7_cfg_func: i2c7_cfg_func {
+ pinctrl-single,pins = <
+ 0x02c 0x0 /* I2C7_SCL */
+ 0x030 0x0 /* I2C7_SDA */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_UP
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ slimbus_cfg_func: slimbus_cfg_func {
+ pinctrl-single,pins = <
+ 0x034 0x0 /* SLIMBUS_CLK */
+ 0x038 0x0 /* SLIMBUS_DATA */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_UP
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ i2s0_cfg_func: i2s0_cfg_func {
+ pinctrl-single,pins = <
+ 0x040 0x0 /* I2S0_DI */
+ 0x044 0x0 /* I2S0_DO */
+ 0x048 0x0 /* I2S0_XCLK */
+ 0x04c 0x0 /* I2S0_XFS */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_UP
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ i2s2_cfg_func: i2s2_cfg_func {
+ pinctrl-single,pins = <
+ 0x050 0x0 /* I2S2_DI */
+ 0x054 0x0 /* I2S2_DO */
+ 0x058 0x0 /* I2S2_XCLK */
+ 0x05c 0x0 /* I2S2_XFS */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_UP
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ pcie_cfg_func: pcie_cfg_func {
+ pinctrl-single,pins = <
+ 0x094 0x0 /* PCIE_CLKREQ_N */
+ 0x098 0x0 /* PCIE_WAKE_N */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_UP
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ spi2_cfg_func: spi2_cfg_func {
+ pinctrl-single,pins = <
+ 0x09c 0x0 /* SPI2_CLK */
+ 0x0a0 0x0 /* SPI2_DI */
+ 0x0a4 0x0 /* SPI2_DO */
+ 0x0a8 0x0 /* SPI2_CS0_N */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_UP
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
+ >;
+ };
+
+ usb_cfg_func: usb_cfg_func {
+ pinctrl-single,pins = <
+ 0x0ac 0x0 /* GPIO_219 */
+ >;
+ pinctrl-single,bias-pulldown = <
+ PULL_DIS
+ PULL_DOWN
+ PULL_DIS
+ PULL_DOWN
+ >;
+ pinctrl-single,bias-pullup = <
+ PULL_UP
+ PULL_UP
+ PULL_DIS
+ PULL_UP
+ >;
+ pinctrl-single,drive-strength = <
+ DRIVE7_02MA DRIVE6_MASK
>;
};
};
--
2.10.2
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v4 04/20] arm64: dts: hi3660: add resources for clock and reset
2017-06-15 3:03 [PATCH v4 00/20] arm64: dts: hi3660: add device nodes Guodong Xu
` (2 preceding siblings ...)
2017-06-15 3:04 ` [PATCH v4 03/20] arm64: dts: hikey960: pinctrl: add more pinmux and pinconfig Guodong Xu
@ 2017-06-15 3:04 ` Guodong Xu
2017-06-15 3:04 ` [PATCH v4 05/20] arm64: dts: Add I2C nodes for Hi3660 Guodong Xu
` (16 subsequent siblings)
20 siblings, 0 replies; 24+ messages in thread
From: Guodong Xu @ 2017-06-15 3:04 UTC (permalink / raw)
To: lee.jones, robh+dt, mark.rutland, xuwei5, catalin.marinas,
will.deacon, lgirdwood, broonie, khilman, arnd, gregory.clement,
horms+renesas, olof, thomas.petazzoni, yamada.masahiro,
riku.voipio, treding, krzk, eric, damm+renesas, ard.biesheuvel,
linus.walleij, geert+renesas
Cc: devicetree, linux-kernel, linux-arm-kernel, hw.wangxiaoyin, Zhangfei Gao
From: Zhangfei Gao <zhangfei.gao@linaro.org>
Add some resource nodes for clock and reset
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
---
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 53 +++++++++++++++++++++++++++----
1 file changed, 46 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index 3983086..f55710a 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -5,6 +5,7 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/hi3660-clock.h>
/ {
compatible = "hisilicon,hi3660";
@@ -141,18 +142,56 @@
#size-cells = <2>;
ranges;
- fixed_uart5: fixed_19_2M {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <19200000>;
- clock-output-names = "fixed:uart5";
+ crg_ctrl: crg_ctrl@fff35000 {
+ compatible = "hisilicon,hi3660-crgctrl", "syscon";
+ reg = <0x0 0xfff35000 0x0 0x1000>;
+ #clock-cells = <1>;
};
- uart5: uart@fdf05000 {
+ crg_rst: crg_rst_controller {
+ compatible = "hisilicon,hi3660-reset";
+ #reset-cells = <2>;
+ hisi,rst-syscon = <&crg_ctrl>;
+ };
+
+
+ pctrl: pctrl@e8a09000 {
+ compatible = "hisilicon,hi3660-pctrl", "syscon";
+ reg = <0x0 0xe8a09000 0x0 0x2000>;
+ #clock-cells = <1>;
+ };
+
+ pmuctrl: crg_ctrl@fff34000 {
+ compatible = "hisilicon,hi3660-pmuctrl", "syscon";
+ reg = <0x0 0xfff34000 0x0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ sctrl: sctrl@fff0a000 {
+ compatible = "hisilicon,hi3660-sctrl", "syscon";
+ reg = <0x0 0xfff0a000 0x0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ iomcu: iomcu@ffd7e000 {
+ compatible = "hisilicon,hi3660-iomcu", "syscon";
+ reg = <0x0 0xffd7e000 0x0 0x1000>;
+ #clock-cells = <1>;
+
+ };
+
+ iomcu_rst: reset {
+ compatible = "hisilicon,hi3660-reset";
+ hisi,rst-syscon = <&iomcu>;
+ #reset-cells = <2>;
+ };
+
+ uart5: serial@fdf05000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xfdf05000 0x0 0x1000>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&fixed_uart5 &fixed_uart5>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>,
+ <&crg_ctrl HI3660_CLK_GATE_UART5>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
--
2.10.2
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v4 05/20] arm64: dts: Add I2C nodes for Hi3660
2017-06-15 3:03 [PATCH v4 00/20] arm64: dts: hi3660: add device nodes Guodong Xu
` (3 preceding siblings ...)
2017-06-15 3:04 ` [PATCH v4 04/20] arm64: dts: hi3660: add resources for clock and reset Guodong Xu
@ 2017-06-15 3:04 ` Guodong Xu
2017-06-15 3:04 ` [PATCH v4 06/20] arm64: dts: hi3660: add gpio dtsi file for Hisilicon Hi3660 SOC Guodong Xu
` (15 subsequent siblings)
20 siblings, 0 replies; 24+ messages in thread
From: Guodong Xu @ 2017-06-15 3:04 UTC (permalink / raw)
To: lee.jones, robh+dt, mark.rutland, xuwei5, catalin.marinas,
will.deacon, lgirdwood, broonie, khilman, arnd, gregory.clement,
horms+renesas, olof, thomas.petazzoni, yamada.masahiro,
riku.voipio, treding, krzk, eric, damm+renesas, ard.biesheuvel,
linus.walleij, geert+renesas
Cc: devicetree, linux-kernel, linux-arm-kernel, hw.wangxiaoyin,
Zhangfei Gao, Jarkko Nikula, Guodong Xu
From: Zhangfei Gao <zhangfei.gao@linaro.org>
Add I2C nodes for Hi3660-hikey960.
On HiKey960,
I2C0, I2C7 are connected to Low Speed Expansion Connector.
I2C1 is connected to ADV7535.
I2C3 is connected to USB5734.
Cc: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
---
arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 22 +++++++++
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 56 +++++++++++++++++++++++
2 files changed, 78 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
index 64875a5..1a4d6c5 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
@@ -29,6 +29,28 @@
};
};
+&i2c0 {
+ /* On Low speed expansion */
+ label = "LS-I2C0";
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+
+ adv7533: adv7533@39 {
+ status = "ok";
+ compatible = "adi,adv7533";
+ reg = <0x39>;
+ };
+};
+
+&i2c7 {
+ /* On Low speed expansion */
+ label = "LS-I2C1";
+ status = "okay";
+};
+
&uart5 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index f55710a..9abe84e 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -186,6 +186,62 @@
#reset-cells = <2>;
};
+ i2c0: i2c@ffd71000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0xffd71000 0x0 0x1000>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <400000>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>;
+ resets = <&iomcu_rst 0x20 3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@ffd72000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0xffd72000 0x0 0x1000>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <400000>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>;
+ resets = <&iomcu_rst 0x20 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@fdf0c000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0xfdf0c000 0x0 0x1000>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <400000>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>;
+ resets = <&crg_rst 0x78 7>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>;
+ status = "disabled";
+ };
+
+ i2c7: i2c@fdf0b000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0xfdf0b000 0x0 0x1000>;
+ interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <400000>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>;
+ resets = <&crg_rst 0x60 14>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>;
+ status = "disabled";
+ };
+
uart5: serial@fdf05000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xfdf05000 0x0 0x1000>;
--
2.10.2
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v4 06/20] arm64: dts: hi3660: add gpio dtsi file for Hisilicon Hi3660 SOC
2017-06-15 3:03 [PATCH v4 00/20] arm64: dts: hi3660: add device nodes Guodong Xu
` (4 preceding siblings ...)
2017-06-15 3:04 ` [PATCH v4 05/20] arm64: dts: Add I2C nodes for Hi3660 Guodong Xu
@ 2017-06-15 3:04 ` Guodong Xu
2017-06-15 3:04 ` [PATCH v4 07/20] arm64: dts: hi3660: Add uarts nodes Guodong Xu
` (14 subsequent siblings)
20 siblings, 0 replies; 24+ messages in thread
From: Guodong Xu @ 2017-06-15 3:04 UTC (permalink / raw)
To: lee.jones, robh+dt, mark.rutland, xuwei5, catalin.marinas,
will.deacon, lgirdwood, broonie, khilman, arnd, gregory.clement,
horms+renesas, olof, thomas.petazzoni, yamada.masahiro,
riku.voipio, treding, krzk, eric, damm+renesas, ard.biesheuvel,
linus.walleij, geert+renesas
Cc: devicetree, linux-kernel, linux-arm-kernel, hw.wangxiaoyin
From: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com>
This patch adds pl061 device nodes for Hi3660 SoC.
Signed-off-by: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com>
---
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 380 ++++++++++++++++++++++++++++++
1 file changed, 380 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index 9abe84e..b03be4d 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -251,5 +251,385 @@
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
+
+ gpio0: gpio@e8a0b000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a0b000 0 0x1000>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 1 0 7>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO0>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio1: gpio@e8a0c000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a0c000 0 0x1000>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 1 7 7>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO1>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio2: gpio@e8a0d000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a0d000 0 0x1000>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 14 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO2>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio3: gpio@e8a0e000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a0e000 0 0x1000>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 22 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO3>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio4: gpio@e8a0f000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a0f000 0 0x1000>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 30 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO4>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio5: gpio@e8a10000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a10000 0 0x1000>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 38 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO5>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio6: gpio@e8a11000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a11000 0 0x1000>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 46 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO6>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio7: gpio@e8a12000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a12000 0 0x1000>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 54 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO7>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio8: gpio@e8a13000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a13000 0 0x1000>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 62 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO8>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio9: gpio@e8a14000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a14000 0 0x1000>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 70 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO9>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio10: gpio@e8a15000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a15000 0 0x1000>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 78 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO10>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio11: gpio@e8a16000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a16000 0 0x1000>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 86 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO11>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio12: gpio@e8a17000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a17000 0 0x1000>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO12>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio13: gpio@e8a18000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a18000 0 0x1000>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 102 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO13>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio14: gpio@e8a19000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a19000 0 0x1000>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 110 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO14>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio15: gpio@e8a1a000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a1a000 0 0x1000>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx0 0 118 6>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO15>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio16: gpio@e8a1b000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a1b000 0 0x1000>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO16>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio17: gpio@e8a1c000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a1c000 0 0x1000>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO17>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio18: gpio@ff3b4000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xff3b4000 0 0x1000>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx2 0 0 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO18>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio19: gpio@ff3b5000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xff3b5000 0 0x1000>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx2 0 8 4>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO19>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio20: gpio@e8a1f000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a1f000 0 0x1000>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmx1 0 0 6>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO20>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio21: gpio@e8a20000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xe8a20000 0 0x1000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&pmx3 0 0 6>;
+ clocks = <&crg_ctrl HI3660_PCLK_GPIO21>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio22: gpio@fff0b000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xfff0b000 0 0x1000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /* GPIO176 */
+ gpio-ranges = <&pmx4 2 0 6>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&sctrl HI3660_PCLK_AO_GPIO0>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio23: gpio@fff0c000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xfff0c000 0 0x1000>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /* GPIO184 */
+ gpio-ranges = <&pmx4 0 6 7>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&sctrl HI3660_PCLK_AO_GPIO1>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio24: gpio@fff0d000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xfff0d000 0 0x1000>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /* GPIO192 */
+ gpio-ranges = <&pmx4 0 13 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&sctrl HI3660_PCLK_AO_GPIO2>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio25: gpio@fff0e000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xfff0e000 0 0x1000>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /* GPIO200 */
+ gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&sctrl HI3660_PCLK_AO_GPIO3>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio26: gpio@fff0f000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xfff0f000 0 0x1000>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /* GPIO208 */
+ gpio-ranges = <&pmx4 0 28 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&sctrl HI3660_PCLK_AO_GPIO4>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio27: gpio@fff10000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xfff10000 0 0x1000>;
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /* GPIO216 */
+ gpio-ranges = <&pmx4 0 36 6>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&sctrl HI3660_PCLK_AO_GPIO5>;
+ clock-names = "apb_pclk";
+ };
+
+ gpio28: gpio@fff1d000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0 0xfff1d000 0 0x1000>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&sctrl HI3660_PCLK_AO_GPIO6>;
+ clock-names = "apb_pclk";
+ };
};
};
--
2.10.2
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v4 07/20] arm64: dts: hi3660: Add uarts nodes
2017-06-15 3:03 [PATCH v4 00/20] arm64: dts: hi3660: add device nodes Guodong Xu
` (5 preceding siblings ...)
2017-06-15 3:04 ` [PATCH v4 06/20] arm64: dts: hi3660: add gpio dtsi file for Hisilicon Hi3660 SOC Guodong Xu
@ 2017-06-15 3:04 ` Guodong Xu
2017-06-15 3:04 ` [PATCH v4 08/20] arm64: dts: hikey960: add WL1837 Bluetooth device node Guodong Xu
` (13 subsequent siblings)
20 siblings, 0 replies; 24+ messages in thread
From: Guodong Xu @ 2017-06-15 3:04 UTC (permalink / raw)
To: lee.jones, robh+dt, mark.rutland, xuwei5, catalin.marinas,
will.deacon, lgirdwood, broonie, khilman, arnd, gregory.clement,
horms+renesas, olof, thomas.petazzoni, yamada.masahiro,
riku.voipio, treding, krzk, eric, damm+renesas, ard.biesheuvel,
linus.walleij, geert+renesas
Cc: devicetree, linux-kernel, linux-arm-kernel, hw.wangxiaoyin,
Chen Feng, Guodong Xu
From: Chen Feng <puck.chen@hisilicon.com>
Add nodes uart0 to uart4 and uart6 for hi3660 SoC.
Enable uart3 and uart6, disable uart5, in hikey960 board dts.
On HiKey960:
- UART6 is used as default console, and is wired out through low speed
expansion connector.
- UART3 has RTS/CTS hardware handshake, and is wired out through low
speed expansion connector.
- UART5 is not used in commercial launched boards. So disable it.
- UART4 is connected to Bluetooth, WL1837.
Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
Signed-off-by: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com>
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Reviewed-by: Zhangfei Gao <zhangfei.gao@hisilicon.com>
---
arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 20 +++++-
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 74 +++++++++++++++++++++++
2 files changed, 91 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
index 1a4d6c5..0a3f2e0 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
@@ -15,11 +15,17 @@
compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
aliases {
- serial5 = &uart5; /* console UART */
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5;
+ serial6 = &uart6;
};
chosen {
- stdout-path = "serial5:115200n8";
+ stdout-path = "serial6:115200n8";
};
memory@0 {
@@ -51,6 +57,14 @@
status = "okay";
};
-&uart5 {
+&uart3 {
+ /* On Low speed expansion */
+ label = "LS-UART0";
+ status = "okay";
+};
+
+&uart6 {
+ /* On Low speed expansion */
+ label = "LS-UART1";
status = "okay";
};
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index b03be4d..7a90c92 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -242,6 +242,66 @@
status = "disabled";
};
+ uart0: serial@fdf02000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0xfdf02000 0x0 0x1000>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>,
+ <&crg_ctrl HI3660_PCLK>;
+ clock-names = "uartclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
+ status = "disabled";
+ };
+
+ uart1: serial@fdf00000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0xfdf00000 0x0 0x1000>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>,
+ <&crg_ctrl HI3660_CLK_GATE_UART1>;
+ clock-names = "uartclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>;
+ status = "disabled";
+ };
+
+ uart2: serial@fdf03000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0xfdf03000 0x0 0x1000>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>,
+ <&crg_ctrl HI3660_PCLK>;
+ clock-names = "uartclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
+ status = "disabled";
+ };
+
+ uart3: serial@ffd74000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0xffd74000 0x0 0x1000>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3660_FACTOR_UART3>,
+ <&crg_ctrl HI3660_PCLK>;
+ clock-names = "uartclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
+ status = "disabled";
+ };
+
+ uart4: serial@fdf01000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0xfdf01000 0x0 0x1000>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>,
+ <&crg_ctrl HI3660_CLK_GATE_UART4>;
+ clock-names = "uartclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
+ status = "disabled";
+ };
+
uart5: serial@fdf05000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xfdf05000 0x0 0x1000>;
@@ -249,6 +309,20 @@
clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>,
<&crg_ctrl HI3660_CLK_GATE_UART5>;
clock-names = "uartclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>;
+ status = "disabled";
+ };
+
+ uart6: serial@fff32000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0xfff32000 0x0 0x1000>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3660_CLK_UART6>,
+ <&crg_ctrl HI3660_PCLK>;
+ clock-names = "uartclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>;
status = "disabled";
};
--
2.10.2
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v4 08/20] arm64: dts: hikey960: add WL1837 Bluetooth device node
2017-06-15 3:03 [PATCH v4 00/20] arm64: dts: hi3660: add device nodes Guodong Xu
` (6 preceding siblings ...)
2017-06-15 3:04 ` [PATCH v4 07/20] arm64: dts: hi3660: Add uarts nodes Guodong Xu
@ 2017-06-15 3:04 ` Guodong Xu
2017-06-15 3:04 ` [PATCH v4 09/20] arm64: dts: hi3660: Add pl031 rtc node Guodong Xu
` (12 subsequent siblings)
20 siblings, 0 replies; 24+ messages in thread
From: Guodong Xu @ 2017-06-15 3:04 UTC (permalink / raw)
To: lee.jones, robh+dt, mark.rutland, xuwei5, catalin.marinas,
will.deacon, lgirdwood, broonie, khilman, arnd, gregory.clement,
horms+renesas, olof, thomas.petazzoni, yamada.masahiro,
riku.voipio, treding, krzk, eric, damm+renesas, ard.biesheuvel,
linus.walleij, geert+renesas
Cc: devicetree, linux-kernel, linux-arm-kernel, hw.wangxiaoyin, Guodong Xu
This adds the serial slave device for the WL1837 Bluetooth interface.
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
---
arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
index 0a3f2e0..c25fff9 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
@@ -9,6 +9,7 @@
#include "hi3660.dtsi"
#include "hikey960-pinctrl.dtsi"
+#include <dt-bindings/gpio/gpio.h>
/ {
model = "HiKey960";
@@ -63,6 +64,16 @@
status = "okay";
};
+&uart4 {
+ status = "okay";
+
+ bluetooth {
+ compatible = "ti,wl1837-st";
+ enable-gpios = <&gpio15 6 GPIO_ACTIVE_HIGH>;
+ max-speed = <921600>;
+ };
+};
+
&uart6 {
/* On Low speed expansion */
label = "LS-UART1";
--
2.10.2
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v4 09/20] arm64: dts: hi3660: Add pl031 rtc node
2017-06-15 3:03 [PATCH v4 00/20] arm64: dts: hi3660: add device nodes Guodong Xu
` (7 preceding siblings ...)
2017-06-15 3:04 ` [PATCH v4 08/20] arm64: dts: hikey960: add WL1837 Bluetooth device node Guodong Xu
@ 2017-06-15 3:04 ` Guodong Xu
2017-06-15 3:04 ` [PATCH v4 10/20] arm64: dts: hi3660: add power key dts node Guodong Xu
` (11 subsequent siblings)
20 siblings, 0 replies; 24+ messages in thread
From: Guodong Xu @ 2017-06-15 3:04 UTC (permalink / raw)
To: lee.jones, robh+dt, mark.rutland, xuwei5, catalin.marinas,
will.deacon, lgirdwood, broonie, khilman, arnd, gregory.clement,
horms+renesas, olof, thomas.petazzoni, yamada.masahiro,
riku.voipio, treding, krzk, eric, damm+renesas, ard.biesheuvel,
linus.walleij, geert+renesas
Cc: devicetree, linux-kernel, linux-arm-kernel, hw.wangxiaoyin, Chen Feng
From: Chen Feng <puck.chen@hisilicon.com>
Add dts node to enable pl031 rtc.
Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
Acked-by: Rob Herring <robh@kernel.org>
---
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index 7a90c92..3b2a3a7 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -326,6 +326,14 @@
status = "disabled";
};
+ rtc0: rtc@fff04000 {
+ compatible = "arm,pl031", "arm,primecell";
+ reg = <0x0 0Xfff04000 0x0 0x1000>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3660_PCLK>;
+ clock-names = "apb_pclk";
+ };
+
gpio0: gpio@e8a0b000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0 0xe8a0b000 0 0x1000>;
--
2.10.2
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v4 10/20] arm64: dts: hi3660: add power key dts node
2017-06-15 3:03 [PATCH v4 00/20] arm64: dts: hi3660: add device nodes Guodong Xu
` (8 preceding siblings ...)
2017-06-15 3:04 ` [PATCH v4 09/20] arm64: dts: hi3660: Add pl031 rtc node Guodong Xu
@ 2017-06-15 3:04 ` Guodong Xu
2017-06-15 3:04 ` [PATCH v4 11/20] arm64: dts: hikey960: add LED nodes Guodong Xu
` (10 subsequent siblings)
20 siblings, 0 replies; 24+ messages in thread
From: Guodong Xu @ 2017-06-15 3:04 UTC (permalink / raw)
To: lee.jones, robh+dt, mark.rutland, xuwei5, catalin.marinas,
will.deacon, lgirdwood, broonie, khilman, arnd, gregory.clement,
horms+renesas, olof, thomas.petazzoni, yamada.masahiro,
riku.voipio, treding, krzk, eric, damm+renesas, ard.biesheuvel,
linus.walleij, geert+renesas
Cc: devicetree, linux-kernel, linux-arm-kernel, hw.wangxiaoyin,
Chen Jun, John Stultz, Guodong Xu
From: Chen Jun <chenjun14@huawei.com>
We use gpio_034 as power key on hikey960, and set gpio with pull-up
state, when key press the voltage on the gpio will come to lower, and
power key event will be reported.
Signed-off-by: Chen Jun <chenjun14@huawei.com>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
---
arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
index c25fff9..7aac35b 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
@@ -10,6 +10,8 @@
#include "hi3660.dtsi"
#include "hikey960-pinctrl.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "HiKey960";
@@ -34,6 +36,19 @@
/* rewrite this at bootloader */
reg = <0x0 0x0 0x0 0x0>;
};
+
+ keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwr_key_pmx_func &pwr_key_cfg_func>;
+
+ power {
+ wakeup-source;
+ gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
+ label = "GPIO Power";
+ linux,code = <KEY_POWER>;
+ };
+ };
};
&i2c0 {
--
2.10.2
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v4 11/20] arm64: dts: hikey960: add LED nodes
2017-06-15 3:03 [PATCH v4 00/20] arm64: dts: hi3660: add device nodes Guodong Xu
` (9 preceding siblings ...)
2017-06-15 3:04 ` [PATCH v4 10/20] arm64: dts: hi3660: add power key dts node Guodong Xu
@ 2017-06-15 3:04 ` Guodong Xu
2017-06-15 3:04 ` [PATCH v4 12/20] arm64: dts: hi3660: add spi device nodes Guodong Xu
` (9 subsequent siblings)
20 siblings, 0 replies; 24+ messages in thread
From: Guodong Xu @ 2017-06-15 3:04 UTC (permalink / raw)
To: lee.jones, robh+dt, mark.rutland, xuwei5, catalin.marinas,
will.deacon, lgirdwood, broonie, khilman, arnd, gregory.clement,
horms+renesas, olof, thomas.petazzoni, yamada.masahiro,
riku.voipio, treding, krzk, eric, damm+renesas, ard.biesheuvel,
linus.walleij, geert+renesas
Cc: devicetree, linux-kernel, linux-arm-kernel, hw.wangxiaoyin, Guodong Xu
HiKey960 has four user LEDs, and two special purpose LEDs: WiFi and BT
respectively.
All of them are implemented as GPIO.
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
---
arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 48 +++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
index 7aac35b..9ecf6c6 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
@@ -49,6 +49,54 @@
linux,code = <KEY_POWER>;
};
};
+
+ leds {
+ compatible = "gpio-leds";
+
+ user_led1 {
+ label = "user_led1";
+ /* gpio_150_user_led1 */
+ gpios = <&gpio18 6 0>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ user_led2 {
+ label = "user_led2";
+ /* gpio_151_user_led2 */
+ gpios = <&gpio18 7 0>;
+ linux,default-trigger = "mmc0";
+ };
+
+ user_led3 {
+ label = "user_led3";
+ /* gpio_189_user_led3 */
+ gpios = <&gpio23 5 0>;
+ default-state = "off";
+ };
+
+ user_led4 {
+ label = "user_led4";
+ /* gpio_190_user_led4 */
+ gpios = <&gpio23 6 0>;
+ linux,default-trigger = "cpu0";
+ };
+
+ wlan_active_led {
+ label = "wifi_active";
+ /* gpio_205_wifi_active */
+ gpios = <&gpio25 5 0>;
+ linux,default-trigger = "phy0tx";
+ default-state = "off";
+ };
+
+ bt_active_led {
+ label = "bt_active";
+ gpios = <&gpio25 7 0>;
+ /* gpio_207_user_led1 */
+ linux,default-trigger = "hci0-power";
+ default-state = "off";
+ };
+ };
};
&i2c0 {
--
2.10.2
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v4 12/20] arm64: dts: hi3660: add spi device nodes
2017-06-15 3:03 [PATCH v4 00/20] arm64: dts: hi3660: add device nodes Guodong Xu
` (10 preceding siblings ...)
2017-06-15 3:04 ` [PATCH v4 11/20] arm64: dts: hikey960: add LED nodes Guodong Xu
@ 2017-06-15 3:04 ` Guodong Xu
2017-06-15 3:04 ` [PATCH v4 13/20] arm64: dts: hi3660: add sp804 timer node Guodong Xu
` (8 subsequent siblings)
20 siblings, 0 replies; 24+ messages in thread
From: Guodong Xu @ 2017-06-15 3:04 UTC (permalink / raw)
To: lee.jones, robh+dt, mark.rutland, xuwei5, catalin.marinas,
will.deacon, lgirdwood, broonie, khilman, arnd, gregory.clement,
horms+renesas, olof, thomas.petazzoni, yamada.masahiro,
riku.voipio, treding, krzk, eric, damm+renesas, ard.biesheuvel,
linus.walleij, geert+renesas
Cc: devicetree, linux-kernel, linux-arm-kernel, hw.wangxiaoyin, Guodong Xu
From: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com>
Add spi2 and spi3 device nodes for hi3660, and enable them for hikey960.
On HiKey960:
- SPI2 is wired out through low speed expansion connector.
- SPI3 is wired out through high speed expansion connector.
Signed-off-by: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com>
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
---
arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 12 +++++++++
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 30 +++++++++++++++++++++++
2 files changed, 42 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
index 9ecf6c6..ca448f0 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
@@ -142,3 +142,15 @@
label = "LS-UART1";
status = "okay";
};
+
+&spi2 {
+ /* On Low speed expansion */
+ label = "LS-SPI0";
+ status = "okay";
+};
+
+&spi3 {
+ /* On High speed expansion */
+ label = "HS-SPI1";
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index 3b2a3a7..a6b91f1 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -713,5 +713,35 @@
clocks = <&sctrl HI3660_PCLK_AO_GPIO6>;
clock-names = "apb_pclk";
};
+
+ spi2: spi@ffd68000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x0 0xffd68000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>;
+ clock-names = "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_pmx_func>;
+ num-cs = <1>;
+ cs-gpios = <&gpio27 2 0>;
+ status = "disabled";
+ };
+
+ spi3: spi@ff3b3000 {
+ compatible = "arm,pl022", "arm,primecell";
+ reg = <0x0 0xff3b3000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>;
+ clock-names = "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi3_pmx_func>;
+ num-cs = <1>;
+ cs-gpios = <&gpio18 5 0>;
+ status = "disabled";
+ };
};
};
--
2.10.2
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v4 13/20] arm64: dts: hi3660: add sp804 timer node
2017-06-15 3:03 [PATCH v4 00/20] arm64: dts: hi3660: add device nodes Guodong Xu
` (11 preceding siblings ...)
2017-06-15 3:04 ` [PATCH v4 12/20] arm64: dts: hi3660: add spi device nodes Guodong Xu
@ 2017-06-15 3:04 ` Guodong Xu
2017-06-15 3:04 ` [PATCH v4 14/20] dt-bindings: PCI: hisi: Add document for PCIe of Kirin SoCs Guodong Xu
` (7 subsequent siblings)
20 siblings, 0 replies; 24+ messages in thread
From: Guodong Xu @ 2017-06-15 3:04 UTC (permalink / raw)
To: lee.jones, robh+dt, mark.rutland, xuwei5, catalin.marinas,
will.deacon, lgirdwood, broonie, khilman, arnd, gregory.clement,
horms+renesas, olof, thomas.petazzoni, yamada.masahiro,
riku.voipio, treding, krzk, eric, damm+renesas, ard.biesheuvel,
linus.walleij, geert+renesas
Cc: devicetree, linux-kernel, linux-arm-kernel, hw.wangxiaoyin, Leo Yan
From: Leo Yan <leo.yan@linaro.org>
The Hi3660 SoC comes with the sp804 timer in addition to the
architecture timers. These ones are shutdown when reaching a deep idle
states and a backup timer is needed. The sp804 belongs to another power
domain and can fulfill the purpose of replacing temporarily an
architecture timer when the CPU is idle.
Describe it in the device tree, so it can be enabled at boot time.
Suggested-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
---
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index a6b91f1..e138973 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -186,6 +186,17 @@
#reset-cells = <2>;
};
+ dual_timer0: timer@fff14000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x0 0xfff14000 0x0 0x1000>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3660_OSC32K>,
+ <&crg_ctrl HI3660_OSC32K>,
+ <&crg_ctrl HI3660_OSC32K>;
+ clock-names = "timer1", "timer2", "apb_pclk";
+ };
+
i2c0: i2c@ffd71000 {
compatible = "snps,designware-i2c";
reg = <0x0 0xffd71000 0x0 0x1000>;
--
2.10.2
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v4 14/20] dt-bindings: PCI: hisi: Add document for PCIe of Kirin SoCs
2017-06-15 3:03 [PATCH v4 00/20] arm64: dts: hi3660: add device nodes Guodong Xu
` (12 preceding siblings ...)
2017-06-15 3:04 ` [PATCH v4 13/20] arm64: dts: hi3660: add sp804 timer node Guodong Xu
@ 2017-06-15 3:04 ` Guodong Xu
2017-06-15 3:04 ` [PATCH v4 15/20] arm64: dts: hisi: add kirin pcie node Guodong Xu
` (6 subsequent siblings)
20 siblings, 0 replies; 24+ messages in thread
From: Guodong Xu @ 2017-06-15 3:04 UTC (permalink / raw)
To: lee.jones, robh+dt, mark.rutland, xuwei5, catalin.marinas,
will.deacon, lgirdwood, broonie, khilman, arnd, gregory.clement,
horms+renesas, olof, thomas.petazzoni, yamada.masahiro,
riku.voipio, treding, krzk, eric, damm+renesas, ard.biesheuvel,
linus.walleij, geert+renesas
Cc: devicetree, linux-kernel, linux-arm-kernel, hw.wangxiaoyin, Xiaowei Song
From: Xiaowei Song <songxiaowei@hisilicon.com>
This patch adds document for PCIe of Kirin SoC series.
Signed-off-by: Xiaowei Song <songxiaowei@hisilicon.com>
Acked-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/pci/kirin-pcie.txt | 50 ++++++++++++++++++++++
1 file changed, 50 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txt
diff --git a/Documentation/devicetree/bindings/pci/kirin-pcie.txt b/Documentation/devicetree/bindings/pci/kirin-pcie.txt
new file mode 100644
index 0000000..68ffa0f
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/kirin-pcie.txt
@@ -0,0 +1,50 @@
+HiSilicon Kirin SoCs PCIe host DT description
+
+Kirin PCIe host controller is based on Designware PCI core.
+It shares common functions with PCIe Designware core driver
+and inherits common properties defined in
+Documentation/devicetree/bindings/pci/designware-pci.txt.
+
+Additional properties are described here:
+
+Required properties
+- compatible:
+ "hisilicon,kirin960-pcie" for PCIe of Kirin960 SoC
+- reg: Should contain rc_dbi, apb, phy, config registers location and length.
+- reg-names: Must include the following entries:
+ "dbi": controller configuration registers;
+ "apb": apb Ctrl register defined by Kirin;
+ "phy": apb PHY register defined by Kirin;
+ "config": PCIe configuration space registers.
+- reset-gpios: The gpio to generate PCIe perst assert and deassert signal.
+
+Optional properties:
+
+Example based on kirin960:
+
+ pcie@f4000000 {
+ compatible = "hisilicon,kirin-pcie";
+ reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>,
+ <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF4000000 0 0x2000>;
+ reg-names = "dbi","apb","phy", "config";
+ bus-range = <0x0 0x1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x02000000 0x0 0x00000000 0x0 0xf5000000 0x0 0x2000000>;
+ num-lanes = <1>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <0x0 0 0 1 &gic 0 0 0 282 4>,
+ <0x0 0 0 2 &gic 0 0 0 283 4>,
+ <0x0 0 0 3 &gic 0 0 0 284 4>,
+ <0x0 0 0 4 &gic 0 0 0 285 4>;
+ clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
+ <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
+ <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
+ <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
+ <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
+ clock-names = "pcie_phy_ref", "pcie_aux",
+ "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk";
+ reset-gpios = <&gpio11 1 0 >;
+ };
--
2.10.2
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v4 15/20] arm64: dts: hisi: add kirin pcie node
2017-06-15 3:03 [PATCH v4 00/20] arm64: dts: hi3660: add device nodes Guodong Xu
` (13 preceding siblings ...)
2017-06-15 3:04 ` [PATCH v4 14/20] dt-bindings: PCI: hisi: Add document for PCIe of Kirin SoCs Guodong Xu
@ 2017-06-15 3:04 ` Guodong Xu
2017-06-16 14:13 ` [PATCH v5 " Guodong Xu
2017-06-15 3:04 ` [PATCH v4 16/20] dt-bindings: mfd: hi6421: Add hi6421v530 compatible string Guodong Xu
` (5 subsequent siblings)
20 siblings, 1 reply; 24+ messages in thread
From: Guodong Xu @ 2017-06-15 3:04 UTC (permalink / raw)
To: lee.jones, robh+dt, mark.rutland, xuwei5, catalin.marinas,
will.deacon, lgirdwood, broonie, khilman, arnd, gregory.clement,
horms+renesas, olof, thomas.petazzoni, yamada.masahiro,
riku.voipio, treding, krzk, eric, damm+renesas, ard.biesheuvel,
linus.walleij, geert+renesas
Cc: devicetree, linux-kernel, linux-arm-kernel, hw.wangxiaoyin,
Xiaowei Song, Guodong Xu
From: Xiaowei Song <songxiaowei@hisilicon.com>
Add PCIe node for hi3660, and add binding documentation.
Cc: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Xiaowei Song <songxiaowei@hisilicon.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
---
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 32 +++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index e138973..529cf08 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -754,5 +754,37 @@
cs-gpios = <&gpio18 5 0>;
status = "disabled";
};
+
+ pcie@f4000000 {
+ compatible = "hisilicon,kirin960-pcie";
+ reg = <0x0 0xf4000000 0x0 0x1000>,
+ <0x0 0xff3fe000 0x0 0x1000>,
+ <0x0 0xf3f20000 0x0 0x40000>,
+ <0x0 0xf5000000 0x0 0x2000>;
+ reg-names = "dbi", "apb", "phy", "config";
+ bus-range = <0x0 0x1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x02000000 0x0 0x00000000 0x0
+ 0xf6000000 0x0 0x2000000>;
+ num-lanes = <1>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <0x0 0 0 1 &gic 0 0 0 282 4>,
+ <0x0 0 0 2 &gic 0 0 0 283 4>,
+ <0x0 0 0 3 &gic 0 0 0 284 4>,
+ <0x0 0 0 4 &gic 0 0 0 285 4>;
+ clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
+ <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
+ <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
+ <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
+ <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
+ clock-names = "pcie_phy_ref", "pcie_aux",
+ "pcie_apb_phy", "pcie_apb_sys",
+ "pcie_aclk";
+ reset-gpios = <&gpio11 1 0 >;
+ status = "ok";
+ };
};
};
--
2.10.2
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v4 16/20] dt-bindings: mfd: hi6421: Add hi6421v530 compatible string
2017-06-15 3:03 [PATCH v4 00/20] arm64: dts: hi3660: add device nodes Guodong Xu
` (14 preceding siblings ...)
2017-06-15 3:04 ` [PATCH v4 15/20] arm64: dts: hisi: add kirin pcie node Guodong Xu
@ 2017-06-15 3:04 ` Guodong Xu
2017-06-15 3:04 ` [PATCH v4 17/20] arm64: dts: hikey960: add device node for pmic and regulators Guodong Xu
` (4 subsequent siblings)
20 siblings, 0 replies; 24+ messages in thread
From: Guodong Xu @ 2017-06-15 3:04 UTC (permalink / raw)
To: lee.jones, robh+dt, mark.rutland, xuwei5, catalin.marinas,
will.deacon, lgirdwood, broonie, khilman, arnd, gregory.clement,
horms+renesas, olof, thomas.petazzoni, yamada.masahiro,
riku.voipio, treding, krzk, eric, damm+renesas, ard.biesheuvel,
linus.walleij, geert+renesas
Cc: devicetree, linux-kernel, linux-arm-kernel, hw.wangxiaoyin, Guodong Xu
Add compatible string for HiSilicon Hi6421v530 PMIC.
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Acked-for-mfd-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
---
Documentation/devicetree/bindings/mfd/hi6421.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mfd/hi6421.txt b/Documentation/devicetree/bindings/mfd/hi6421.txt
index 0d5a446..22da96d 100644
--- a/Documentation/devicetree/bindings/mfd/hi6421.txt
+++ b/Documentation/devicetree/bindings/mfd/hi6421.txt
@@ -1,7 +1,9 @@
* HI6421 Multi-Functional Device (MFD), by HiSilicon Ltd.
Required parent device properties:
-- compatible : contains "hisilicon,hi6421-pmic";
+- compatible : One of the following chip-specific strings:
+ "hisilicon,hi6421-pmic";
+ "hisilicon,hi6421v530-pmic";
- reg : register range space of hi6421;
Supported Hi6421 sub-devices include:
--
2.10.2
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v4 17/20] arm64: dts: hikey960: add device node for pmic and regulators
2017-06-15 3:03 [PATCH v4 00/20] arm64: dts: hi3660: add device nodes Guodong Xu
` (15 preceding siblings ...)
2017-06-15 3:04 ` [PATCH v4 16/20] dt-bindings: mfd: hi6421: Add hi6421v530 compatible string Guodong Xu
@ 2017-06-15 3:04 ` Guodong Xu
2017-06-15 3:04 ` [PATCH v4 18/20] dt-bindings: mmc: dw_mmc-k3: add document of hi3660 mmc Guodong Xu
` (3 subsequent siblings)
20 siblings, 0 replies; 24+ messages in thread
From: Guodong Xu @ 2017-06-15 3:04 UTC (permalink / raw)
To: lee.jones, robh+dt, mark.rutland, xuwei5, catalin.marinas,
will.deacon, lgirdwood, broonie, khilman, arnd, gregory.clement,
horms+renesas, olof, thomas.petazzoni, yamada.masahiro,
riku.voipio, treding, krzk, eric, damm+renesas, ard.biesheuvel,
linus.walleij, geert+renesas
Cc: devicetree, linux-kernel, linux-arm-kernel, hw.wangxiaoyin, Guodong Xu
From: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com>
add device node for hi6421 pmic core and hi6421v530
voltage regulator,include LDO(1,3,9,11,15,16)
Signed-off-by: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com>
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
---
arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 46 +++++++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
index ca448f0..e579333 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
@@ -97,6 +97,52 @@
default-state = "off";
};
};
+
+ pmic: pmic@fff34000 {
+ compatible = "hisilicon,hi6421v530-pmic";
+ reg = <0x0 0xfff34000 0x0 0x1000>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ regulators {
+ ldo3: LDO3 { /* HDMI */
+ regulator-name = "VOUT3_1V85";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2200000>;
+ regulator-enable-ramp-delay = <120>;
+ };
+
+ ldo9: LDO9 { /* SDCARD I/O */
+ regulator-name = "VOUT9_1V8_2V95";
+ regulator-min-microvolt = <1750000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <240>;
+ };
+
+ ldo11: LDO11 { /* Low Speed Connector */
+ regulator-name = "VOUT11_1V8_2V95";
+ regulator-min-microvolt = <1750000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-enable-ramp-delay = <240>;
+ };
+
+ ldo15: LDO15 { /* UFS VCC */
+ regulator-name = "VOUT15_3V0";
+ regulator-min-microvolt = <1750000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-enable-ramp-delay = <120>;
+ };
+
+ ldo16: LDO16 { /* SD VDD */
+ regulator-name = "VOUT16_2V95";
+ regulator-min-microvolt = <1750000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-enable-ramp-delay = <360>;
+ };
+ };
+ };
};
&i2c0 {
--
2.10.2
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v4 18/20] dt-bindings: mmc: dw_mmc-k3: add document of hi3660 mmc
2017-06-15 3:03 [PATCH v4 00/20] arm64: dts: hi3660: add device nodes Guodong Xu
` (16 preceding siblings ...)
2017-06-15 3:04 ` [PATCH v4 17/20] arm64: dts: hikey960: add device node for pmic and regulators Guodong Xu
@ 2017-06-15 3:04 ` Guodong Xu
2017-06-15 3:04 ` [PATCH v4 19/20] arm64: dts: hi3660: add sd/sdio device nodes Guodong Xu
` (2 subsequent siblings)
20 siblings, 0 replies; 24+ messages in thread
From: Guodong Xu @ 2017-06-15 3:04 UTC (permalink / raw)
To: lee.jones, robh+dt, mark.rutland, xuwei5, catalin.marinas,
will.deacon, lgirdwood, broonie, khilman, arnd, gregory.clement,
horms+renesas, olof, thomas.petazzoni, yamada.masahiro,
riku.voipio, treding, krzk, eric, damm+renesas, ard.biesheuvel,
linus.walleij, geert+renesas
Cc: devicetree, linux-kernel, linux-arm-kernel, hw.wangxiaoyin,
Guodong Xu, Li Wei
Add bindings for hi3660 mmc support
Signed-off-by: Li Wei <liwei213@huawei.com>
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
---
Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt
index df37058..8af1afc 100644
--- a/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/k3-dw-mshc.txt
@@ -12,6 +12,7 @@ extensions to the Synopsys Designware Mobile Storage Host Controller.
Required Properties:
* compatible: should be one of the following.
+ - "hisilicon,hi3660-dw-mshc": for controllers with hi3660 specific extensions.
- "hisilicon,hi4511-dw-mshc": for controllers with hi4511 specific extensions.
- "hisilicon,hi6220-dw-mshc": for controllers with hi6220 specific extensions.
--
2.10.2
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v4 19/20] arm64: dts: hi3660: add sd/sdio device nodes
2017-06-15 3:03 [PATCH v4 00/20] arm64: dts: hi3660: add device nodes Guodong Xu
` (17 preceding siblings ...)
2017-06-15 3:04 ` [PATCH v4 18/20] dt-bindings: mmc: dw_mmc-k3: add document of hi3660 mmc Guodong Xu
@ 2017-06-15 3:04 ` Guodong Xu
2017-06-15 3:04 ` [PATCH v4 20/20] arm64: dts: hi3660-hikey960: add nodes for WiFi Guodong Xu
2017-06-15 19:49 ` [PATCH v4 00/20] arm64: dts: hi3660: add device nodes Wei Xu
20 siblings, 0 replies; 24+ messages in thread
From: Guodong Xu @ 2017-06-15 3:04 UTC (permalink / raw)
To: lee.jones, robh+dt, mark.rutland, xuwei5, catalin.marinas,
will.deacon, lgirdwood, broonie, khilman, arnd, gregory.clement,
horms+renesas, olof, thomas.petazzoni, yamada.masahiro,
riku.voipio, treding, krzk, eric, damm+renesas, ard.biesheuvel,
linus.walleij, geert+renesas
Cc: devicetree, linux-kernel, linux-arm-kernel, hw.wangxiaoyin,
Li Wei, Chen Jun
From: Li Wei <liwei213@huawei.com>
Add sd/sdio device nodes for hi3660 soc
Signed-off-by: Li Wei <liwei213@huawei.com>
Signed-off-by: Chen Jun <chenjun14@huawei.com>
---
arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 8 ++++
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 58 +++++++++++++++++++++++
2 files changed, 66 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
index e579333..cec0b60 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
@@ -18,6 +18,8 @@
compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
aliases {
+ mshc1 = &dwmmc1;
+ mshc2 = &dwmmc2;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
@@ -200,3 +202,9 @@
label = "HS-SPI1";
status = "okay";
};
+
+&dwmmc1 {
+ vmmc-supply = <&ldo16>;
+ vqmmc-supply = <&ldo9>;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index 529cf08..f7ff593 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -786,5 +786,63 @@
reset-gpios = <&gpio11 1 0 >;
status = "ok";
};
+
+ /* SD */
+ dwmmc1: dwmmc1@ff37f000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cd-inverted;
+ compatible = "hisilicon,hi3660-dw-mshc";
+ num-slots = <1>;
+ bus-width = <0x4>;
+ disable-wp;
+ cap-sd-highspeed;
+ supports-highspeed;
+ card-detect-delay = <200>;
+ reg = <0x0 0xff37f000 0x0 0x1000>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_SD>,
+ <&crg_ctrl HI3660_HCLK_GATE_SD>;
+ clock-names = "ciu", "biu";
+ clock-frequency = <3200000>;
+ resets = <&crg_rst 0x94 18>;
+ cd-gpios = <&gpio25 3 0>;
+ hisilicon,peripheral-syscon = <&sctrl>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd_pmx_func
+ &sd_clk_cfg_func
+ &sd_cfg_func>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ status = "disabled";
+
+ slot@0 {
+ reg = <0x0>;
+ bus-width = <4>;
+ disable-wp;
+ };
+ };
+
+ /* SDIO */
+ dwmmc2: dwmmc2@ff3ff000 {
+ compatible = "hisilicon,hi3660-dw-mshc";
+ reg = <0x0 0xff3ff000 0x0 0x1000>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ num-slots = <1>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_SDIO0>,
+ <&crg_ctrl HI3660_HCLK_GATE_SDIO0>;
+ clock-names = "ciu", "biu";
+ resets = <&crg_rst 0x94 20>;
+ card-detect-delay = <200>;
+ supports-highspeed;
+ keep-power-in-suspend;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio_pmx_func
+ &sdio_clk_cfg_func
+ &sdio_cfg_func>;
+ status = "disabled";
+ };
};
};
--
2.10.2
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH v4 20/20] arm64: dts: hi3660-hikey960: add nodes for WiFi
2017-06-15 3:03 [PATCH v4 00/20] arm64: dts: hi3660: add device nodes Guodong Xu
` (18 preceding siblings ...)
2017-06-15 3:04 ` [PATCH v4 19/20] arm64: dts: hi3660: add sd/sdio device nodes Guodong Xu
@ 2017-06-15 3:04 ` Guodong Xu
2017-06-15 19:49 ` [PATCH v4 00/20] arm64: dts: hi3660: add device nodes Wei Xu
20 siblings, 0 replies; 24+ messages in thread
From: Guodong Xu @ 2017-06-15 3:04 UTC (permalink / raw)
To: lee.jones, robh+dt, mark.rutland, xuwei5, catalin.marinas,
will.deacon, lgirdwood, broonie, khilman, arnd, gregory.clement,
horms+renesas, olof, thomas.petazzoni, yamada.masahiro,
riku.voipio, treding, krzk, eric, damm+renesas, ard.biesheuvel,
linus.walleij, geert+renesas
Cc: devicetree, linux-kernel, linux-arm-kernel, hw.wangxiaoyin, Guodong Xu
Add nodes for WiFi. HiKey960 is using TI WL1837MOD module.
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
---
arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 33 +++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
index cec0b60..6609b0f 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
@@ -145,6 +145,20 @@
};
};
};
+
+ wlan_en: wlan-en-1-8v {
+ compatible = "regulator-fixed";
+ regulator-name = "wlan-en-regulator";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ /* GPIO_051_WIFI_EN */
+ gpio = <&gpio6 3 0>;
+
+ /* WLAN card specific delay */
+ startup-delay-us = <70000>;
+ enable-active-high;
+ };
};
&i2c0 {
@@ -208,3 +222,22 @@
vqmmc-supply = <&ldo9>;
status = "okay";
};
+
+&dwmmc2 { /* WIFI */
+ broken-cd;
+ /* WL_EN */
+ vmmc-supply = <&wlan_en>;
+ ti,non-removable;
+ non-removable;
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ status = "ok";
+
+ wlcore: wlcore@2 {
+ compatible = "ti,wl1837";
+ reg = <2>; /* sdio func num */
+ /* WL_IRQ, GPIO_179_WL_WAKEUP_AP */
+ interrupt-parent = <&gpio22>;
+ interrupts = <3 IRQ_TYPE_EDGE_RISING>;
+ };
+};
--
2.10.2
^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH v4 00/20] arm64: dts: hi3660: add device nodes
2017-06-15 3:03 [PATCH v4 00/20] arm64: dts: hi3660: add device nodes Guodong Xu
` (19 preceding siblings ...)
2017-06-15 3:04 ` [PATCH v4 20/20] arm64: dts: hi3660-hikey960: add nodes for WiFi Guodong Xu
@ 2017-06-15 19:49 ` Wei Xu
20 siblings, 0 replies; 24+ messages in thread
From: Wei Xu @ 2017-06-15 19:49 UTC (permalink / raw)
To: Guodong Xu, lee.jones, robh+dt, mark.rutland, catalin.marinas,
will.deacon, lgirdwood, broonie, khilman, arnd, gregory.clement,
horms+renesas, olof, thomas.petazzoni, yamada.masahiro,
riku.voipio, treding, krzk, eric, damm+renesas, ard.biesheuvel,
linus.walleij, geert+renesas
Cc: devicetree, linux-kernel, linux-arm-kernel, hw.wangxiaoyin
Hi Guodong,
On 2017/6/15 4:03, Guodong Xu wrote:
> This patchset adds various devices nodes for hi3660 and hikey960.
>
> HiKey960 is one of 96boards. For details information about it, please
> refer to [1].
>
> In v4, I removed cpuidle patch
> * (v3-0014-arm64-dts-hi3660-enable-idle-states.patch)
> , since we are not sure yet whether the corresponding driver can get
> into mainline. Sorry about the noise.
> * Other patches are not changed.
>
> In v3,
> * nothing is changed for patches already exists in v2.
> * added 9 more dts patches. Most of them already were reviewed with their
> corresponding driver patchset. For purpose of easy integration for
> platform maintainer, I copied them here, including threads [2], [3],
> and [4].
> * four patches, this is the first time they are sent out for review.
> v3-0014-arm64-dts-hi3660-enable-idle-states.patch
> v3-0019-dt-bindings-mmc-dw_mmc-k3-add-document-of-hi3660-.patch
> v3-0020-arm64-dts-hi3660-add-sd-sdio-device-nodes.patch
> v3-0021-arm64-dts-hi3660-hikey960-add-nodes-for-WiFi.patch
> mmc driver is under review in [5].
>
> In v2, incorporated review comments from Rob Herring <robh@kernel.org>
> * uart4: max-speed should be in slave device bluetooth node
> * LEDs: - bt_active triggered by 'hci0-power'
> - move out of SoC level
> * pinctrl: update dts to use #pinctrl-cells
> * uart: add pinctrl information into uart nodes; add label strings.
> * chosen: update stdout-path. serial6 is used.
> * i2c: add label strings. change reg address to lower case.
> * remove unnecessary status="ok"
> * gpio-keys: move out of SoC level.
>
> [1] https://github.com/96boards/documentation/tree/master/ConsumerEdition/HiKey960
> [2] sp804 timer: https://www.spinics.net/lists/kernel/msg2513025.html
> [3] PCIe: https://www.spinics.net/lists/kernel/msg2520677.html
> [4] mfd and regulator: https://www.spinics.net/lists/arm-kernel/msg586147.html
> [5] mmc: https://patchwork.kernel.org/patch/9783273/
>
> Chen Feng (2):
> arm64: dts: hi3660: Add uarts nodes
> arm64: dts: hi3660: Add pl031 rtc node
>
> Chen Jun (1):
> arm64: dts: hi3660: add power key dts node
>
> Guodong Xu (7):
> dt-bindings: arm: hisilicon: add bindings for HiKey960 board
> arm64: dts: hisilicon: update compatible string for hikey960
> arm64: dts: hikey960: add WL1837 Bluetooth device node
> arm64: dts: hikey960: add LED nodes
> dt-bindings: mfd: hi6421: Add hi6421v530 compatible string
> dt-bindings: mmc: dw_mmc-k3: add document of hi3660 mmc
> arm64: dts: hi3660-hikey960: add nodes for WiFi
>
> Leo Yan (1):
> arm64: dts: hi3660: add sp804 timer node
>
> Li Wei (1):
> arm64: dts: hi3660: add sd/sdio device nodes
>
> Wang Xiaoyin (4):
> arm64: dts: hikey960: pinctrl: add more pinmux and pinconfig
> arm64: dts: hi3660: add gpio dtsi file for Hisilicon Hi3660 SOC
> arm64: dts: hi3660: add spi device nodes
> arm64: dts: hikey960: add device node for pmic and regulators
>
> Xiaowei Song (2):
> dt-bindings: PCI: hisi: Add document for PCIe of Kirin SoCs
> arm64: dts: hisi: add kirin pcie node
>
> Zhangfei Gao (2):
> arm64: dts: hi3660: add resources for clock and reset
> arm64: dts: Add I2C nodes for Hi3660
>
> .../bindings/arm/hisilicon/hisilicon.txt | 4 +
> Documentation/devicetree/bindings/mfd/hi6421.txt | 4 +-
> .../devicetree/bindings/mmc/k3-dw-mshc.txt | 1 +
> .../devicetree/bindings/pci/kirin-pcie.txt | 50 ++
> arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 217 +++++-
> arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 702 ++++++++++++++++++-
> .../arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi | 778 +++++++++++++++++++--
> 7 files changed, 1681 insertions(+), 75 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txt
>
Series applied to hisilicon arm64 dt tree.
Thanks!
BR,
Wei
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v5 15/20] arm64: dts: hisi: add kirin pcie node
2017-06-15 3:04 ` [PATCH v4 15/20] arm64: dts: hisi: add kirin pcie node Guodong Xu
@ 2017-06-16 14:13 ` Guodong Xu
2017-06-16 14:43 ` Wei Xu
0 siblings, 1 reply; 24+ messages in thread
From: Guodong Xu @ 2017-06-16 14:13 UTC (permalink / raw)
To: robh+dt, mark.rutland, lee.jones, ulf.hansson, bhelgaas, xuwei5,
catalin.marinas, will.deacon, wangkefeng.wang, arnd,
xuejiancheng, puck.chen
Cc: zhangfei.gao, devicetree, linux-kernel, linux-arm-kernel,
linux-mmc, linux-pci, Xiaowei Song, Guodong Xu
From: Xiaowei Song <songxiaowei@hisilicon.com>
Add PCIe node for hi3660
Cc: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Xiaowei Song <songxiaowei@hisilicon.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Changes in v5:
* fix interrupt-map, to conform to gic's #address-cells = <0>
* remove redundant status = "ok"
---
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 36 +++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index e138973..8183d71 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -754,5 +754,41 @@
cs-gpios = <&gpio18 5 0>;
status = "disabled";
};
+
+ pcie@f4000000 {
+ compatible = "hisilicon,kirin960-pcie";
+ reg = <0x0 0xf4000000 0x0 0x1000>,
+ <0x0 0xff3fe000 0x0 0x1000>,
+ <0x0 0xf3f20000 0x0 0x40000>,
+ <0x0 0xf5000000 0x0 0x2000>;
+ reg-names = "dbi", "apb", "phy", "config";
+ bus-range = <0x0 0x1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x02000000 0x0 0x00000000
+ 0x0 0xf6000000
+ 0x0 0x02000000>;
+ num-lanes = <1>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <0x0 0 0 1
+ &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0 0 0 2
+ &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0 0 0 3
+ &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0 0 0 4
+ &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
+ <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
+ <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
+ <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
+ <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
+ clock-names = "pcie_phy_ref", "pcie_aux",
+ "pcie_apb_phy", "pcie_apb_sys",
+ "pcie_aclk";
+ reset-gpios = <&gpio11 1 0 >;
+ };
};
};
--
2.10.2
^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH v5 15/20] arm64: dts: hisi: add kirin pcie node
2017-06-16 14:13 ` [PATCH v5 " Guodong Xu
@ 2017-06-16 14:43 ` Wei Xu
0 siblings, 0 replies; 24+ messages in thread
From: Wei Xu @ 2017-06-16 14:43 UTC (permalink / raw)
To: Guodong Xu, robh+dt, mark.rutland, lee.jones, ulf.hansson,
bhelgaas, catalin.marinas, will.deacon, wangkefeng.wang, arnd,
xuejiancheng, puck.chen
Cc: zhangfei.gao, devicetree, linux-kernel, linux-arm-kernel,
linux-mmc, linux-pci, Xiaowei Song
Hi Guodong,
On 2017/6/16 15:13, Guodong Xu wrote:
> From: Xiaowei Song <songxiaowei@hisilicon.com>
>
> Add PCIe node for hi3660
>
> Cc: Guodong Xu <guodong.xu@linaro.org>
> Signed-off-by: Xiaowei Song <songxiaowei@hisilicon.com>
> Acked-by: Arnd Bergmann <arnd@arndb.de>
>
> Changes in v5:
> * fix interrupt-map, to conform to gic's #address-cells = <0>
> * remove redundant status = "ok"
> ---
Thanks!
Applied v5 and dropped the v4 in the hisilicon arm64 dt tree.
BR,
Wei
> arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 36 +++++++++++++++++++++++++++++++
> 1 file changed, 36 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> index e138973..8183d71 100644
> --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> @@ -754,5 +754,41 @@
> cs-gpios = <&gpio18 5 0>;
> status = "disabled";
> };
> +
> + pcie@f4000000 {
> + compatible = "hisilicon,kirin960-pcie";
> + reg = <0x0 0xf4000000 0x0 0x1000>,
> + <0x0 0xff3fe000 0x0 0x1000>,
> + <0x0 0xf3f20000 0x0 0x40000>,
> + <0x0 0xf5000000 0x0 0x2000>;
> + reg-names = "dbi", "apb", "phy", "config";
> + bus-range = <0x0 0x1>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + ranges = <0x02000000 0x0 0x00000000
> + 0x0 0xf6000000
> + 0x0 0x02000000>;
> + num-lanes = <1>;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0xf800 0 0 7>;
> + interrupt-map = <0x0 0 0 1
> + &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
> + <0x0 0 0 2
> + &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
> + <0x0 0 0 3
> + &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
> + <0x0 0 0 4
> + &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
> + <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
> + <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
> + <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
> + <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
> + clock-names = "pcie_phy_ref", "pcie_aux",
> + "pcie_apb_phy", "pcie_apb_sys",
> + "pcie_aclk";
> + reset-gpios = <&gpio11 1 0 >;
> + };
> };
> };
>
^ permalink raw reply [flat|nested] 24+ messages in thread
end of thread, other threads:[~2017-06-16 14:50 UTC | newest]
Thread overview: 24+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-06-15 3:03 [PATCH v4 00/20] arm64: dts: hi3660: add device nodes Guodong Xu
2017-06-15 3:03 ` [PATCH v4 01/20] dt-bindings: arm: hisilicon: add bindings for HiKey960 board Guodong Xu
2017-06-15 3:03 ` [PATCH v4 02/20] arm64: dts: hisilicon: update compatible string for hikey960 Guodong Xu
2017-06-15 3:04 ` [PATCH v4 03/20] arm64: dts: hikey960: pinctrl: add more pinmux and pinconfig Guodong Xu
2017-06-15 3:04 ` [PATCH v4 04/20] arm64: dts: hi3660: add resources for clock and reset Guodong Xu
2017-06-15 3:04 ` [PATCH v4 05/20] arm64: dts: Add I2C nodes for Hi3660 Guodong Xu
2017-06-15 3:04 ` [PATCH v4 06/20] arm64: dts: hi3660: add gpio dtsi file for Hisilicon Hi3660 SOC Guodong Xu
2017-06-15 3:04 ` [PATCH v4 07/20] arm64: dts: hi3660: Add uarts nodes Guodong Xu
2017-06-15 3:04 ` [PATCH v4 08/20] arm64: dts: hikey960: add WL1837 Bluetooth device node Guodong Xu
2017-06-15 3:04 ` [PATCH v4 09/20] arm64: dts: hi3660: Add pl031 rtc node Guodong Xu
2017-06-15 3:04 ` [PATCH v4 10/20] arm64: dts: hi3660: add power key dts node Guodong Xu
2017-06-15 3:04 ` [PATCH v4 11/20] arm64: dts: hikey960: add LED nodes Guodong Xu
2017-06-15 3:04 ` [PATCH v4 12/20] arm64: dts: hi3660: add spi device nodes Guodong Xu
2017-06-15 3:04 ` [PATCH v4 13/20] arm64: dts: hi3660: add sp804 timer node Guodong Xu
2017-06-15 3:04 ` [PATCH v4 14/20] dt-bindings: PCI: hisi: Add document for PCIe of Kirin SoCs Guodong Xu
2017-06-15 3:04 ` [PATCH v4 15/20] arm64: dts: hisi: add kirin pcie node Guodong Xu
2017-06-16 14:13 ` [PATCH v5 " Guodong Xu
2017-06-16 14:43 ` Wei Xu
2017-06-15 3:04 ` [PATCH v4 16/20] dt-bindings: mfd: hi6421: Add hi6421v530 compatible string Guodong Xu
2017-06-15 3:04 ` [PATCH v4 17/20] arm64: dts: hikey960: add device node for pmic and regulators Guodong Xu
2017-06-15 3:04 ` [PATCH v4 18/20] dt-bindings: mmc: dw_mmc-k3: add document of hi3660 mmc Guodong Xu
2017-06-15 3:04 ` [PATCH v4 19/20] arm64: dts: hi3660: add sd/sdio device nodes Guodong Xu
2017-06-15 3:04 ` [PATCH v4 20/20] arm64: dts: hi3660-hikey960: add nodes for WiFi Guodong Xu
2017-06-15 19:49 ` [PATCH v4 00/20] arm64: dts: hi3660: add device nodes Wei Xu
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).