[PATCH 0/2] clk: ARM: dts: exynos: Fix hang on Odroid U3

[PATCH 0/2] clk: ARM: dts: exynos: Fix hang on Odroid U3

[Krzysztof Kozlowski]

Recent linux-next fails to boot on Odroid U3 (Exynos4412) because
of commit 6edfa11cb396 ("clk: samsung: Add enable/disable operation
for PLL36XX clocks").

Patchset fixes it. Patches are independent although both are required
to fix the issue.

I will be taking DTS change.

Best regards,
Krzysztof

Krzysztof Kozlowski (2):
  clk: samsung: audss: Fix silent hang on Exynos4412 due to disabled
    EPLL
  ARM: dts: exynos: Add clocks to audss block to fix silent hang on
    Exynos4412

 arch/arm/boot/dts/exynos4.dtsi         | 3 +++
 drivers/clk/samsung/clk-exynos-audss.c | 1 +
 2 files changed, 4 insertions(+)

-- 
2.9.3

[PATCH 1/2] clk: samsung: audss: Fix silent hang on Exynos4412 due to disabled EPLL

[Krzysztof Kozlowski]

Similarly to commit f1e9203e2366 ("clk: samsung: Fix Exynos 5420 pinctrl
setup and clock disable failure due to domain being gated") for
Exynos5420, the Exynos4412 also requires that EPLL is not disabled.
Otherwise any access to MAUDIO block will silently halt.

This was not visible before because EPLL on Exynos4 could not be
disabled before commit 6edfa11cb396 ("clk: samsung:
Add enable/disable operation for PLL36XX clocks").  After this commit,
on Odroid U3 board one can see silent hang, usually with last (but
unrelated) messages:

	[    2.382741] input: gpio_keys as /devices/platform/gpio_keys/input/input0
	[    2.405686] usb 1-3: new high-speed USB device number 3 using exynos-ehci
	[    2.419843] max77686-rtc max77686-rtc: setting system clock to 2017-06-21 17:04:13 UTC (1498064653)

Mark Exynos4 variant as also needed EPLL to be enabled all the time.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
 drivers/clk/samsung/clk-exynos-audss.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c
index 85edeb738853..1fab56f396d4 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -73,6 +73,7 @@ struct exynos_audss_clk_drvdata {
 
 static const struct exynos_audss_clk_drvdata exynos4210_drvdata = {
 	.num_clks	= EXYNOS_AUDSS_MAX_CLKS - 1,
+	.enable_epll	= 1,
 };
 
 static const struct exynos_audss_clk_drvdata exynos5410_drvdata = {
-- 
2.9.3

Re: [PATCH 1/2] clk: samsung: audss: Fix silent hang on Exynos4412 due to disabled EPLL

[Sylwester Nawrocki]

On 06/21/2017 09:08 PM, Krzysztof Kozlowski wrote:
> Similarly to commit f1e9203e2366 ("clk: samsung: Fix Exynos 5420 pinctrl
> setup and clock disable failure due to domain being gated") for
> Exynos5420, the Exynos4412 also requires that EPLL is not disabled.
> Otherwise any access to MAUDIO block will silently halt.
> 
> This was not visible before because EPLL on Exynos4 could not be
> disabled before commit 6edfa11cb396 ("clk: samsung:
> Add enable/disable operation for PLL36XX clocks").  After this commit,
> on Odroid U3 board one can see silent hang, usually with last (but
> unrelated) messages:
> 
> 	[    2.382741] input: gpio_keys as /devices/platform/gpio_keys/input/input0
> 	[    2.405686] usb 1-3: new high-speed USB device number 3 using exynos-ehci
> 	[    2.419843] max77686-rtc max77686-rtc: setting system clock to 2017-06-21 17:04:13 UTC (1498064653)
> 
> Mark Exynos4 variant as also needed EPLL to be enabled all the time.
> 
> Signed-off-by: Krzysztof Kozlowski<krzk@kernel.org>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

Stephen, Mike,

Can you please apply this patch directly?

-- 
Thanks,
Sylwester

Re: [PATCH 1/2] clk: samsung: audss: Fix silent hang on Exynos4412 due to disabled EPLL

[Stephen Boyd]

On 06/22, Sylwester Nawrocki wrote:
> On 06/21/2017 09:08 PM, Krzysztof Kozlowski wrote:
> >Similarly to commit f1e9203e2366 ("clk: samsung: Fix Exynos 5420 pinctrl
> >setup and clock disable failure due to domain being gated") for
> >Exynos5420, the Exynos4412 also requires that EPLL is not disabled.
> >Otherwise any access to MAUDIO block will silently halt.
> >
> >This was not visible before because EPLL on Exynos4 could not be
> >disabled before commit 6edfa11cb396 ("clk: samsung:
> >Add enable/disable operation for PLL36XX clocks").  After this commit,
> >on Odroid U3 board one can see silent hang, usually with last (but
> >unrelated) messages:
> >
> >	[    2.382741] input: gpio_keys as /devices/platform/gpio_keys/input/input0
> >	[    2.405686] usb 1-3: new high-speed USB device number 3 using exynos-ehci
> >	[    2.419843] max77686-rtc max77686-rtc: setting system clock to 2017-06-21 17:04:13 UTC (1498064653)
> >
> >Mark Exynos4 variant as also needed EPLL to be enabled all the time.
> >
> >Signed-off-by: Krzysztof Kozlowski<krzk@kernel.org>
> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
> 
> Stephen, Mike,
> 
> Can you please apply this patch directly?
> 

Applied to clk-next.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 2/2] ARM: dts: exynos: Add clocks to audss block to fix silent hang on Exynos4412

[Krzysztof Kozlowski]

Add necessary parent clocks for audss (Audio SubSystem, MAUDIO) clock
controller block.

This allows driver to keep EPLL enabled before accessing any MAUDIO
registers thus fixing silent hang.  This silent hang appeard with commit
6edfa11cb396 ("clk: samsung: Add enable/disable operation for PLL36XX
clocks"), e.g. on Odroid U3 usually with last (but unrelated) messages:

	[    2.382741] input: gpio_keys as /devices/platform/gpio_keys/input/input0
	[    2.405686] usb 1-3: new high-speed USB device number 3 using exynos-ehci
	[    2.419843] max77686-rtc max77686-rtc: setting system clock to 2017-06-21 17:04:13 UTC (1498064653)

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
 arch/arm/boot/dts/exynos4.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 497a9470c888..5739389f5bb8 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -59,6 +59,9 @@
 		compatible = "samsung,exynos4210-audss-clock";
 		reg = <0x03810000 0x0C>;
 		#clock-cells = <1>;
+		clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
+			 <&clock CLK_SCLK_AUDIO0>, <&clock CLK_SCLK_AUDIO0>;
+		clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
 	};
 
 	i2s0: i2s@03830000 {
-- 
2.9.3