[PATCH v11 0/3]add PCIe driver for Kirin PCIe

[PATCH v11 0/3]add PCIe driver for Kirin PCIe

[Xiaowei Song]

Before Version Patches
======================
patch v9
http://www.spinics.net/lists/linux-pci/msg61821.html
patch V8
http://www.spinics.net/lists/linux-pci/msg61715.html
patch V7
https://www.spinics.net/lists/linux-pci/msg61664.html
patch V6
https://www.spinics.net/lists/linux-pci/msg61610.html

patch V4
https://www.spinics.net/lists/linux-pci/msg61406.html

patch V3
https://www.spinics.net/lists/linux-pci/msg61399.html

Changes between V11 and V9
========================
1. Fix the indent issues according to the review comments from Bjorn:
   (1) The value of reg is right-aligned in both dtsi file and Documentation file.
   (2) Re-indent the space of macro defination pointed out by Bjorn.
   (3) Adjust the space in 'struct kirin_pcie' defination.
   (4) Use dev replace of pdev->dev in function  kirin_pcie_get_clk and kirin_pcie_get_resource.
   (5) Aligned params with '(' in function kirin_apb_ctrl_writel and several others.
2. Fix the issues that compitable value in Documentation was different with .dtsi file.
3. For dependance during compiling, the dtsi patch is deleted, and it was merged in patch[1].
4. The indent style issues will be pull with MSI-patch in the next weeks;

patch[1]: https://www.spinics.net/lists/arm-kernel/msg588944.html

=========================
Changes between V8 and V7
=========================
1. Fix the indent issues in Documentation, dtsi file and macro defination.
2. Replace pdev->dev with dev in kirin_pcie_get_resource and 
   kirin_pcie_get_clk functions.
3. Put variables "pci" and "kirin_pcie" to be initialized at first
   in kirin_pcie_wr_own_config, kirin_pcie_read_dbi and other functions.
4. Add space before blankets in "Low power mode(L1 ".
5. Short the Makefile sentence to lower than 80 characters
   and delete reduntant words.
6. Use word 'located' instead of the wrong one 'lacated'.
7. Fix the problem of return value type.

Changes between V8 and V7
=========================
1. Replace 'reset-gpios' of 'reset-gpio' in Documentation.

Changes between V7 and V6
=========================
1. add enumeration log Based on Hikey960 Board with these patches.
2. fix issues as fellows:
   (1) delete reduntant blankets in macro defination,
   (2) add blank line in  kirin_pcie_clk_ctrl function.
   (3) Fix compitable property in DT with the SoC name,
       for example "hisilicon,kirin960-pcie".

Changes between V6 and V4
=========================
1. seperate Document from .dtsi patch.
2. fix issues according to review comments
   from Bjorn Helgaas and Rob Herring: annotation stype, DT node,
   patch post method and so on.

Enumeration log
===============
These test logs come from patches running on Hikey960 Board
(1) Connect with Atheros Communications WIFI
	OF: PCI: host bridge /soc/kirin_pcie_rc@f4000000 ranges:
	OF: PCI:   MEM 0xf6000000..0xf7ffffff -> 0x00000000
	kirin-pcie f4000000.kirin_pcie_rc: PCI host bridge to bus 0000:00
	pci_bus 0000:00: root bus resource [bus 00-01]
	pci_bus 0000:00: root bus resource [mem 0xf6000000-0xf7ffffff] (bus address [0x00000000-0x01ffffff])
	pci 0000:00:00.0: [19e5:3660] type 01 class 0x060400
	pci 0000:00:00.0: reg 0x10: [mem 0xf6000000-0xf6ffffff]
	pci 0000:00:00.0: supports D1 D2
	pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot
	pci 0000:01:00.0: [168c:002a] type 00 class 0x028000
	pci 0000:01:00.0: reg 0x10: [mem 0xf6000000-0xf600ffff 64bit]
	pci 0000:01:00.0: supports D1
	pci 0000:01:00.0: PME# supported from D0 D1 D3hot
	pci 0000:01:00.0: disabling ASPM on pre-1.1 PCIe device.  You can enable it with 'pcie_aspm=force'
	pci 0000:00:00.0: BAR 0: assigned [mem 0xf6000000-0xf6ffffff]
	pci 0000:00:00.0: BAR 14: assigned [mem 0xf7000000-0xf70fffff]
	pci 0000:01:00.0: BAR 0: assigned [mem 0xf7000000-0xf700ffff 64bit]
	pci 0000:00:00.0: PCI bridge to [bus 01]
	pci 0000:00:00.0:   bridge window [mem 0xf7000000-0xf70fffff]
	pcieport 0000:00:00.0: Signaling PME with IRQ 276
	pcieport 0000:00:00.0: AER enabled with IRQ 276	 


Xiaowei Song (3):
  PCI: hisi: Add DT binding for PCIe of Kirin SoC series
  PCI: dwc: kirin: add PCIe Driver for HiSilicon Kirin SoC
  ARM4: defconfig: Enable  Kirin PCIe

 .../devicetree/bindings/pci/kirin-pcie.txt         |  55 +++
 arch/arm64/configs/defconfig                       |   1 +
 drivers/pci/dwc/Kconfig                            |  10 +
 drivers/pci/dwc/Makefile                           |   1 +
 drivers/pci/dwc/pcie-kirin.c                       | 518 +++++++++++++++++++++
 5 files changed, 585 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txt
 create mode 100644 drivers/pci/dwc/pcie-kirin.c

-- 
2.11.GIT

[PATCH v11 1/3] PCI: hisi: Add DT binding for PCIe of Kirin SoC series

[Xiaowei Song]

Cc: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Xiaowei Song <songxiaowei@hisilicon.com>
Acked-by: Rob Herring <robh@kernel.org>
---
 .../devicetree/bindings/pci/kirin-pcie.txt         | 55 ++++++++++++++++++++++
 1 file changed, 55 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txt

diff --git a/Documentation/devicetree/bindings/pci/kirin-pcie.txt b/Documentation/devicetree/bindings/pci/kirin-pcie.txt
new file mode 100644
index 000000000000..c2be01270ec5
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/kirin-pcie.txt
@@ -0,0 +1,55 @@
+HiSilicon Kirin SoCs PCIe host DT description
+
+Kirin PCIe host controller is based on Designware PCI core.
+It shares common functions with PCIe Designware core driver
+and inherits common properties defined in
+Documentation/devicetree/bindings/pci/designware-pci.txt.
+
+Additional properties are described here:
+
+Required properties
+- compatible:
+	"hisilicon,kirin960-pcie" for PCIe of Kirin960 SoC
+- reg: Should contain rc_dbi, apb, phy, config registers location and length.
+- reg-names: Must include the following entries:
+  "dbi": controller configuration registers;
+  "apb": apb Ctrl register defined by Kirin;
+  "phy": apb PHY register defined by Kirin;
+  "config": PCIe configuration space registers.
+- reset-gpios: The gpio to generate PCIe perst assert and deassert signal.
+
+Optional properties:
+
+Example based on kirin960:
+
+	pcie@f4000000 {
+		compatible = "hisilicon,kirin960-pcie";
+		reg = <0x0 0xf4000000 0x0 0x1000>,
+		      <0x0 0xff3fe000 0x0 0x1000>,
+		      <0x0 0xf3f20000 0x0 0x40000>,
+		      <0x0 0xf4000000 0x0  0x2000>;
+		reg-names = "dbi","apb","phy", "config";
+		bus-range = <0x0  0x1>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		ranges = <0x02000000 0x0 0x0
+			  0x0 0xf5000000
+			  0x0 0x2000000>;
+		num-lanes = <1>;
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0xf800 0 0 7>;
+		interrupt-map = <0x0 0 0 1 &gic 0 282 4>,
+				<0x0 0 0 2 &gic 0 283 4>,
+				<0x0 0 0 3 &gic 0 284 4>,
+				<0x0 0 0 4 &gic 0 285 4>;
+		clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
+			 <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
+			 <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
+			 <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
+			 <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
+		clock-names = "pcie_phy_ref", "pcie_aux",
+			      "pcie_apb_phy", "pcie_apb_sys",
+			      "pcie_aclk";
+		reset-gpios = <&gpio11 1 0>;
+	};
-- 
2.11.GIT

[PATCH v11 2/3] PCI: dwc: kirin: add PCIe Driver for HiSilicon Kirin SoC

[Xiaowei Song]

Hisilicon PCIe Driver shares the common functions for PCIe dw-host

The poweron functions is developed on hi3660 SoC,
while Others Functions are common for Kirin series SoCs.

Low power mode (L1 sub-state and Suspend/Resume), hotplug
and MSI feature are not supported currently.

Cc: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Xiaowei Song <songxiaowei@hisilicon.com>
Reviewed-by: Jingoo Han <jingoohan1@gmail.com>
---
 drivers/pci/dwc/Kconfig      |  10 +
 drivers/pci/dwc/Makefile     |   1 +
 drivers/pci/dwc/pcie-kirin.c | 518 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 529 insertions(+)
 create mode 100644 drivers/pci/dwc/pcie-kirin.c

diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig
index d2d2ba5b8a68..afecfb2b6ff4 100644
--- a/drivers/pci/dwc/Kconfig
+++ b/drivers/pci/dwc/Kconfig
@@ -130,4 +130,14 @@ config PCIE_ARTPEC6
 	  Say Y here to enable PCIe controller support on Axis ARTPEC-6
 	  SoCs.  This PCIe controller uses the DesignWare core.
 
+config PCIE_KIRIN
+	depends on OF && ARM64
+	bool "HiSilicon Kirin series SoCs PCIe controllers"
+	depends on PCI
+	select PCIEPORTBUS
+	select PCIE_DW_HOST
+	help
+	  Say Y here if you want PCIe controller support
+	  on HiSilicon Kirin series SoCs.
+
 endmenu
diff --git a/drivers/pci/dwc/Makefile b/drivers/pci/dwc/Makefile
index a2df13c28798..4bd69bacd4ab 100644
--- a/drivers/pci/dwc/Makefile
+++ b/drivers/pci/dwc/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
 obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
 obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
 obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
+obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o
 
 # The following drivers are for devices that use the generic ACPI
 # pci_root.c driver but don't support standard ECAM config access.
diff --git a/drivers/pci/dwc/pcie-kirin.c b/drivers/pci/dwc/pcie-kirin.c
new file mode 100644
index 000000000000..c5f35df8cced
--- /dev/null
+++ b/drivers/pci/dwc/pcie-kirin.c
@@ -0,0 +1,518 @@
+/*
+ * PCIe host controller driver for Kirin Phone SoCs
+ *
+ * Copyright (C) 2017 Hilisicon Electronics Co., Ltd.
+ *		http://www.huawei.com
+ *
+ * Author: Xiaowei Song <songxiaowei@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <asm/compiler.h>
+#include <linux/compiler.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of_address.h>
+#include <linux/of_gpio.h>
+#include <linux/of_pci.h>
+#include <linux/pci.h>
+#include <linux/pci_regs.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/resource.h>
+#include <linux/types.h>
+#include "pcie-designware.h"
+
+#define to_kirin_pcie(x) dev_get_drvdata((x)->dev)
+
+#define REF_CLK_FREQ			100000000
+
+/* PCIe ELBI registers */
+#define SOC_PCIECTRL_CTRL0_ADDR		0x000
+#define SOC_PCIECTRL_CTRL1_ADDR		0x004
+#define SOC_PCIEPHY_CTRL2_ADDR		0x008
+#define SOC_PCIEPHY_CTRL3_ADDR		0x00c
+#define PCIE_ELBI_SLV_DBI_ENABLE	(0x1 << 21)
+
+/* info located in APB */
+#define PCIE_APP_LTSSM_ENABLE	0x01c
+#define PCIE_APB_PHY_CTRL0	0x0
+#define PCIE_APB_PHY_CTRL1	0x4
+#define PCIE_APB_PHY_STATUS0	0x400
+#define PCIE_LINKUP_ENABLE	(0x8020)
+#define PCIE_LTSSM_ENABLE_BIT	(0x1 << 11)
+#define PIPE_CLK_STABLE		(0x1 << 19)
+#define PHY_REF_PAD_BIT		(0x1 << 8)
+#define PHY_PWR_DOWN_BIT	(0x1 << 22)
+#define PHY_RST_ACK_BIT		(0x1 << 16)
+
+/* info located in sysctrl */
+#define SCTRL_PCIE_CMOS_OFFSET	0x60
+#define SCTRL_PCIE_CMOS_BIT	0x10
+#define SCTRL_PCIE_ISO_OFFSET	0x44
+#define SCTRL_PCIE_ISO_BIT	0x30
+#define SCTRL_PCIE_HPCLK_OFFSET	0x190
+#define SCTRL_PCIE_HPCLK_BIT	0x184000
+#define SCTRL_PCIE_OE_OFFSET	0x14a
+#define PCIE_DEBOUNCE_PARAM	0xF0F400
+#define PCIE_OE_BYPASS		(0x3 << 28)
+
+/* peri_crg ctrl */
+#define CRGCTRL_PCIE_ASSERT_OFFSET	0x88
+#define CRGCTRL_PCIE_ASSERT_BIT		0x8c000000
+
+/* Time for delay */
+#define REF_2_PERST_MIN		20000
+#define REF_2_PERST_MAX		25000
+#define PERST_2_ACCESS_MIN	10000
+#define PERST_2_ACCESS_MAX	12000
+#define LINK_WAIT_MIN		900
+#define LINK_WAIT_MAX		1000
+#define PIPE_CLK_WAIT_MIN	550
+#define PIPE_CLK_WAIT_MAX	600
+#define TIME_CMOS_MIN		100
+#define TIME_CMOS_MAX		105
+#define TIME_PHY_PD_MIN		10
+#define TIME_PHY_PD_MAX		11
+
+struct kirin_pcie {
+	struct dw_pcie	*pci;
+	void __iomem	*apb_base;
+	void __iomem	*phy_base;
+	struct regmap	*crgctrl;
+	struct regmap	*sysctrl;
+	struct clk	*apb_sys_clk;
+	struct clk	*apb_phy_clk;
+	struct clk	*phy_ref_clk;
+	struct clk	*pcie_aclk;
+	struct clk	*pcie_aux_clk;
+	int		gpio_id_reset;
+};
+
+/* Registers in PCIeCTRL */
+static inline void kirin_apb_ctrl_writel(struct kirin_pcie *kirin_pcie,
+					 u32 val, u32 reg)
+{
+	writel(val, kirin_pcie->apb_base + reg);
+}
+
+static inline u32 kirin_apb_ctrl_readl(struct kirin_pcie *kirin_pcie, u32 reg)
+{
+	return readl(kirin_pcie->apb_base + reg);
+}
+
+/* Registers in PCIePHY */
+static inline void kirin_apb_phy_writel(struct kirin_pcie *kirin_pcie,
+					u32 val, u32 reg)
+{
+	writel(val, kirin_pcie->phy_base + reg);
+}
+
+static inline u32 kirin_apb_phy_readl(struct kirin_pcie *kirin_pcie, u32 reg)
+{
+	return readl(kirin_pcie->phy_base + reg);
+}
+
+static long kirin_pcie_get_clk(struct kirin_pcie *kirin_pcie,
+			       struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+
+	kirin_pcie->phy_ref_clk = devm_clk_get(dev, "pcie_phy_ref");
+	if (IS_ERR(kirin_pcie->phy_ref_clk))
+		return PTR_ERR(kirin_pcie->phy_ref_clk);
+
+	kirin_pcie->pcie_aux_clk = devm_clk_get(dev, "pcie_aux");
+	if (IS_ERR(kirin_pcie->pcie_aux_clk))
+		return PTR_ERR(kirin_pcie->pcie_aux_clk);
+
+	kirin_pcie->apb_phy_clk = devm_clk_get(dev, "pcie_apb_phy");
+	if (IS_ERR(kirin_pcie->apb_phy_clk))
+		return PTR_ERR(kirin_pcie->apb_phy_clk);
+
+	kirin_pcie->apb_sys_clk = devm_clk_get(dev, "pcie_apb_sys");
+	if (IS_ERR(kirin_pcie->apb_sys_clk))
+		return PTR_ERR(kirin_pcie->apb_sys_clk);
+
+	kirin_pcie->pcie_aclk = devm_clk_get(dev, "pcie_aclk");
+	if (IS_ERR(kirin_pcie->pcie_aclk))
+		return PTR_ERR(kirin_pcie->pcie_aclk);
+
+	return 0;
+}
+
+static long kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie,
+				    struct platform_device *pdev)
+{
+	struct resource *apb;
+	struct resource *phy;
+	struct resource *dbi;
+	struct device *dev = &pdev->dev;
+
+	apb = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apb");
+	kirin_pcie->apb_base = devm_ioremap_resource(dev, apb);
+	if (IS_ERR(kirin_pcie->apb_base))
+		return PTR_ERR(kirin_pcie->apb_base);
+
+	phy = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
+	kirin_pcie->phy_base = devm_ioremap_resource(dev, phy);
+	if (IS_ERR(kirin_pcie->phy_base))
+		return PTR_ERR(kirin_pcie->phy_base);
+
+	dbi = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
+	kirin_pcie->pci->dbi_base = devm_ioremap_resource(dev, dbi);
+	if (IS_ERR(kirin_pcie->pci->dbi_base))
+		return PTR_ERR(kirin_pcie->pci->dbi_base);
+
+	kirin_pcie->crgctrl =
+		syscon_regmap_lookup_by_compatible("hisilicon,hi3660-crgctrl");
+	if (IS_ERR(kirin_pcie->crgctrl))
+		return PTR_ERR(kirin_pcie->crgctrl);
+
+	kirin_pcie->sysctrl =
+		syscon_regmap_lookup_by_compatible("hisilicon,hi3660-sctrl");
+	if (IS_ERR(kirin_pcie->sysctrl))
+		return PTR_ERR(kirin_pcie->sysctrl);
+
+	return 0;
+}
+
+static int kirin_pcie_phy_init(struct kirin_pcie *kirin_pcie)
+{
+	u32 reg_val;
+	struct device *dev = kirin_pcie->pci->dev;
+
+	reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL1);
+	reg_val &= ~PHY_REF_PAD_BIT;
+	kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL1);
+
+	reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL0);
+	reg_val &= ~PHY_PWR_DOWN_BIT;
+	kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL0);
+	usleep_range(TIME_PHY_PD_MIN, TIME_PHY_PD_MAX);
+
+	reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL1);
+	reg_val &= ~PHY_RST_ACK_BIT;
+	kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL1);
+
+	usleep_range(PIPE_CLK_WAIT_MIN, PIPE_CLK_WAIT_MAX);
+	reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_STATUS0);
+	if (reg_val & PIPE_CLK_STABLE) {
+		dev_err(dev, "PIPE clk is not stable\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static void kirin_pcie_oe_enable(struct kirin_pcie *kirin_pcie)
+{
+	u32 val;
+
+	regmap_read(kirin_pcie->sysctrl, SCTRL_PCIE_OE_OFFSET, &val);
+	val |= PCIE_DEBOUNCE_PARAM;
+	val &= ~PCIE_OE_BYPASS;
+	regmap_write(kirin_pcie->sysctrl, SCTRL_PCIE_OE_OFFSET, val);
+}
+
+static int kirin_pcie_clk_ctrl(struct kirin_pcie *kirin_pcie, bool enable)
+{
+	int ret = 0;
+
+	if (!enable)
+		goto close_clk;
+
+	ret = clk_set_rate(kirin_pcie->phy_ref_clk, REF_CLK_FREQ);
+	if (ret)
+		return ret;
+
+	ret = clk_prepare_enable(kirin_pcie->phy_ref_clk);
+	if (ret)
+		return ret;
+
+	ret = clk_prepare_enable(kirin_pcie->apb_sys_clk);
+	if (ret)
+		goto apb_sys_fail;
+
+	ret = clk_prepare_enable(kirin_pcie->apb_phy_clk);
+	if (ret)
+		goto apb_phy_fail;
+
+	ret = clk_prepare_enable(kirin_pcie->pcie_aclk);
+	if (ret)
+		goto aclk_fail;
+
+	ret = clk_prepare_enable(kirin_pcie->pcie_aux_clk);
+	if (ret)
+		goto aux_clk_fail;
+
+	return 0;
+
+close_clk:
+	clk_disable_unprepare(kirin_pcie->pcie_aux_clk);
+aux_clk_fail:
+	clk_disable_unprepare(kirin_pcie->pcie_aclk);
+aclk_fail:
+	clk_disable_unprepare(kirin_pcie->apb_phy_clk);
+apb_phy_fail:
+	clk_disable_unprepare(kirin_pcie->apb_sys_clk);
+apb_sys_fail:
+	clk_disable_unprepare(kirin_pcie->phy_ref_clk);
+
+	return ret;
+}
+
+static int kirin_pcie_power_on(struct kirin_pcie *kirin_pcie)
+{
+	int ret;
+
+	/* Power supply for Host */
+	regmap_write(kirin_pcie->sysctrl,
+		     SCTRL_PCIE_CMOS_OFFSET, SCTRL_PCIE_CMOS_BIT);
+	usleep_range(TIME_CMOS_MIN, TIME_CMOS_MAX);
+	kirin_pcie_oe_enable(kirin_pcie);
+
+	ret = kirin_pcie_clk_ctrl(kirin_pcie, true);
+	if (ret)
+		return ret;
+
+	/* ISO disable, PCIeCtrl, PHY assert and clk gate clear */
+	regmap_write(kirin_pcie->sysctrl,
+		     SCTRL_PCIE_ISO_OFFSET, SCTRL_PCIE_ISO_BIT);
+	regmap_write(kirin_pcie->crgctrl,
+		     CRGCTRL_PCIE_ASSERT_OFFSET, CRGCTRL_PCIE_ASSERT_BIT);
+	regmap_write(kirin_pcie->sysctrl,
+		     SCTRL_PCIE_HPCLK_OFFSET, SCTRL_PCIE_HPCLK_BIT);
+
+	ret = kirin_pcie_phy_init(kirin_pcie);
+	if (ret)
+		goto close_clk;
+
+	/* perst assert Endpoint */
+	if (!gpio_request(kirin_pcie->gpio_id_reset, "pcie_perst")) {
+		usleep_range(REF_2_PERST_MIN, REF_2_PERST_MAX);
+		ret = gpio_direction_output(kirin_pcie->gpio_id_reset, 1);
+		if (ret)
+			goto close_clk;
+		usleep_range(PERST_2_ACCESS_MIN, PERST_2_ACCESS_MAX);
+
+		return 0;
+	}
+
+close_clk:
+	kirin_pcie_clk_ctrl(kirin_pcie, false);
+	return ret;
+}
+
+static void kirin_pcie_sideband_dbi_w_mode(struct kirin_pcie *kirin_pcie,
+					   bool on)
+{
+	u32 val;
+
+	val = kirin_apb_ctrl_readl(kirin_pcie, SOC_PCIECTRL_CTRL0_ADDR);
+	if (on)
+		val = val | PCIE_ELBI_SLV_DBI_ENABLE;
+	else
+		val = val & ~PCIE_ELBI_SLV_DBI_ENABLE;
+
+	kirin_apb_ctrl_writel(kirin_pcie, val, SOC_PCIECTRL_CTRL0_ADDR);
+}
+
+static void kirin_pcie_sideband_dbi_r_mode(struct kirin_pcie *kirin_pcie,
+					   bool on)
+{
+	u32 val;
+
+	val = kirin_apb_ctrl_readl(kirin_pcie, SOC_PCIECTRL_CTRL1_ADDR);
+	if (on)
+		val = val | PCIE_ELBI_SLV_DBI_ENABLE;
+	else
+		val = val & ~PCIE_ELBI_SLV_DBI_ENABLE;
+
+	kirin_apb_ctrl_writel(kirin_pcie, val, SOC_PCIECTRL_CTRL1_ADDR);
+}
+
+static int kirin_pcie_rd_own_conf(struct pcie_port *pp,
+				  int where, int size, u32 *val)
+{
+	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+	struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
+	int ret;
+
+	kirin_pcie_sideband_dbi_r_mode(kirin_pcie, true);
+	ret = dw_pcie_read(pci->dbi_base + where, size, val);
+	kirin_pcie_sideband_dbi_r_mode(kirin_pcie, false);
+
+	return ret;
+}
+
+static int kirin_pcie_wr_own_conf(struct pcie_port *pp,
+				  int where, int size, u32 val)
+{
+	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+	struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
+	int ret;
+
+	kirin_pcie_sideband_dbi_w_mode(kirin_pcie, true);
+	ret = dw_pcie_write(pci->dbi_base + where, size, val);
+	kirin_pcie_sideband_dbi_w_mode(kirin_pcie, false);
+
+	return ret;
+}
+
+static u32 kirin_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base,
+			       u32 reg, size_t size)
+{
+	struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
+	u32 ret;
+
+	kirin_pcie_sideband_dbi_r_mode(kirin_pcie, true);
+	dw_pcie_read(base + reg, size, &ret);
+	kirin_pcie_sideband_dbi_r_mode(kirin_pcie, false);
+
+	return ret;
+}
+
+static void kirin_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base,
+				 u32 reg, size_t size, u32 val)
+{
+	struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
+
+	kirin_pcie_sideband_dbi_w_mode(kirin_pcie, true);
+	dw_pcie_write(base + reg, size, val);
+	kirin_pcie_sideband_dbi_w_mode(kirin_pcie, false);
+}
+
+static int kirin_pcie_link_up(struct dw_pcie *pci)
+{
+	struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
+	u32 val = kirin_apb_ctrl_readl(kirin_pcie, PCIE_APB_PHY_STATUS0);
+
+	if ((val & PCIE_LINKUP_ENABLE) == PCIE_LINKUP_ENABLE)
+		return 1;
+
+	return 0;
+}
+
+static int kirin_pcie_establish_link(struct pcie_port *pp)
+{
+	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+	struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
+	struct device *dev = kirin_pcie->pci->dev;
+	int count = 0;
+
+	if (kirin_pcie_link_up(pci))
+		return 0;
+
+	dw_pcie_setup_rc(pp);
+
+	/* assert LTSSM enable */
+	kirin_apb_ctrl_writel(kirin_pcie, PCIE_LTSSM_ENABLE_BIT,
+			      PCIE_APP_LTSSM_ENABLE);
+
+	/* check if the link is up or not */
+	while (!kirin_pcie_link_up(pci)) {
+		usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX);
+		count++;
+		if (count == 1000) {
+			dev_err(dev, "Link Fail\n");
+			return -EINVAL;
+		}
+	}
+
+	return 0;
+}
+
+static void kirin_pcie_host_init(struct pcie_port *pp)
+{
+	kirin_pcie_establish_link(pp);
+}
+
+static struct dw_pcie_ops kirin_dw_pcie_ops = {
+	.read_dbi = kirin_pcie_read_dbi,
+	.write_dbi = kirin_pcie_write_dbi,
+	.link_up = kirin_pcie_link_up,
+};
+
+static struct dw_pcie_host_ops kirin_pcie_host_ops = {
+	.rd_own_conf = kirin_pcie_rd_own_conf,
+	.wr_own_conf = kirin_pcie_wr_own_conf,
+	.host_init = kirin_pcie_host_init,
+};
+
+static int __init kirin_add_pcie_port(struct dw_pcie *pci,
+				      struct platform_device *pdev)
+{
+	pci->pp.ops = &kirin_pcie_host_ops;
+
+	return dw_pcie_host_init(&pci->pp);
+}
+
+static int kirin_pcie_probe(struct platform_device *pdev)
+{
+	struct kirin_pcie *kirin_pcie;
+	struct dw_pcie *pci;
+	struct device *dev = &pdev->dev;
+	int ret;
+
+	if (!dev->of_node) {
+		dev_err(dev, "NULL node\n");
+		return -EINVAL;
+	}
+
+	kirin_pcie = devm_kzalloc(dev, sizeof(struct kirin_pcie), GFP_KERNEL);
+	if (!kirin_pcie)
+		return -ENOMEM;
+
+	pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
+	if (!pci)
+		return -ENOMEM;
+
+	pci->dev = dev;
+	pci->ops = &kirin_dw_pcie_ops;
+	kirin_pcie->pci = pci;
+
+	ret = kirin_pcie_get_clk(kirin_pcie, pdev);
+	if (ret)
+		return ret;
+
+	ret = kirin_pcie_get_resource(kirin_pcie, pdev);
+	if (ret)
+		return ret;
+
+	kirin_pcie->gpio_id_reset = of_get_named_gpio(dev->of_node,
+						      "reset-gpio", 0);
+	if (kirin_pcie->gpio_id_reset < 0)
+		return -ENODEV;
+
+	ret = kirin_pcie_power_on(kirin_pcie);
+	if (ret)
+		return ret;
+
+	platform_set_drvdata(pdev, kirin_pcie);
+
+	return kirin_add_pcie_port(pci, pdev);
+}
+
+static const struct of_device_id kirin_pcie_match[] = {
+	{ .compatible = "hisilicon,kirin960-pcie" },
+	{},
+};
+
+struct platform_driver kirin_pcie_driver = {
+	.probe			= kirin_pcie_probe,
+	.driver			= {
+		.name			= "kirin-pcie",
+		.of_match_table = kirin_pcie_match,
+		.suppress_bind_attrs = true,
+	},
+};
+
+builtin_platform_driver(kirin_pcie_driver);
-- 
2.11.GIT

[PATCH v11 3/3] ARM4: defconfig: Enable Kirin PCIe

[Xiaowei Song]

Cc: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Xiaowei Song <songxiaowei@hisilicon.com>
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 7c48028ec64a..d56d8f1062ab 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -71,6 +71,7 @@ CONFIG_PCI_XGENE=y
 CONFIG_PCI_LAYERSCAPE=y
 CONFIG_PCI_HISI=y
 CONFIG_PCIE_QCOM=y
+CONFIG_PCIE_KIRIN=y
 CONFIG_PCIE_ARMADA_8K=y
 CONFIG_ARM64_VA_BITS_48=y
 CONFIG_SCHED_MC=y
-- 
2.11.GIT

Re: [PATCH v11 1/3] PCI: hisi: Add DT binding for PCIe of Kirin SoC series

[Wei Xu]

Hi Xiaowei,

On 2017/6/19 11:23, Xiaowei Song wrote:

Please add some commit message.

> Cc: Guodong Xu <guodong.xu@linaro.org>
> Signed-off-by: Xiaowei Song <songxiaowei@hisilicon.com>
> Acked-by: Rob Herring <robh@kernel.org>
> ---

I have picked up the patch from [1] and
the pull request has been merged into ARM SoC tree.
Please do not resend the same patch.
Thanks!

[1]:https://lkml.org/lkml/2017/6/14/1055

Best Regards,
Wei

>  .../devicetree/bindings/pci/kirin-pcie.txt         | 55 ++++++++++++++++++++++
>  1 file changed, 55 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txt
> 
> diff --git a/Documentation/devicetree/bindings/pci/kirin-pcie.txt b/Documentation/devicetree/bindings/pci/kirin-pcie.txt
> new file mode 100644
> index 000000000000..c2be01270ec5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/kirin-pcie.txt
> @@ -0,0 +1,55 @@
> +HiSilicon Kirin SoCs PCIe host DT description
> +
> +Kirin PCIe host controller is based on Designware PCI core.
> +It shares common functions with PCIe Designware core driver
> +and inherits common properties defined in
> +Documentation/devicetree/bindings/pci/designware-pci.txt.
> +
> +Additional properties are described here:
> +
> +Required properties
> +- compatible:
> +	"hisilicon,kirin960-pcie" for PCIe of Kirin960 SoC
> +- reg: Should contain rc_dbi, apb, phy, config registers location and length.
> +- reg-names: Must include the following entries:
> +  "dbi": controller configuration registers;
> +  "apb": apb Ctrl register defined by Kirin;
> +  "phy": apb PHY register defined by Kirin;
> +  "config": PCIe configuration space registers.
> +- reset-gpios: The gpio to generate PCIe perst assert and deassert signal.
> +
> +Optional properties:
> +
> +Example based on kirin960:
> +
> +	pcie@f4000000 {
> +		compatible = "hisilicon,kirin960-pcie";
> +		reg = <0x0 0xf4000000 0x0 0x1000>,
> +		      <0x0 0xff3fe000 0x0 0x1000>,
> +		      <0x0 0xf3f20000 0x0 0x40000>,
> +		      <0x0 0xf4000000 0x0  0x2000>;
> +		reg-names = "dbi","apb","phy", "config";
> +		bus-range = <0x0  0x1>;
> +		#address-cells = <3>;
> +		#size-cells = <2>;
> +		device_type = "pci";
> +		ranges = <0x02000000 0x0 0x0
> +			  0x0 0xf5000000
> +			  0x0 0x2000000>;
> +		num-lanes = <1>;
> +		#interrupt-cells = <1>;
> +		interrupt-map-mask = <0xf800 0 0 7>;
> +		interrupt-map = <0x0 0 0 1 &gic 0 282 4>,
> +				<0x0 0 0 2 &gic 0 283 4>,
> +				<0x0 0 0 3 &gic 0 284 4>,
> +				<0x0 0 0 4 &gic 0 285 4>;
> +		clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
> +			 <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
> +			 <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
> +			 <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
> +			 <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
> +		clock-names = "pcie_phy_ref", "pcie_aux",
> +			      "pcie_apb_phy", "pcie_apb_sys",
> +			      "pcie_aclk";
> +		reset-gpios = <&gpio11 1 0>;
> +	};
> 

Re: [PATCH v11 1/3] PCI: hisi: Add DT binding for PCIe of Kirin SoC series

[Wei Xu]

Hi Xiaowei,

On 2017/6/19 11:44, Wei Xu wrote:
> Hi Xiaowei,
> 
> On 2017/6/19 11:23, Xiaowei Song wrote:
> 
> Please add some commit message.
> 
>> Cc: Guodong Xu <guodong.xu@linaro.org>
>> Signed-off-by: Xiaowei Song <songxiaowei@hisilicon.com>
>> Acked-by: Rob Herring <robh@kernel.org>
>> ---
> 
> I have picked up the patch from [1] and
> the pull request has been merged into ARM SoC tree.
> Please do not resend the same patch.
> Thanks!
> 
> [1]:https://lkml.org/lkml/2017/6/14/1055

Sorry, the above link is wrong.
It should be https://lkml.org/lkml/2017/6/14/1056

BR,
Wei

> 
> Best Regards,
> Wei
> 
>>  .../devicetree/bindings/pci/kirin-pcie.txt         | 55 ++++++++++++++++++++++
>>  1 file changed, 55 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txt
>>
>> diff --git a/Documentation/devicetree/bindings/pci/kirin-pcie.txt b/Documentation/devicetree/bindings/pci/kirin-pcie.txt
>> new file mode 100644
>> index 000000000000..c2be01270ec5
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/kirin-pcie.txt
>> @@ -0,0 +1,55 @@
>> +HiSilicon Kirin SoCs PCIe host DT description
>> +
>> +Kirin PCIe host controller is based on Designware PCI core.
>> +It shares common functions with PCIe Designware core driver
>> +and inherits common properties defined in
>> +Documentation/devicetree/bindings/pci/designware-pci.txt.
>> +
>> +Additional properties are described here:
>> +
>> +Required properties
>> +- compatible:
>> +	"hisilicon,kirin960-pcie" for PCIe of Kirin960 SoC
>> +- reg: Should contain rc_dbi, apb, phy, config registers location and length.
>> +- reg-names: Must include the following entries:
>> +  "dbi": controller configuration registers;
>> +  "apb": apb Ctrl register defined by Kirin;
>> +  "phy": apb PHY register defined by Kirin;
>> +  "config": PCIe configuration space registers.
>> +- reset-gpios: The gpio to generate PCIe perst assert and deassert signal.
>> +
>> +Optional properties:
>> +
>> +Example based on kirin960:
>> +
>> +	pcie@f4000000 {
>> +		compatible = "hisilicon,kirin960-pcie";
>> +		reg = <0x0 0xf4000000 0x0 0x1000>,
>> +		      <0x0 0xff3fe000 0x0 0x1000>,
>> +		      <0x0 0xf3f20000 0x0 0x40000>,
>> +		      <0x0 0xf4000000 0x0  0x2000>;
>> +		reg-names = "dbi","apb","phy", "config";
>> +		bus-range = <0x0  0x1>;
>> +		#address-cells = <3>;
>> +		#size-cells = <2>;
>> +		device_type = "pci";
>> +		ranges = <0x02000000 0x0 0x0
>> +			  0x0 0xf5000000
>> +			  0x0 0x2000000>;
>> +		num-lanes = <1>;
>> +		#interrupt-cells = <1>;
>> +		interrupt-map-mask = <0xf800 0 0 7>;
>> +		interrupt-map = <0x0 0 0 1 &gic 0 282 4>,
>> +				<0x0 0 0 2 &gic 0 283 4>,
>> +				<0x0 0 0 3 &gic 0 284 4>,
>> +				<0x0 0 0 4 &gic 0 285 4>;
>> +		clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
>> +			 <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
>> +			 <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
>> +			 <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
>> +			 <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
>> +		clock-names = "pcie_phy_ref", "pcie_aux",
>> +			      "pcie_apb_phy", "pcie_apb_sys",
>> +			      "pcie_aclk";
>> +		reset-gpios = <&gpio11 1 0>;
>> +	};
>>

Re: [PATCH v11 2/3] PCI: dwc: kirin: add PCIe Driver for HiSilicon Kirin SoC

[Guodong Xu]

Hi, Bjorn

May I know what other comments you may have about this patchset? Do
you need us to do any further clean up?

If not, would you please pick patch 2 and 3 of v11 into your git tree
for -next? Thank you for your time.

Patch 1 of v11 has been picked up by platform maintainer, Wei Xu. I
can see it in linux-next 0626.

Best regards,
Guodong Xu

On Mon, Jun 19, 2017 at 6:23 PM, Xiaowei Song <songxiaowei@hisilicon.com> wrote:
> Hisilicon PCIe Driver shares the common functions for PCIe dw-host
>
> The poweron functions is developed on hi3660 SoC,
> while Others Functions are common for Kirin series SoCs.
>
> Low power mode (L1 sub-state and Suspend/Resume), hotplug
> and MSI feature are not supported currently.
>
> Cc: Guodong Xu <guodong.xu@linaro.org>
> Signed-off-by: Xiaowei Song <songxiaowei@hisilicon.com>
> Reviewed-by: Jingoo Han <jingoohan1@gmail.com>
> ---
>  drivers/pci/dwc/Kconfig      |  10 +
>  drivers/pci/dwc/Makefile     |   1 +
>  drivers/pci/dwc/pcie-kirin.c | 518 +++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 529 insertions(+)
>  create mode 100644 drivers/pci/dwc/pcie-kirin.c
>
> diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig
> index d2d2ba5b8a68..afecfb2b6ff4 100644
> --- a/drivers/pci/dwc/Kconfig
> +++ b/drivers/pci/dwc/Kconfig
> @@ -130,4 +130,14 @@ config PCIE_ARTPEC6
>           Say Y here to enable PCIe controller support on Axis ARTPEC-6
>           SoCs.  This PCIe controller uses the DesignWare core.
>
> +config PCIE_KIRIN
> +       depends on OF && ARM64
> +       bool "HiSilicon Kirin series SoCs PCIe controllers"
> +       depends on PCI
> +       select PCIEPORTBUS
> +       select PCIE_DW_HOST
> +       help
> +         Say Y here if you want PCIe controller support
> +         on HiSilicon Kirin series SoCs.
> +
>  endmenu
> diff --git a/drivers/pci/dwc/Makefile b/drivers/pci/dwc/Makefile
> index a2df13c28798..4bd69bacd4ab 100644
> --- a/drivers/pci/dwc/Makefile
> +++ b/drivers/pci/dwc/Makefile
> @@ -10,6 +10,7 @@ obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
>  obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
>  obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
>  obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
> +obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o
>
>  # The following drivers are for devices that use the generic ACPI
>  # pci_root.c driver but don't support standard ECAM config access.
> diff --git a/drivers/pci/dwc/pcie-kirin.c b/drivers/pci/dwc/pcie-kirin.c
> new file mode 100644
> index 000000000000..c5f35df8cced
> --- /dev/null
> +++ b/drivers/pci/dwc/pcie-kirin.c
> @@ -0,0 +1,518 @@
> +/*
> + * PCIe host controller driver for Kirin Phone SoCs
> + *
> + * Copyright (C) 2017 Hilisicon Electronics Co., Ltd.
> + *             http://www.huawei.com
> + *
> + * Author: Xiaowei Song <songxiaowei@huawei.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <asm/compiler.h>
> +#include <linux/compiler.h>
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/gpio.h>
> +#include <linux/interrupt.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/of_address.h>
> +#include <linux/of_gpio.h>
> +#include <linux/of_pci.h>
> +#include <linux/pci.h>
> +#include <linux/pci_regs.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/resource.h>
> +#include <linux/types.h>
> +#include "pcie-designware.h"
> +
> +#define to_kirin_pcie(x) dev_get_drvdata((x)->dev)
> +
> +#define REF_CLK_FREQ                   100000000
> +
> +/* PCIe ELBI registers */
> +#define SOC_PCIECTRL_CTRL0_ADDR                0x000
> +#define SOC_PCIECTRL_CTRL1_ADDR                0x004
> +#define SOC_PCIEPHY_CTRL2_ADDR         0x008
> +#define SOC_PCIEPHY_CTRL3_ADDR         0x00c
> +#define PCIE_ELBI_SLV_DBI_ENABLE       (0x1 << 21)
> +
> +/* info located in APB */
> +#define PCIE_APP_LTSSM_ENABLE  0x01c
> +#define PCIE_APB_PHY_CTRL0     0x0
> +#define PCIE_APB_PHY_CTRL1     0x4
> +#define PCIE_APB_PHY_STATUS0   0x400
> +#define PCIE_LINKUP_ENABLE     (0x8020)
> +#define PCIE_LTSSM_ENABLE_BIT  (0x1 << 11)
> +#define PIPE_CLK_STABLE                (0x1 << 19)
> +#define PHY_REF_PAD_BIT                (0x1 << 8)
> +#define PHY_PWR_DOWN_BIT       (0x1 << 22)
> +#define PHY_RST_ACK_BIT                (0x1 << 16)
> +
> +/* info located in sysctrl */
> +#define SCTRL_PCIE_CMOS_OFFSET 0x60
> +#define SCTRL_PCIE_CMOS_BIT    0x10
> +#define SCTRL_PCIE_ISO_OFFSET  0x44
> +#define SCTRL_PCIE_ISO_BIT     0x30
> +#define SCTRL_PCIE_HPCLK_OFFSET        0x190
> +#define SCTRL_PCIE_HPCLK_BIT   0x184000
> +#define SCTRL_PCIE_OE_OFFSET   0x14a
> +#define PCIE_DEBOUNCE_PARAM    0xF0F400
> +#define PCIE_OE_BYPASS         (0x3 << 28)
> +
> +/* peri_crg ctrl */
> +#define CRGCTRL_PCIE_ASSERT_OFFSET     0x88
> +#define CRGCTRL_PCIE_ASSERT_BIT                0x8c000000
> +
> +/* Time for delay */
> +#define REF_2_PERST_MIN                20000
> +#define REF_2_PERST_MAX                25000
> +#define PERST_2_ACCESS_MIN     10000
> +#define PERST_2_ACCESS_MAX     12000
> +#define LINK_WAIT_MIN          900
> +#define LINK_WAIT_MAX          1000
> +#define PIPE_CLK_WAIT_MIN      550
> +#define PIPE_CLK_WAIT_MAX      600
> +#define TIME_CMOS_MIN          100
> +#define TIME_CMOS_MAX          105
> +#define TIME_PHY_PD_MIN                10
> +#define TIME_PHY_PD_MAX                11
> +
> +struct kirin_pcie {
> +       struct dw_pcie  *pci;
> +       void __iomem    *apb_base;
> +       void __iomem    *phy_base;
> +       struct regmap   *crgctrl;
> +       struct regmap   *sysctrl;
> +       struct clk      *apb_sys_clk;
> +       struct clk      *apb_phy_clk;
> +       struct clk      *phy_ref_clk;
> +       struct clk      *pcie_aclk;
> +       struct clk      *pcie_aux_clk;
> +       int             gpio_id_reset;
> +};
> +
> +/* Registers in PCIeCTRL */
> +static inline void kirin_apb_ctrl_writel(struct kirin_pcie *kirin_pcie,
> +                                        u32 val, u32 reg)
> +{
> +       writel(val, kirin_pcie->apb_base + reg);
> +}
> +
> +static inline u32 kirin_apb_ctrl_readl(struct kirin_pcie *kirin_pcie, u32 reg)
> +{
> +       return readl(kirin_pcie->apb_base + reg);
> +}
> +
> +/* Registers in PCIePHY */
> +static inline void kirin_apb_phy_writel(struct kirin_pcie *kirin_pcie,
> +                                       u32 val, u32 reg)
> +{
> +       writel(val, kirin_pcie->phy_base + reg);
> +}
> +
> +static inline u32 kirin_apb_phy_readl(struct kirin_pcie *kirin_pcie, u32 reg)
> +{
> +       return readl(kirin_pcie->phy_base + reg);
> +}
> +
> +static long kirin_pcie_get_clk(struct kirin_pcie *kirin_pcie,
> +                              struct platform_device *pdev)
> +{
> +       struct device *dev = &pdev->dev;
> +
> +       kirin_pcie->phy_ref_clk = devm_clk_get(dev, "pcie_phy_ref");
> +       if (IS_ERR(kirin_pcie->phy_ref_clk))
> +               return PTR_ERR(kirin_pcie->phy_ref_clk);
> +
> +       kirin_pcie->pcie_aux_clk = devm_clk_get(dev, "pcie_aux");
> +       if (IS_ERR(kirin_pcie->pcie_aux_clk))
> +               return PTR_ERR(kirin_pcie->pcie_aux_clk);
> +
> +       kirin_pcie->apb_phy_clk = devm_clk_get(dev, "pcie_apb_phy");
> +       if (IS_ERR(kirin_pcie->apb_phy_clk))
> +               return PTR_ERR(kirin_pcie->apb_phy_clk);
> +
> +       kirin_pcie->apb_sys_clk = devm_clk_get(dev, "pcie_apb_sys");
> +       if (IS_ERR(kirin_pcie->apb_sys_clk))
> +               return PTR_ERR(kirin_pcie->apb_sys_clk);
> +
> +       kirin_pcie->pcie_aclk = devm_clk_get(dev, "pcie_aclk");
> +       if (IS_ERR(kirin_pcie->pcie_aclk))
> +               return PTR_ERR(kirin_pcie->pcie_aclk);
> +
> +       return 0;
> +}
> +
> +static long kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie,
> +                                   struct platform_device *pdev)
> +{
> +       struct resource *apb;
> +       struct resource *phy;
> +       struct resource *dbi;
> +       struct device *dev = &pdev->dev;
> +
> +       apb = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apb");
> +       kirin_pcie->apb_base = devm_ioremap_resource(dev, apb);
> +       if (IS_ERR(kirin_pcie->apb_base))
> +               return PTR_ERR(kirin_pcie->apb_base);
> +
> +       phy = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
> +       kirin_pcie->phy_base = devm_ioremap_resource(dev, phy);
> +       if (IS_ERR(kirin_pcie->phy_base))
> +               return PTR_ERR(kirin_pcie->phy_base);
> +
> +       dbi = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
> +       kirin_pcie->pci->dbi_base = devm_ioremap_resource(dev, dbi);
> +       if (IS_ERR(kirin_pcie->pci->dbi_base))
> +               return PTR_ERR(kirin_pcie->pci->dbi_base);
> +
> +       kirin_pcie->crgctrl =
> +               syscon_regmap_lookup_by_compatible("hisilicon,hi3660-crgctrl");
> +       if (IS_ERR(kirin_pcie->crgctrl))
> +               return PTR_ERR(kirin_pcie->crgctrl);
> +
> +       kirin_pcie->sysctrl =
> +               syscon_regmap_lookup_by_compatible("hisilicon,hi3660-sctrl");
> +       if (IS_ERR(kirin_pcie->sysctrl))
> +               return PTR_ERR(kirin_pcie->sysctrl);
> +
> +       return 0;
> +}
> +
> +static int kirin_pcie_phy_init(struct kirin_pcie *kirin_pcie)
> +{
> +       u32 reg_val;
> +       struct device *dev = kirin_pcie->pci->dev;
> +
> +       reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL1);
> +       reg_val &= ~PHY_REF_PAD_BIT;
> +       kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL1);
> +
> +       reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL0);
> +       reg_val &= ~PHY_PWR_DOWN_BIT;
> +       kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL0);
> +       usleep_range(TIME_PHY_PD_MIN, TIME_PHY_PD_MAX);
> +
> +       reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL1);
> +       reg_val &= ~PHY_RST_ACK_BIT;
> +       kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL1);
> +
> +       usleep_range(PIPE_CLK_WAIT_MIN, PIPE_CLK_WAIT_MAX);
> +       reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_STATUS0);
> +       if (reg_val & PIPE_CLK_STABLE) {
> +               dev_err(dev, "PIPE clk is not stable\n");
> +               return -EINVAL;
> +       }
> +
> +       return 0;
> +}
> +
> +static void kirin_pcie_oe_enable(struct kirin_pcie *kirin_pcie)
> +{
> +       u32 val;
> +
> +       regmap_read(kirin_pcie->sysctrl, SCTRL_PCIE_OE_OFFSET, &val);
> +       val |= PCIE_DEBOUNCE_PARAM;
> +       val &= ~PCIE_OE_BYPASS;
> +       regmap_write(kirin_pcie->sysctrl, SCTRL_PCIE_OE_OFFSET, val);
> +}
> +
> +static int kirin_pcie_clk_ctrl(struct kirin_pcie *kirin_pcie, bool enable)
> +{
> +       int ret = 0;
> +
> +       if (!enable)
> +               goto close_clk;
> +
> +       ret = clk_set_rate(kirin_pcie->phy_ref_clk, REF_CLK_FREQ);
> +       if (ret)
> +               return ret;
> +
> +       ret = clk_prepare_enable(kirin_pcie->phy_ref_clk);
> +       if (ret)
> +               return ret;
> +
> +       ret = clk_prepare_enable(kirin_pcie->apb_sys_clk);
> +       if (ret)
> +               goto apb_sys_fail;
> +
> +       ret = clk_prepare_enable(kirin_pcie->apb_phy_clk);
> +       if (ret)
> +               goto apb_phy_fail;
> +
> +       ret = clk_prepare_enable(kirin_pcie->pcie_aclk);
> +       if (ret)
> +               goto aclk_fail;
> +
> +       ret = clk_prepare_enable(kirin_pcie->pcie_aux_clk);
> +       if (ret)
> +               goto aux_clk_fail;
> +
> +       return 0;
> +
> +close_clk:
> +       clk_disable_unprepare(kirin_pcie->pcie_aux_clk);
> +aux_clk_fail:
> +       clk_disable_unprepare(kirin_pcie->pcie_aclk);
> +aclk_fail:
> +       clk_disable_unprepare(kirin_pcie->apb_phy_clk);
> +apb_phy_fail:
> +       clk_disable_unprepare(kirin_pcie->apb_sys_clk);
> +apb_sys_fail:
> +       clk_disable_unprepare(kirin_pcie->phy_ref_clk);
> +
> +       return ret;
> +}
> +
> +static int kirin_pcie_power_on(struct kirin_pcie *kirin_pcie)
> +{
> +       int ret;
> +
> +       /* Power supply for Host */
> +       regmap_write(kirin_pcie->sysctrl,
> +                    SCTRL_PCIE_CMOS_OFFSET, SCTRL_PCIE_CMOS_BIT);
> +       usleep_range(TIME_CMOS_MIN, TIME_CMOS_MAX);
> +       kirin_pcie_oe_enable(kirin_pcie);
> +
> +       ret = kirin_pcie_clk_ctrl(kirin_pcie, true);
> +       if (ret)
> +               return ret;
> +
> +       /* ISO disable, PCIeCtrl, PHY assert and clk gate clear */
> +       regmap_write(kirin_pcie->sysctrl,
> +                    SCTRL_PCIE_ISO_OFFSET, SCTRL_PCIE_ISO_BIT);
> +       regmap_write(kirin_pcie->crgctrl,
> +                    CRGCTRL_PCIE_ASSERT_OFFSET, CRGCTRL_PCIE_ASSERT_BIT);
> +       regmap_write(kirin_pcie->sysctrl,
> +                    SCTRL_PCIE_HPCLK_OFFSET, SCTRL_PCIE_HPCLK_BIT);
> +
> +       ret = kirin_pcie_phy_init(kirin_pcie);
> +       if (ret)
> +               goto close_clk;
> +
> +       /* perst assert Endpoint */
> +       if (!gpio_request(kirin_pcie->gpio_id_reset, "pcie_perst")) {
> +               usleep_range(REF_2_PERST_MIN, REF_2_PERST_MAX);
> +               ret = gpio_direction_output(kirin_pcie->gpio_id_reset, 1);
> +               if (ret)
> +                       goto close_clk;
> +               usleep_range(PERST_2_ACCESS_MIN, PERST_2_ACCESS_MAX);
> +
> +               return 0;
> +       }
> +
> +close_clk:
> +       kirin_pcie_clk_ctrl(kirin_pcie, false);
> +       return ret;
> +}
> +
> +static void kirin_pcie_sideband_dbi_w_mode(struct kirin_pcie *kirin_pcie,
> +                                          bool on)
> +{
> +       u32 val;
> +
> +       val = kirin_apb_ctrl_readl(kirin_pcie, SOC_PCIECTRL_CTRL0_ADDR);
> +       if (on)
> +               val = val | PCIE_ELBI_SLV_DBI_ENABLE;
> +       else
> +               val = val & ~PCIE_ELBI_SLV_DBI_ENABLE;
> +
> +       kirin_apb_ctrl_writel(kirin_pcie, val, SOC_PCIECTRL_CTRL0_ADDR);
> +}
> +
> +static void kirin_pcie_sideband_dbi_r_mode(struct kirin_pcie *kirin_pcie,
> +                                          bool on)
> +{
> +       u32 val;
> +
> +       val = kirin_apb_ctrl_readl(kirin_pcie, SOC_PCIECTRL_CTRL1_ADDR);
> +       if (on)
> +               val = val | PCIE_ELBI_SLV_DBI_ENABLE;
> +       else
> +               val = val & ~PCIE_ELBI_SLV_DBI_ENABLE;
> +
> +       kirin_apb_ctrl_writel(kirin_pcie, val, SOC_PCIECTRL_CTRL1_ADDR);
> +}
> +
> +static int kirin_pcie_rd_own_conf(struct pcie_port *pp,
> +                                 int where, int size, u32 *val)
> +{
> +       struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> +       struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
> +       int ret;
> +
> +       kirin_pcie_sideband_dbi_r_mode(kirin_pcie, true);
> +       ret = dw_pcie_read(pci->dbi_base + where, size, val);
> +       kirin_pcie_sideband_dbi_r_mode(kirin_pcie, false);
> +
> +       return ret;
> +}
> +
> +static int kirin_pcie_wr_own_conf(struct pcie_port *pp,
> +                                 int where, int size, u32 val)
> +{
> +       struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> +       struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
> +       int ret;
> +
> +       kirin_pcie_sideband_dbi_w_mode(kirin_pcie, true);
> +       ret = dw_pcie_write(pci->dbi_base + where, size, val);
> +       kirin_pcie_sideband_dbi_w_mode(kirin_pcie, false);
> +
> +       return ret;
> +}
> +
> +static u32 kirin_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base,
> +                              u32 reg, size_t size)
> +{
> +       struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
> +       u32 ret;
> +
> +       kirin_pcie_sideband_dbi_r_mode(kirin_pcie, true);
> +       dw_pcie_read(base + reg, size, &ret);
> +       kirin_pcie_sideband_dbi_r_mode(kirin_pcie, false);
> +
> +       return ret;
> +}
> +
> +static void kirin_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base,
> +                                u32 reg, size_t size, u32 val)
> +{
> +       struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
> +
> +       kirin_pcie_sideband_dbi_w_mode(kirin_pcie, true);
> +       dw_pcie_write(base + reg, size, val);
> +       kirin_pcie_sideband_dbi_w_mode(kirin_pcie, false);
> +}
> +
> +static int kirin_pcie_link_up(struct dw_pcie *pci)
> +{
> +       struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
> +       u32 val = kirin_apb_ctrl_readl(kirin_pcie, PCIE_APB_PHY_STATUS0);
> +
> +       if ((val & PCIE_LINKUP_ENABLE) == PCIE_LINKUP_ENABLE)
> +               return 1;
> +
> +       return 0;
> +}
> +
> +static int kirin_pcie_establish_link(struct pcie_port *pp)
> +{
> +       struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> +       struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
> +       struct device *dev = kirin_pcie->pci->dev;
> +       int count = 0;
> +
> +       if (kirin_pcie_link_up(pci))
> +               return 0;
> +
> +       dw_pcie_setup_rc(pp);
> +
> +       /* assert LTSSM enable */
> +       kirin_apb_ctrl_writel(kirin_pcie, PCIE_LTSSM_ENABLE_BIT,
> +                             PCIE_APP_LTSSM_ENABLE);
> +
> +       /* check if the link is up or not */
> +       while (!kirin_pcie_link_up(pci)) {
> +               usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX);
> +               count++;
> +               if (count == 1000) {
> +                       dev_err(dev, "Link Fail\n");
> +                       return -EINVAL;
> +               }
> +       }
> +
> +       return 0;
> +}
> +
> +static void kirin_pcie_host_init(struct pcie_port *pp)
> +{
> +       kirin_pcie_establish_link(pp);
> +}
> +
> +static struct dw_pcie_ops kirin_dw_pcie_ops = {
> +       .read_dbi = kirin_pcie_read_dbi,
> +       .write_dbi = kirin_pcie_write_dbi,
> +       .link_up = kirin_pcie_link_up,
> +};
> +
> +static struct dw_pcie_host_ops kirin_pcie_host_ops = {
> +       .rd_own_conf = kirin_pcie_rd_own_conf,
> +       .wr_own_conf = kirin_pcie_wr_own_conf,
> +       .host_init = kirin_pcie_host_init,
> +};
> +
> +static int __init kirin_add_pcie_port(struct dw_pcie *pci,
> +                                     struct platform_device *pdev)
> +{
> +       pci->pp.ops = &kirin_pcie_host_ops;
> +
> +       return dw_pcie_host_init(&pci->pp);
> +}
> +
> +static int kirin_pcie_probe(struct platform_device *pdev)
> +{
> +       struct kirin_pcie *kirin_pcie;
> +       struct dw_pcie *pci;
> +       struct device *dev = &pdev->dev;
> +       int ret;
> +
> +       if (!dev->of_node) {
> +               dev_err(dev, "NULL node\n");
> +               return -EINVAL;
> +       }
> +
> +       kirin_pcie = devm_kzalloc(dev, sizeof(struct kirin_pcie), GFP_KERNEL);
> +       if (!kirin_pcie)
> +               return -ENOMEM;
> +
> +       pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
> +       if (!pci)
> +               return -ENOMEM;
> +
> +       pci->dev = dev;
> +       pci->ops = &kirin_dw_pcie_ops;
> +       kirin_pcie->pci = pci;
> +
> +       ret = kirin_pcie_get_clk(kirin_pcie, pdev);
> +       if (ret)
> +               return ret;
> +
> +       ret = kirin_pcie_get_resource(kirin_pcie, pdev);
> +       if (ret)
> +               return ret;
> +
> +       kirin_pcie->gpio_id_reset = of_get_named_gpio(dev->of_node,
> +                                                     "reset-gpio", 0);
> +       if (kirin_pcie->gpio_id_reset < 0)
> +               return -ENODEV;
> +
> +       ret = kirin_pcie_power_on(kirin_pcie);
> +       if (ret)
> +               return ret;
> +
> +       platform_set_drvdata(pdev, kirin_pcie);
> +
> +       return kirin_add_pcie_port(pci, pdev);
> +}
> +
> +static const struct of_device_id kirin_pcie_match[] = {
> +       { .compatible = "hisilicon,kirin960-pcie" },
> +       {},
> +};
> +
> +struct platform_driver kirin_pcie_driver = {
> +       .probe                  = kirin_pcie_probe,
> +       .driver                 = {
> +               .name                   = "kirin-pcie",
> +               .of_match_table = kirin_pcie_match,
> +               .suppress_bind_attrs = true,
> +       },
> +};
> +
> +builtin_platform_driver(kirin_pcie_driver);
> --
> 2.11.GIT
>

Re: [PATCH v11 0/3]add PCIe driver for Kirin PCIe

[Bjorn Helgaas]

[+cc Catalin, Will, linux-arm-kernel]

Applied patches 2 & 3 to pci/host-kirin for v4.13.

I would like a MAINTAINERS update, too.  If you send me that, I'll
squash it into the driver patch.

Catalin, Will, how do you want to handle the
arch/arm64/configs/defconfig change (patch 3)?  It's currently on my
branch, but I'm happy to drop it if another route is better.

On Mon, Jun 19, 2017 at 06:23:46PM +0800, Xiaowei Song wrote:
> Before Version Patches
> ======================
> patch v9
> http://www.spinics.net/lists/linux-pci/msg61821.html
> patch V8
> http://www.spinics.net/lists/linux-pci/msg61715.html
> patch V7
> https://www.spinics.net/lists/linux-pci/msg61664.html
> patch V6
> https://www.spinics.net/lists/linux-pci/msg61610.html
> 
> patch V4
> https://www.spinics.net/lists/linux-pci/msg61406.html
> 
> patch V3
> https://www.spinics.net/lists/linux-pci/msg61399.html
> 
> Changes between V11 and V9
> ========================
> 1. Fix the indent issues according to the review comments from Bjorn:
>    (1) The value of reg is right-aligned in both dtsi file and Documentation file.
>    (2) Re-indent the space of macro defination pointed out by Bjorn.
>    (3) Adjust the space in 'struct kirin_pcie' defination.
>    (4) Use dev replace of pdev->dev in function  kirin_pcie_get_clk and kirin_pcie_get_resource.
>    (5) Aligned params with '(' in function kirin_apb_ctrl_writel and several others.
> 2. Fix the issues that compitable value in Documentation was different with .dtsi file.
> 3. For dependance during compiling, the dtsi patch is deleted, and it was merged in patch[1].
> 4. The indent style issues will be pull with MSI-patch in the next weeks;
> 
> patch[1]: https://www.spinics.net/lists/arm-kernel/msg588944.html
> 
> =========================
> Changes between V8 and V7
> =========================
> 1. Fix the indent issues in Documentation, dtsi file and macro defination.
> 2. Replace pdev->dev with dev in kirin_pcie_get_resource and 
>    kirin_pcie_get_clk functions.
> 3. Put variables "pci" and "kirin_pcie" to be initialized at first
>    in kirin_pcie_wr_own_config, kirin_pcie_read_dbi and other functions.
> 4. Add space before blankets in "Low power mode(L1 ".
> 5. Short the Makefile sentence to lower than 80 characters
>    and delete reduntant words.
> 6. Use word 'located' instead of the wrong one 'lacated'.
> 7. Fix the problem of return value type.
> 
> Changes between V8 and V7
> =========================
> 1. Replace 'reset-gpios' of 'reset-gpio' in Documentation.
> 
> Changes between V7 and V6
> =========================
> 1. add enumeration log Based on Hikey960 Board with these patches.
> 2. fix issues as fellows:
>    (1) delete reduntant blankets in macro defination,
>    (2) add blank line in  kirin_pcie_clk_ctrl function.
>    (3) Fix compitable property in DT with the SoC name,
>        for example "hisilicon,kirin960-pcie".
> 
> Changes between V6 and V4
> =========================
> 1. seperate Document from .dtsi patch.
> 2. fix issues according to review comments
>    from Bjorn Helgaas and Rob Herring: annotation stype, DT node,
>    patch post method and so on.
> 
> Enumeration log
> ===============
> These test logs come from patches running on Hikey960 Board
> (1) Connect with Atheros Communications WIFI
> 	OF: PCI: host bridge /soc/kirin_pcie_rc@f4000000 ranges:
> 	OF: PCI:   MEM 0xf6000000..0xf7ffffff -> 0x00000000
> 	kirin-pcie f4000000.kirin_pcie_rc: PCI host bridge to bus 0000:00
> 	pci_bus 0000:00: root bus resource [bus 00-01]
> 	pci_bus 0000:00: root bus resource [mem 0xf6000000-0xf7ffffff] (bus address [0x00000000-0x01ffffff])
> 	pci 0000:00:00.0: [19e5:3660] type 01 class 0x060400
> 	pci 0000:00:00.0: reg 0x10: [mem 0xf6000000-0xf6ffffff]
> 	pci 0000:00:00.0: supports D1 D2
> 	pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot
> 	pci 0000:01:00.0: [168c:002a] type 00 class 0x028000
> 	pci 0000:01:00.0: reg 0x10: [mem 0xf6000000-0xf600ffff 64bit]
> 	pci 0000:01:00.0: supports D1
> 	pci 0000:01:00.0: PME# supported from D0 D1 D3hot
> 	pci 0000:01:00.0: disabling ASPM on pre-1.1 PCIe device.  You can enable it with 'pcie_aspm=force'
> 	pci 0000:00:00.0: BAR 0: assigned [mem 0xf6000000-0xf6ffffff]
> 	pci 0000:00:00.0: BAR 14: assigned [mem 0xf7000000-0xf70fffff]
> 	pci 0000:01:00.0: BAR 0: assigned [mem 0xf7000000-0xf700ffff 64bit]
> 	pci 0000:00:00.0: PCI bridge to [bus 01]
> 	pci 0000:00:00.0:   bridge window [mem 0xf7000000-0xf70fffff]
> 	pcieport 0000:00:00.0: Signaling PME with IRQ 276
> 	pcieport 0000:00:00.0: AER enabled with IRQ 276	 
> 
> 
> Xiaowei Song (3):
>   PCI: hisi: Add DT binding for PCIe of Kirin SoC series
>   PCI: dwc: kirin: add PCIe Driver for HiSilicon Kirin SoC
>   ARM4: defconfig: Enable  Kirin PCIe
> 
>  .../devicetree/bindings/pci/kirin-pcie.txt         |  55 +++
>  arch/arm64/configs/defconfig                       |   1 +
>  drivers/pci/dwc/Kconfig                            |  10 +
>  drivers/pci/dwc/Makefile                           |   1 +
>  drivers/pci/dwc/pcie-kirin.c                       | 518 +++++++++++++++++++++
>  5 files changed, 585 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txt
>  create mode 100644 drivers/pci/dwc/pcie-kirin.c
> 
> -- 
> 2.11.GIT
> 

Re: [PATCH v11 0/3]add PCIe driver for Kirin PCIe

[Will Deacon]

On Sun, Jul 02, 2017 at 06:36:57PM -0500, Bjorn Helgaas wrote:
> [+cc Catalin, Will, linux-arm-kernel]
> 
> Applied patches 2 & 3 to pci/host-kirin for v4.13.
> 
> I would like a MAINTAINERS update, too.  If you send me that, I'll
> squash it into the driver patch.
> 
> Catalin, Will, how do you want to handle the
> arch/arm64/configs/defconfig change (patch 3)?  It's currently on my
> branch, but I'm happy to drop it if another route is better.

defconfig updates usually go through arm-soc, via the relevant platform
maintainer, so it would be best to follow that route here too otherwise
you'll probably see conflicts in -next.

Will

Re: [PATCH v11 0/3]add PCIe driver for Kirin PCIe

[Bjorn Helgaas]

On Mon, Jul 03, 2017 at 11:47:27AM +0100, Will Deacon wrote:
> On Sun, Jul 02, 2017 at 06:36:57PM -0500, Bjorn Helgaas wrote:
> > [+cc Catalin, Will, linux-arm-kernel]
> > 
> > Applied patches 2 & 3 to pci/host-kirin for v4.13.
> > 
> > I would like a MAINTAINERS update, too.  If you send me that, I'll
> > squash it into the driver patch.
> > 
> > Catalin, Will, how do you want to handle the
> > arch/arm64/configs/defconfig change (patch 3)?  It's currently on my
> > branch, but I'm happy to drop it if another route is better.
> 
> defconfig updates usually go through arm-soc, via the relevant platform
> maintainer, so it would be best to follow that route here too otherwise
> you'll probably see conflicts in -next.

OK, dropped the defconfig change and updated my -next branch.

I'm still looking for a MAINTAINERS update.

Re: [PATCH v11 0/3]add PCIe driver for Kirin PCIe

[Guodong Xu]

Hi, Xu Wei



On Mon, Jul 3, 2017 at 6:47 PM, Will Deacon <will.deacon@arm.com> wrote:
> On Sun, Jul 02, 2017 at 06:36:57PM -0500, Bjorn Helgaas wrote:
>> [+cc Catalin, Will, linux-arm-kernel]
>>
>> Applied patches 2 & 3 to pci/host-kirin for v4.13.
>>
>> I would like a MAINTAINERS update, too.  If you send me that, I'll
>> squash it into the driver patch.
>>
>> Catalin, Will, how do you want to handle the
>> arch/arm64/configs/defconfig change (patch 3)?  It's currently on my
>> branch, but I'm happy to drop it if another route is better.
>
> defconfig updates usually go through arm-soc, via the relevant platform
> maintainer, so it would be best to follow that route here too otherwise
> you'll probably see conflicts in -next.
>

Is it ok for you to pick up the arch/arm64/configs/defconfig change (patch 3)?

-Guodong

> Will

Re: [PATCH v11 0/3]add PCIe driver for Kirin PCIe

[Wei Xu]

Hi Guodong,

On 2017/7/3 14:04, Guodong Xu wrote:
> Hi, Xu Wei
> 
> 
> 
> On Mon, Jul 3, 2017 at 6:47 PM, Will Deacon <will.deacon@arm.com> wrote:
>> On Sun, Jul 02, 2017 at 06:36:57PM -0500, Bjorn Helgaas wrote:
>>> [+cc Catalin, Will, linux-arm-kernel]
>>>
>>> Applied patches 2 & 3 to pci/host-kirin for v4.13.
>>>
>>> I would like a MAINTAINERS update, too.  If you send me that, I'll
>>> squash it into the driver patch.
>>>
>>> Catalin, Will, how do you want to handle the
>>> arch/arm64/configs/defconfig change (patch 3)?  It's currently on my
>>> branch, but I'm happy to drop it if another route is better.
>>
>> defconfig updates usually go through arm-soc, via the relevant platform
>> maintainer, so it would be best to follow that route here too otherwise
>> you'll probably see conflicts in -next.
>>
> 
> Is it ok for you to pick up the arch/arm64/configs/defconfig change (patch 3)?

Since it is already 4.12-rc7, I will pick up it and queue for the v4.14.
Are you fine about that?
Thanks!

Best Regards,
Wei

> 
> -Guodong
> 
>> Will
> 
> .
> 

Re: [PATCH v11 0/3]add PCIe driver for Kirin PCIe

[Guodong Xu]

On Mon, Jul 3, 2017 at 9:32 PM, Wei Xu <xuwei5@hisilicon.com> wrote:
> Hi Guodong,
>
> On 2017/7/3 14:04, Guodong Xu wrote:
>> Hi, Xu Wei
>>
>>
>>
>> On Mon, Jul 3, 2017 at 6:47 PM, Will Deacon <will.deacon@arm.com> wrote:
>>> On Sun, Jul 02, 2017 at 06:36:57PM -0500, Bjorn Helgaas wrote:
>>>> [+cc Catalin, Will, linux-arm-kernel]
>>>>
>>>> Applied patches 2 & 3 to pci/host-kirin for v4.13.
>>>>
>>>> I would like a MAINTAINERS update, too.  If you send me that, I'll
>>>> squash it into the driver patch.
>>>>
>>>> Catalin, Will, how do you want to handle the
>>>> arch/arm64/configs/defconfig change (patch 3)?  It's currently on my
>>>> branch, but I'm happy to drop it if another route is better.
>>>
>>> defconfig updates usually go through arm-soc, via the relevant platform
>>> maintainer, so it would be best to follow that route here too otherwise
>>> you'll probably see conflicts in -next.
>>>
>>
>> Is it ok for you to pick up the arch/arm64/configs/defconfig change (patch 3)?
>
> Since it is already 4.12-rc7, I will pick up it and queue for the v4.14.
> Are you fine about that?
> Thanks!

Sure.

>
> Best Regards,
> Wei
>
>>
>> -Guodong
>>
>>> Will
>>
>> .
>>
>

Re: [PATCH v11 0/3]add PCIe driver for Kirin PCIe

[Wei Xu]

Hi Guodong,

On 2017/7/4 3:03, Guodong Xu wrote:
> On Mon, Jul 3, 2017 at 9:32 PM, Wei Xu <xuwei5@hisilicon.com> wrote:
>> Hi Guodong,
>>
>> On 2017/7/3 14:04, Guodong Xu wrote:
>>> Hi, Xu Wei
>>>
>>>
>>>
>>> On Mon, Jul 3, 2017 at 6:47 PM, Will Deacon <will.deacon@arm.com> wrote:
>>>> On Sun, Jul 02, 2017 at 06:36:57PM -0500, Bjorn Helgaas wrote:
>>>>> [+cc Catalin, Will, linux-arm-kernel]
>>>>>
>>>>> Applied patches 2 & 3 to pci/host-kirin for v4.13.
>>>>>
>>>>> I would like a MAINTAINERS update, too.  If you send me that, I'll
>>>>> squash it into the driver patch.
>>>>>
>>>>> Catalin, Will, how do you want to handle the
>>>>> arch/arm64/configs/defconfig change (patch 3)?  It's currently on my
>>>>> branch, but I'm happy to drop it if another route is better.
>>>>
>>>> defconfig updates usually go through arm-soc, via the relevant platform
>>>> maintainer, so it would be best to follow that route here too otherwise
>>>> you'll probably see conflicts in -next.
>>>>
>>>
>>> Is it ok for you to pick up the arch/arm64/configs/defconfig change (patch 3)?
>>
>> Since it is already 4.12-rc7, I will pick up it and queue for the v4.14.
>> Are you fine about that?
>> Thanks!
> 
> Sure.

Applied the patch 3 into the hisilicon defconfig tree.

BR,
Wei

> 
>>
>> Best Regards,
>> Wei
>>
>>>
>>> -Guodong
>>>
>>>> Will
>>>
>>> .
>>>
>>
> 
> .
>