[PATCH 0/2] Allwinner H5 IRQ fixes

[PATCH 0/2] Allwinner H5 IRQ fixes

[Icenowy Zheng]

The current pinctrl code and H5 device tree have an error: the bank number
of IRQs are wrongly set to 2, which makes PG bank interrupts not usable.

Fixes in both the pinctrl driver and the device tree.

Please apply the DT fix after applying the pinctrl fix.

Icenowy Zheng (2):
  pinctrl: sunxi: fix wrong irq_banks number for H5 pinctrl
  arm64: allwinner: h5: fix pinctrl IRQs

 arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi |  3 +++
 drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c    | 26 +++++++++++++++++++++++---
 2 files changed, 26 insertions(+), 3 deletions(-)

-- 
2.13.0

[PATCH 1/2] pinctrl: sunxi: fix wrong irq_banks number for H5 pinctrl

[Icenowy Zheng]

The pin controller of Allwinner H5 has three IRQ banks, however in old
versions of drivers and device trees, only two are set, which makes
PG bank IRQ not available.

If it's directly set to 3, the old device trees will fail to boot.

Add a workaround (and a warning) for older device trees, and allow new
device trees to use correct 3 IRQ banks.

Fixes: 838adb576d4a ("drivers: pinctrl: add driver for Allwinner H5 SoC")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c | 26 +++++++++++++++++++++++---
 1 file changed, 23 insertions(+), 3 deletions(-)

diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c
index ccf9419e9418..97b48336f84a 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c
@@ -19,6 +19,7 @@
 #include <linux/platform_device.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
+#include <linux/of_irq.h>
 #include <linux/pinctrl/pinctrl.h>
 
 #include "pinctrl-sunxi.h"
@@ -530,17 +531,36 @@ static const struct sunxi_desc_pin sun50i_h5_pins[] = {
 		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)),	/* PG_EINT13 */
 };
 
-static const struct sunxi_pinctrl_desc sun50i_h5_pinctrl_data = {
+static const struct sunxi_pinctrl_desc sun50i_h5_pinctrl_data_broken = {
 	.pins = sun50i_h5_pins,
 	.npins = ARRAY_SIZE(sun50i_h5_pins),
 	.irq_banks = 2,
 	.irq_read_needs_mux = true
 };
 
+static const struct sunxi_pinctrl_desc sun50i_h5_pinctrl_data = {
+	.pins = sun50i_h5_pins,
+	.npins = ARRAY_SIZE(sun50i_h5_pins),
+	.irq_banks = 3,
+	.irq_read_needs_mux = true
+};
+
 static int sun50i_h5_pinctrl_probe(struct platform_device *pdev)
 {
-	return sunxi_pinctrl_init(pdev,
-				  &sun50i_h5_pinctrl_data);
+	switch (of_irq_count(pdev->dev.of_node)) {
+	case 2:
+		dev_warn(&pdev->dev,
+			 "Your device tree's pinctrl node is broken, which has no IRQ of PG bank routed.\n");
+		dev_warn(&pdev->dev,
+			 "Please update the device tree, otherwise PG bank IRQ won't work.\n");
+		return sunxi_pinctrl_init(pdev,
+					  &sun50i_h5_pinctrl_data_broken);
+	case 3:
+		return sunxi_pinctrl_init(pdev,
+					  &sun50i_h5_pinctrl_data);
+	default:
+		return -EINVAL;
+	}
 }
 
 static const struct of_device_id sun50i_h5_pinctrl_match[] = {
-- 
2.13.0

[PATCH 2/2] arm64: allwinner: h5: fix pinctrl IRQs

[Icenowy Zheng]

The pin controller of H5 has three IRQs at the chip's GIC, which
represents three banks of pinctrl IRQs. However, the device tree used to
miss the third IRQ of the pin controller, which makes the PG bank IRQ
not usable.

Add the missing IRQ to the pinctrl node.

Fixes: 4e36de179f27 ("arm64: allwinner: h5: add Allwinner H5 .dtsi")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
index 732e2e06f503..d9a720bff05d 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
@@ -120,5 +120,8 @@
 };
 
 &pio {
+	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 	compatible = "allwinner,sun50i-h5-pinctrl";
 };
-- 
2.13.0

Re: [linux-sunxi] [PATCH 1/2] pinctrl: sunxi: fix wrong irq_banks number for H5 pinctrl

[Chen-Yu Tsai]

On Fri, Aug 11, 2017 at 10:27 PM, Icenowy Zheng <icenowy@aosc.io> wrote:
> The pin controller of Allwinner H5 has three IRQ banks, however in old
> versions of drivers and device trees, only two are set, which makes
> PG bank IRQ not available.
>
> If it's directly set to 3, the old device trees will fail to boot.
>
> Add a workaround (and a warning) for older device trees, and allow new
> device trees to use correct 3 IRQ banks.
>
> Fixes: 838adb576d4a ("drivers: pinctrl: add driver for Allwinner H5 SoC")
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

Acked-by: Chen-Yu Tsai <wens@csie.org>

Re: [linux-sunxi] [PATCH 2/2] arm64: allwinner: h5: fix pinctrl IRQs

[Chen-Yu Tsai]

On Fri, Aug 11, 2017 at 10:27 PM, Icenowy Zheng <icenowy@aosc.io> wrote:
> The pin controller of H5 has three IRQs at the chip's GIC, which
> represents three banks of pinctrl IRQs. However, the device tree used to
> miss the third IRQ of the pin controller, which makes the PG bank IRQ
> not usable.
>
> Add the missing IRQ to the pinctrl node.
>
> Fixes: 4e36de179f27 ("arm64: allwinner: h5: add Allwinner H5 .dtsi")
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

Applied as fixes for 4.13.

ChenYu

Re: [PATCH 1/2] pinctrl: sunxi: fix wrong irq_banks number for H5 pinctrl

[Linus Walleij]

On Fri, Aug 11, 2017 at 4:27 PM, Icenowy Zheng <icenowy@aosc.io> wrote:

> The pin controller of Allwinner H5 has three IRQ banks, however in old
> versions of drivers and device trees, only two are set, which makes
> PG bank IRQ not available.
>
> If it's directly set to 3, the old device trees will fail to boot.
>
> Add a workaround (and a warning) for older device trees, and allow new
> device trees to use correct 3 IRQ banks.
>
> Fixes: 838adb576d4a ("drivers: pinctrl: add driver for Allwinner H5 SoC")
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

Patch applied with Chen-Yu's ACK.

Yours,
Linus Walleij