* [PATCH v4 0/6] K2G: Add QSPI support
@ 2017-10-03 5:19 Vignesh R
2017-10-03 5:19 ` [PATCH v4 1/6] mtd: spi-nor: cadence-quadspi: Add TI 66AK2G SoC specific compatible Vignesh R
` (6 more replies)
0 siblings, 7 replies; 12+ messages in thread
From: Vignesh R @ 2017-10-03 5:19 UTC (permalink / raw)
To: Marek Vasut, Cyrille Pitchen
Cc: David Woodhouse, Brian Norris, Boris Brezillon, Rob Herring,
linux-mtd, devicetree, linux-kernel, Vignesh R, linux-arm-kernel
This series adds support for Cadence QSPI IP present in TI's 66AK2G SoC.
The patches enhance the existing cadence-quadspi driver to support
loopback clock circuit, pm_runtime support and tweaks for 66AK2G SoC.
Change log:
v4:
* New patch to fix error handling sequence in probe.
v3:
* Fix build warnings reported by kbuild test bot.
Resend:
* Rebase to latest linux-next.
* Collect Acked-bys
v2:
* Drop DT patches. Will be sent as separate series as requested by
maintainer.
* Split binding docs into separate patches.
* Address comments by Rob Herring.
Vignesh R (6):
mtd: spi-nor: cadence-quadspi: Add TI 66AK2G SoC specific compatible
mtd: spi-nor: cadence-quadspi: add a delay in write sequence
mtd: spi-nor: cadence-quadspi: Add new binding to enable loop-back
circuit
mtd: spi-nor: cadence-quadspi: Add support to enable loop-back clock
circuit
mtd: spi-nor: cadence-quadspi: Fix error path in probe
mtd: spi-nor: cadence-quadspi: Add runtime PM support
.../devicetree/bindings/mtd/cadence-quadspi.txt | 7 ++-
drivers/mtd/spi-nor/cadence-quadspi.c | 55 +++++++++++++++++++---
2 files changed, 55 insertions(+), 7 deletions(-)
--
2.14.1
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v4 1/6] mtd: spi-nor: cadence-quadspi: Add TI 66AK2G SoC specific compatible
2017-10-03 5:19 [PATCH v4 0/6] K2G: Add QSPI support Vignesh R
@ 2017-10-03 5:19 ` Vignesh R
2017-10-03 5:19 ` [PATCH v4 2/6] mtd: spi-nor: cadence-quadspi: add a delay in write sequence Vignesh R
` (5 subsequent siblings)
6 siblings, 0 replies; 12+ messages in thread
From: Vignesh R @ 2017-10-03 5:19 UTC (permalink / raw)
To: Marek Vasut, Cyrille Pitchen
Cc: David Woodhouse, Brian Norris, Boris Brezillon, Rob Herring,
linux-mtd, devicetree, linux-kernel, Vignesh R, linux-arm-kernel
Update binding documentation to add a new compatible for TI 66AK2G SoC,
to handle TI SoC specific quirks in the driver.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/mtd/cadence-quadspi.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
index f248056da24c..7dbe3bd9ac56 100644
--- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
+++ b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
@@ -1,7 +1,9 @@
* Cadence Quad SPI controller
Required properties:
-- compatible : Should be "cdns,qspi-nor".
+- compatible : should be one of the following:
+ Generic default - "cdns,qspi-nor".
+ For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
- reg : Contains two entries, each of which is a tuple consisting of a
physical address and length. The first entry is the address and
length of the controller register set. The second entry is the
--
2.14.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v4 2/6] mtd: spi-nor: cadence-quadspi: add a delay in write sequence
2017-10-03 5:19 [PATCH v4 0/6] K2G: Add QSPI support Vignesh R
2017-10-03 5:19 ` [PATCH v4 1/6] mtd: spi-nor: cadence-quadspi: Add TI 66AK2G SoC specific compatible Vignesh R
@ 2017-10-03 5:19 ` Vignesh R
2017-10-03 5:19 ` [PATCH v4 3/6] mtd: spi-nor: cadence-quadspi: Add new binding to enable loop-back circuit Vignesh R
` (4 subsequent siblings)
6 siblings, 0 replies; 12+ messages in thread
From: Vignesh R @ 2017-10-03 5:19 UTC (permalink / raw)
To: Marek Vasut, Cyrille Pitchen
Cc: David Woodhouse, Brian Norris, Boris Brezillon, Rob Herring,
linux-mtd, devicetree, linux-kernel, Vignesh R, linux-arm-kernel
As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access
Controller programming sequence, a delay equal to couple of QSPI master
clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and
writing data to the flash. Introduce a quirk flag CQSPI_NEEDS_WR_DELAY
to handle this and set this flag for TI 66AK2G SoC.
[1]http://www.ti.com/lit/ug/spruhy8f/spruhy8f.pdf
Signed-off-by: Vignesh R <vigneshr@ti.com>
---
drivers/mtd/spi-nor/cadence-quadspi.c | 27 ++++++++++++++++++++++++++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
index 53c7d8e0327a..5cd5d6f7303f 100644
--- a/drivers/mtd/spi-nor/cadence-quadspi.c
+++ b/drivers/mtd/spi-nor/cadence-quadspi.c
@@ -38,6 +38,9 @@
#define CQSPI_NAME "cadence-qspi"
#define CQSPI_MAX_CHIPSELECT 16
+/* Quirks */
+#define CQSPI_NEEDS_WR_DELAY BIT(0)
+
struct cqspi_st;
struct cqspi_flash_pdata {
@@ -76,6 +79,7 @@ struct cqspi_st {
u32 fifo_depth;
u32 fifo_width;
u32 trigger_address;
+ u32 wr_delay;
struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
};
@@ -608,6 +612,15 @@ static int cqspi_indirect_write_execute(struct spi_nor *nor,
reinit_completion(&cqspi->transfer_complete);
writel(CQSPI_REG_INDIRECTWR_START_MASK,
reg_base + CQSPI_REG_INDIRECTWR);
+ /*
+ * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
+ * Controller programming sequence, couple of cycles of
+ * QSPI_REF_CLK delay is required for the above bit to
+ * be internally synchronized by the QSPI module. Provide 5
+ * cycles of delay.
+ */
+ if (cqspi->wr_delay)
+ ndelay(cqspi->wr_delay);
while (remaining > 0) {
write_bytes = remaining > page_size ? page_size : remaining;
@@ -1156,6 +1169,7 @@ static int cqspi_probe(struct platform_device *pdev)
struct cqspi_st *cqspi;
struct resource *res;
struct resource *res_ahb;
+ unsigned long data;
int ret;
int irq;
@@ -1213,6 +1227,10 @@ static int cqspi_probe(struct platform_device *pdev)
}
cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
+ data = (unsigned long)of_device_get_match_data(dev);
+ if (data & CQSPI_NEEDS_WR_DELAY)
+ cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,
+ cqspi->master_ref_clk_hz);
ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
pdev->name, cqspi);
@@ -1284,7 +1302,14 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = {
#endif
static const struct of_device_id cqspi_dt_ids[] = {
- {.compatible = "cdns,qspi-nor",},
+ {
+ .compatible = "cdns,qspi-nor",
+ .data = (void *)0,
+ },
+ {
+ .compatible = "ti,k2g-qspi",
+ .data = (void *)CQSPI_NEEDS_WR_DELAY,
+ },
{ /* end of table */ }
};
--
2.14.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v4 3/6] mtd: spi-nor: cadence-quadspi: Add new binding to enable loop-back circuit
2017-10-03 5:19 [PATCH v4 0/6] K2G: Add QSPI support Vignesh R
2017-10-03 5:19 ` [PATCH v4 1/6] mtd: spi-nor: cadence-quadspi: Add TI 66AK2G SoC specific compatible Vignesh R
2017-10-03 5:19 ` [PATCH v4 2/6] mtd: spi-nor: cadence-quadspi: add a delay in write sequence Vignesh R
@ 2017-10-03 5:19 ` Vignesh R
2017-10-03 5:19 ` [PATCH v4 4/6] mtd: spi-nor: cadence-quadspi: Add support to enable loop-back clock circuit Vignesh R
` (3 subsequent siblings)
6 siblings, 0 replies; 12+ messages in thread
From: Vignesh R @ 2017-10-03 5:19 UTC (permalink / raw)
To: Marek Vasut, Cyrille Pitchen
Cc: David Woodhouse, Brian Norris, Boris Brezillon, Rob Herring,
linux-mtd, devicetree, linux-kernel, Vignesh R, linux-arm-kernel
Cadence QSPI IP has a adapted loop-back circuit which can be enabled by
setting BYPASS field to 0 in READCAPTURE register. It enables use of
QSPI return clock to latch the data rather than the internal QSPI
reference clock. For high speed operations, adapted loop-back circuit
using QSPI return clock helps to increase data valid window.
Add DT parameter cdns,rclk-en to help enable adapted loop-back circuit
for boards which do have QSPI return clock provided. Update binding
documentation for the same.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/mtd/cadence-quadspi.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
index 7dbe3bd9ac56..bb2075df9b38 100644
--- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
+++ b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
@@ -16,6 +16,9 @@ Required properties:
Optional properties:
- cdns,is-decoded-cs : Flag to indicate whether decoder is used or not.
+- cdns,rclk-en : Flag to indicate that QSPI return clock is used to latch
+ the read data rather than the QSPI clock. Make sure that QSPI return
+ clock is populated on the board before using this property.
Optional subnodes:
Subnodes of the Cadence Quad SPI controller are spi slave nodes with additional
--
2.14.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v4 4/6] mtd: spi-nor: cadence-quadspi: Add support to enable loop-back clock circuit
2017-10-03 5:19 [PATCH v4 0/6] K2G: Add QSPI support Vignesh R
` (2 preceding siblings ...)
2017-10-03 5:19 ` [PATCH v4 3/6] mtd: spi-nor: cadence-quadspi: Add new binding to enable loop-back circuit Vignesh R
@ 2017-10-03 5:19 ` Vignesh R
2017-10-03 5:19 ` [PATCH v4 5/6] mtd: spi-nor: cadence-quadspi: Fix error path in probe Vignesh R
` (2 subsequent siblings)
6 siblings, 0 replies; 12+ messages in thread
From: Vignesh R @ 2017-10-03 5:19 UTC (permalink / raw)
To: Marek Vasut, Cyrille Pitchen
Cc: David Woodhouse, Brian Norris, Boris Brezillon, Rob Herring,
linux-mtd, devicetree, linux-kernel, Vignesh R, linux-arm-kernel
Cadence QSPI IP has a adapted loop-back circuit which can be enabled by
setting BYPASS field to 0 in READCAPTURE register. It enables use of
QSPI return clock to latch the data rather than the internal QSPI
reference clock. For high speed operations, adapted loop-back circuit
using QSPI return clock helps to increase data valid window.
Based on DT parameter cdns,rclk-en enable adapted loop-back circuit
for boards which do have QSPI return clock provided.
This patch also modifies cqspi_readdata_capture() function's bypass
parameter to bool to match how its used in the function.
Signed-off-by: Vignesh R <vigneshr@ti.com>
---
drivers/mtd/spi-nor/cadence-quadspi.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
index 5cd5d6f7303f..d9629e8f4798 100644
--- a/drivers/mtd/spi-nor/cadence-quadspi.c
+++ b/drivers/mtd/spi-nor/cadence-quadspi.c
@@ -78,6 +78,7 @@ struct cqspi_st {
bool is_decoded_cs;
u32 fifo_depth;
u32 fifo_width;
+ bool rclk_en;
u32 trigger_address;
u32 wr_delay;
struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
@@ -788,7 +789,7 @@ static void cqspi_config_baudrate_div(struct cqspi_st *cqspi)
}
static void cqspi_readdata_capture(struct cqspi_st *cqspi,
- const unsigned int bypass,
+ const bool bypass,
const unsigned int delay)
{
void __iomem *reg_base = cqspi->iobase;
@@ -852,7 +853,8 @@ static void cqspi_configure(struct spi_nor *nor)
cqspi->sclk = sclk;
cqspi_config_baudrate_div(cqspi);
cqspi_delay(nor);
- cqspi_readdata_capture(cqspi, 1, f_pdata->read_delay);
+ cqspi_readdata_capture(cqspi, !cqspi->rclk_en,
+ f_pdata->read_delay);
}
if (switch_cs || switch_ck)
@@ -1049,6 +1051,8 @@ static int cqspi_of_get_pdata(struct platform_device *pdev)
return -ENXIO;
}
+ cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
+
return 0;
}
--
2.14.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v4 5/6] mtd: spi-nor: cadence-quadspi: Fix error path in probe
2017-10-03 5:19 [PATCH v4 0/6] K2G: Add QSPI support Vignesh R
` (3 preceding siblings ...)
2017-10-03 5:19 ` [PATCH v4 4/6] mtd: spi-nor: cadence-quadspi: Add support to enable loop-back clock circuit Vignesh R
@ 2017-10-03 5:19 ` Vignesh R
2017-10-03 5:19 ` [PATCH v4 6/6] mtd: spi-nor: cadence-quadspi: Add runtime PM support Vignesh R
2017-10-16 6:15 ` [PATCH v4 0/6] K2G: Add QSPI support Vignesh R
6 siblings, 0 replies; 12+ messages in thread
From: Vignesh R @ 2017-10-03 5:19 UTC (permalink / raw)
To: Marek Vasut, Cyrille Pitchen
Cc: David Woodhouse, Brian Norris, Boris Brezillon, Rob Herring,
linux-mtd, devicetree, linux-kernel, Vignesh R, linux-arm-kernel
Fix the reversed goto labels, so that we disable cqspi controller only
if its enabled previously. This is a minor cleanup.
Signed-off-by: Vignesh R <vigneshr@ti.com>
---
drivers/mtd/spi-nor/cadence-quadspi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
index d9629e8f4798..60b557e00cfb 100644
--- a/drivers/mtd/spi-nor/cadence-quadspi.c
+++ b/drivers/mtd/spi-nor/cadence-quadspi.c
@@ -1255,9 +1255,9 @@ static int cqspi_probe(struct platform_device *pdev)
}
return ret;
-probe_irq_failed:
- cqspi_controller_enable(cqspi, 0);
probe_setup_failed:
+ cqspi_controller_enable(cqspi, 0);
+probe_irq_failed:
clk_disable_unprepare(cqspi->clk);
return ret;
}
--
2.14.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v4 6/6] mtd: spi-nor: cadence-quadspi: Add runtime PM support
2017-10-03 5:19 [PATCH v4 0/6] K2G: Add QSPI support Vignesh R
` (4 preceding siblings ...)
2017-10-03 5:19 ` [PATCH v4 5/6] mtd: spi-nor: cadence-quadspi: Fix error path in probe Vignesh R
@ 2017-10-03 5:19 ` Vignesh R
2017-10-16 6:15 ` [PATCH v4 0/6] K2G: Add QSPI support Vignesh R
6 siblings, 0 replies; 12+ messages in thread
From: Vignesh R @ 2017-10-03 5:19 UTC (permalink / raw)
To: Marek Vasut, Cyrille Pitchen
Cc: David Woodhouse, Brian Norris, Boris Brezillon, Rob Herring,
linux-mtd, devicetree, linux-kernel, Vignesh R, linux-arm-kernel
Add pm_runtime* calls to cadence-quadspi driver. This is required to
switch on QSPI power domain on TI 66AK2G SoC during probe.
Signed-off-by: Vignesh R <vigneshr@ti.com>
---
v4: Disable pm in error path.
drivers/mtd/spi-nor/cadence-quadspi.c | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
index 60b557e00cfb..75a2bc447a99 100644
--- a/drivers/mtd/spi-nor/cadence-quadspi.c
+++ b/drivers/mtd/spi-nor/cadence-quadspi.c
@@ -31,6 +31,7 @@
#include <linux/of_device.h>
#include <linux/of.h>
#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
#include <linux/sched.h>
#include <linux/spi/spi.h>
#include <linux/timer.h>
@@ -1224,10 +1225,17 @@ static int cqspi_probe(struct platform_device *pdev)
return -ENXIO;
}
+ pm_runtime_enable(dev);
+ ret = pm_runtime_get_sync(dev);
+ if (ret < 0) {
+ pm_runtime_put_noidle(dev);
+ return ret;
+ }
+
ret = clk_prepare_enable(cqspi->clk);
if (ret) {
dev_err(dev, "Cannot enable QSPI clock.\n");
- return ret;
+ goto probe_clk_failed;
}
cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
@@ -1259,6 +1267,9 @@ static int cqspi_probe(struct platform_device *pdev)
cqspi_controller_enable(cqspi, 0);
probe_irq_failed:
clk_disable_unprepare(cqspi->clk);
+probe_clk_failed:
+ pm_runtime_put_sync(dev);
+ pm_runtime_disable(dev);
return ret;
}
@@ -1275,6 +1286,9 @@ static int cqspi_remove(struct platform_device *pdev)
clk_disable_unprepare(cqspi->clk);
+ pm_runtime_put_sync(&pdev->dev);
+ pm_runtime_disable(&pdev->dev);
+
return 0;
}
--
2.14.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v4 0/6] K2G: Add QSPI support
2017-10-03 5:19 [PATCH v4 0/6] K2G: Add QSPI support Vignesh R
` (5 preceding siblings ...)
2017-10-03 5:19 ` [PATCH v4 6/6] mtd: spi-nor: cadence-quadspi: Add runtime PM support Vignesh R
@ 2017-10-16 6:15 ` Vignesh R
2017-10-16 9:28 ` Marek Vasut
6 siblings, 1 reply; 12+ messages in thread
From: Vignesh R @ 2017-10-16 6:15 UTC (permalink / raw)
To: Marek Vasut, Cyrille Pitchen
Cc: David Woodhouse, Brian Norris, Boris Brezillon, Rob Herring,
linux-mtd, devicetree, linux-kernel, linux-arm-kernel
On Tuesday 03 October 2017 10:49 AM, Vignesh R wrote:
>
>
> This series adds support for Cadence QSPI IP present in TI's 66AK2G SoC.
> The patches enhance the existing cadence-quadspi driver to support
> loopback clock circuit, pm_runtime support and tweaks for 66AK2G SoC.
Gentle ping on the series...
>
> Change log:
>
> v4:
> * New patch to fix error handling sequence in probe.
>
> v3:
> * Fix build warnings reported by kbuild test bot.
>
> Resend:
> * Rebase to latest linux-next.
> * Collect Acked-bys
>
> v2:
> * Drop DT patches. Will be sent as separate series as requested by
> maintainer.
> * Split binding docs into separate patches.
> * Address comments by Rob Herring.
>
> Vignesh R (6):
> mtd: spi-nor: cadence-quadspi: Add TI 66AK2G SoC specific compatible
> mtd: spi-nor: cadence-quadspi: add a delay in write sequence
> mtd: spi-nor: cadence-quadspi: Add new binding to enable loop-back
> circuit
> mtd: spi-nor: cadence-quadspi: Add support to enable loop-back clock
> circuit
> mtd: spi-nor: cadence-quadspi: Fix error path in probe
> mtd: spi-nor: cadence-quadspi: Add runtime PM support
>
> .../devicetree/bindings/mtd/cadence-quadspi.txt | 7 ++-
> drivers/mtd/spi-nor/cadence-quadspi.c | 55 +++++++++++++++++++---
> 2 files changed, 55 insertions(+), 7 deletions(-)
>
--
Regards
Vignesh
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v4 0/6] K2G: Add QSPI support
2017-10-16 6:15 ` [PATCH v4 0/6] K2G: Add QSPI support Vignesh R
@ 2017-10-16 9:28 ` Marek Vasut
2017-10-16 22:29 ` Cyrille Pitchen
0 siblings, 1 reply; 12+ messages in thread
From: Marek Vasut @ 2017-10-16 9:28 UTC (permalink / raw)
To: Vignesh R, Cyrille Pitchen
Cc: David Woodhouse, Brian Norris, Boris Brezillon, Rob Herring,
linux-mtd, devicetree, linux-kernel, linux-arm-kernel
On 10/16/2017 08:15 AM, Vignesh R wrote:
>
>
> On Tuesday 03 October 2017 10:49 AM, Vignesh R wrote:
>>
>>
>> This series adds support for Cadence QSPI IP present in TI's 66AK2G SoC.
>> The patches enhance the existing cadence-quadspi driver to support
>> loopback clock circuit, pm_runtime support and tweaks for 66AK2G SoC.
>
> Gentle ping on the series...
It's IMO OK, Cyrille, can you pick it ?
>>
>> Change log:
>>
>> v4:
>> * New patch to fix error handling sequence in probe.
>>
>> v3:
>> * Fix build warnings reported by kbuild test bot.
>>
>> Resend:
>> * Rebase to latest linux-next.
>> * Collect Acked-bys
>>
>> v2:
>> * Drop DT patches. Will be sent as separate series as requested by
>> maintainer.
>> * Split binding docs into separate patches.
>> * Address comments by Rob Herring.
>>
>> Vignesh R (6):
>> mtd: spi-nor: cadence-quadspi: Add TI 66AK2G SoC specific compatible
>> mtd: spi-nor: cadence-quadspi: add a delay in write sequence
>> mtd: spi-nor: cadence-quadspi: Add new binding to enable loop-back
>> circuit
>> mtd: spi-nor: cadence-quadspi: Add support to enable loop-back clock
>> circuit
>> mtd: spi-nor: cadence-quadspi: Fix error path in probe
>> mtd: spi-nor: cadence-quadspi: Add runtime PM support
>>
>> .../devicetree/bindings/mtd/cadence-quadspi.txt | 7 ++-
>> drivers/mtd/spi-nor/cadence-quadspi.c | 55 +++++++++++++++++++---
>> 2 files changed, 55 insertions(+), 7 deletions(-)
>>
>
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v4 0/6] K2G: Add QSPI support
2017-10-16 9:28 ` Marek Vasut
@ 2017-10-16 22:29 ` Cyrille Pitchen
2017-10-16 22:34 ` Marek Vasut
0 siblings, 1 reply; 12+ messages in thread
From: Cyrille Pitchen @ 2017-10-16 22:29 UTC (permalink / raw)
To: Marek Vasut, Vignesh R
Cc: Boris Brezillon, devicetree, linux-kernel, Rob Herring,
linux-mtd, Brian Norris, David Woodhouse, linux-arm-kernel
Hi all,
Le 16/10/2017 à 11:28, Marek Vasut a écrit :
> On 10/16/2017 08:15 AM, Vignesh R wrote:
>>
>>
>> On Tuesday 03 October 2017 10:49 AM, Vignesh R wrote:
>>>
>>>
>>> This series adds support for Cadence QSPI IP present in TI's 66AK2G SoC.
>>> The patches enhance the existing cadence-quadspi driver to support
>>> loopback clock circuit, pm_runtime support and tweaks for 66AK2G SoC.
>>
>> Gentle ping on the series...
>
> It's IMO OK, Cyrille, can you pick it ?
>
The series looks good to me too.
Marek, could you please add you "Acked-by" or "Reviewed-by" tag for the
record in patchwork ? It will be automatically added when I use
"pwclient git-am -s" to merge the patches into the spi-nor/next branch.
Best regards,
Cyrille
>>>
>>> Change log:
>>>
>>> v4:
>>> * New patch to fix error handling sequence in probe.
>>>
>>> v3:
>>> * Fix build warnings reported by kbuild test bot.
>>>
>>> Resend:
>>> * Rebase to latest linux-next.
>>> * Collect Acked-bys
>>>
>>> v2:
>>> * Drop DT patches. Will be sent as separate series as requested by
>>> maintainer.
>>> * Split binding docs into separate patches.
>>> * Address comments by Rob Herring.
>>>
>>> Vignesh R (6):
>>> mtd: spi-nor: cadence-quadspi: Add TI 66AK2G SoC specific compatible
>>> mtd: spi-nor: cadence-quadspi: add a delay in write sequence
>>> mtd: spi-nor: cadence-quadspi: Add new binding to enable loop-back
>>> circuit
>>> mtd: spi-nor: cadence-quadspi: Add support to enable loop-back clock
>>> circuit
>>> mtd: spi-nor: cadence-quadspi: Fix error path in probe
>>> mtd: spi-nor: cadence-quadspi: Add runtime PM support
>>>
>>> .../devicetree/bindings/mtd/cadence-quadspi.txt | 7 ++-
>>> drivers/mtd/spi-nor/cadence-quadspi.c | 55 +++++++++++++++++++---
>>> 2 files changed, 55 insertions(+), 7 deletions(-)
>>>
>>
>
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v4 0/6] K2G: Add QSPI support
2017-10-16 22:29 ` Cyrille Pitchen
@ 2017-10-16 22:34 ` Marek Vasut
2017-10-17 18:50 ` Cyrille Pitchen
0 siblings, 1 reply; 12+ messages in thread
From: Marek Vasut @ 2017-10-16 22:34 UTC (permalink / raw)
To: Cyrille Pitchen, Vignesh R
Cc: Boris Brezillon, devicetree, linux-kernel, Rob Herring,
linux-mtd, Brian Norris, David Woodhouse, linux-arm-kernel
On 10/17/2017 12:29 AM, Cyrille Pitchen wrote:
> Hi all,
>
> Le 16/10/2017 à 11:28, Marek Vasut a écrit :
>> On 10/16/2017 08:15 AM, Vignesh R wrote:
>>>
>>>
>>> On Tuesday 03 October 2017 10:49 AM, Vignesh R wrote:
>>>>
>>>>
>>>> This series adds support for Cadence QSPI IP present in TI's 66AK2G SoC.
>>>> The patches enhance the existing cadence-quadspi driver to support
>>>> loopback clock circuit, pm_runtime support and tweaks for 66AK2G SoC.
>>>
>>> Gentle ping on the series...
>>
>> It's IMO OK, Cyrille, can you pick it ?
>>
>
> The series looks good to me too.
>
> Marek, could you please add you "Acked-by" or "Reviewed-by" tag for the
> record in patchwork ? It will be automatically added when I use
> "pwclient git-am -s" to merge the patches into the spi-nor/next branch.
Acked-by: Marek Vasut <marek.vasut@gmail.com>
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v4 0/6] K2G: Add QSPI support
2017-10-16 22:34 ` Marek Vasut
@ 2017-10-17 18:50 ` Cyrille Pitchen
0 siblings, 0 replies; 12+ messages in thread
From: Cyrille Pitchen @ 2017-10-17 18:50 UTC (permalink / raw)
To: Marek Vasut, Vignesh R
Cc: Boris Brezillon, devicetree, linux-kernel, Rob Herring,
linux-mtd, Brian Norris, David Woodhouse, linux-arm-kernel
Le 17/10/2017 à 00:34, Marek Vasut a écrit :
> On 10/17/2017 12:29 AM, Cyrille Pitchen wrote:
>> Hi all,
>>
>> Le 16/10/2017 à 11:28, Marek Vasut a écrit :
>>> On 10/16/2017 08:15 AM, Vignesh R wrote:
>>>>
>>>>
>>>> On Tuesday 03 October 2017 10:49 AM, Vignesh R wrote:
>>>>>
>>>>>
>>>>> This series adds support for Cadence QSPI IP present in TI's 66AK2G SoC.
>>>>> The patches enhance the existing cadence-quadspi driver to support
>>>>> loopback clock circuit, pm_runtime support and tweaks for 66AK2G SoC.
>>>>
>>>> Gentle ping on the series...
>>>
>>> It's IMO OK, Cyrille, can you pick it ?
>>>
>>
>> The series looks good to me too.
>>
>> Marek, could you please add you "Acked-by" or "Reviewed-by" tag for the
>> record in patchwork ? It will be automatically added when I use
>> "pwclient git-am -s" to merge the patches into the spi-nor/next branch.
>
> Acked-by: Marek Vasut <marek.vasut@gmail.com>
>
added Marek's "Acked-by" tags on the whole series and applied it into
the spi-nor/next branch of l2-mtd
Thanks!
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2017-10-17 18:50 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-10-03 5:19 [PATCH v4 0/6] K2G: Add QSPI support Vignesh R
2017-10-03 5:19 ` [PATCH v4 1/6] mtd: spi-nor: cadence-quadspi: Add TI 66AK2G SoC specific compatible Vignesh R
2017-10-03 5:19 ` [PATCH v4 2/6] mtd: spi-nor: cadence-quadspi: add a delay in write sequence Vignesh R
2017-10-03 5:19 ` [PATCH v4 3/6] mtd: spi-nor: cadence-quadspi: Add new binding to enable loop-back circuit Vignesh R
2017-10-03 5:19 ` [PATCH v4 4/6] mtd: spi-nor: cadence-quadspi: Add support to enable loop-back clock circuit Vignesh R
2017-10-03 5:19 ` [PATCH v4 5/6] mtd: spi-nor: cadence-quadspi: Fix error path in probe Vignesh R
2017-10-03 5:19 ` [PATCH v4 6/6] mtd: spi-nor: cadence-quadspi: Add runtime PM support Vignesh R
2017-10-16 6:15 ` [PATCH v4 0/6] K2G: Add QSPI support Vignesh R
2017-10-16 9:28 ` Marek Vasut
2017-10-16 22:29 ` Cyrille Pitchen
2017-10-16 22:34 ` Marek Vasut
2017-10-17 18:50 ` Cyrille Pitchen
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