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From: Paul Burton <paul.burton@mips.com>
To: Jason Cooper <jason@lakedaemon.net>,
	Marc Zyngier <marc.zyngier@arm.com>,
	Thomas Gleixner <tglx@linutronix.de>
Cc: <linux-mips@linux-mips.org>, <linux-kernel@vger.kernel.org>,
	Paul Burton <paul.burton@mips.com>
Subject: [PATCH v2 3/8] irqchip: mips-gic: Mask local interrupts when CPUs come online
Date: Tue, 31 Oct 2017 09:41:46 -0700	[thread overview]
Message-ID: <20171031164151.6357-4-paul.burton@mips.com> (raw)
In-Reply-To: <20171031164151.6357-1-paul.burton@mips.com>

We currently walk through the range 0..gic_vpes-1, expecting these
values all to be valid Linux CPU numbers to provide to mips_cm_vp_id(),
and masking all routable local interrupts during boot. This approach has
a few drawbacks:

 - In multi-cluster systems we won't have access to all CPU's GIC local
   registers when the driver is probed, since clusters (and their GICs)
   may be powered down at this point & only brought online later.

 - In multi-cluster systems we may power down clusters at runtime, for
   example if we offline all CPUs within it via hotplug, and the
   cluster's GIC may lose state. We therefore need to reinitialise it
   when powering back up, which this approach does not take into
   account.

 - The range 0..gic_vpes-1 may not all be valid Linux CPU numbers, for
   example if we run a kernel configured to support fewer CPUs than the
   system it is running on actually has. In this case we'll get garbage
   values from mips_cm_vp_id() as we read past the end of the cpu_data
   array.

Fix this and simplify the code somewhat by writing an all-bits-set
value to the VP-local reset mask register when a CPU is brought online,
before any local interrupts are configured for it. This removes the need
for us to access all CPUs during driver probe, removing all of the
problems described above.

In the name of simplicity we drop the checks for routability of
interrupts and simply clear the mask bits for all interrupts. Bits for
non-routable local interrupts will have no effect so there's no point
performing extra work to avoid modifying them.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-mips@linux-mips.org
---

Changes in v2: None

 drivers/irqchip/irq-mips-gic.c | 14 ++++----------
 1 file changed, 4 insertions(+), 10 deletions(-)

diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
index 60f644279803..bd732b256f67 100644
--- a/drivers/irqchip/irq-mips-gic.c
+++ b/drivers/irqchip/irq-mips-gic.c
@@ -655,6 +655,9 @@ static const struct irq_domain_ops gic_ipi_domain_ops = {
 
 static int gic_cpu_startup(unsigned int cpu)
 {
+	/* Clear all local IRQ masks (ie. disable all local interrupts) */
+	write_gic_vl_rmask(~0);
+
 	/* Invoke irq_cpu_online callbacks to enable desired interrupts */
 	irq_cpu_online();
 
@@ -664,7 +667,7 @@ static int gic_cpu_startup(unsigned int cpu)
 static int __init gic_of_init(struct device_node *node,
 			      struct device_node *parent)
 {
-	unsigned int cpu_vec, i, j, gicconfig, cpu, v[2];
+	unsigned int cpu_vec, i, gicconfig, cpu, v[2];
 	unsigned long reserved;
 	phys_addr_t gic_base;
 	struct resource res;
@@ -797,15 +800,6 @@ static int __init gic_of_init(struct device_node *node,
 		write_gic_rmask(i);
 	}
 
-	for (i = 0; i < gic_vpes; i++) {
-		write_gic_vl_other(mips_cm_vp_id(i));
-		for (j = 0; j < GIC_NUM_LOCAL_INTRS; j++) {
-			if (!gic_local_irq_is_routable(j))
-				continue;
-			write_gic_vo_rmask(BIT(j));
-		}
-	}
-
 	return cpuhp_setup_state(CPUHP_AP_IRQ_MIPS_GIC_STARTING,
 				 "irqchip/mips/gic:starting",
 				 gic_cpu_startup, NULL);
-- 
2.14.3

  parent reply	other threads:[~2017-10-31 16:43 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-10-25 23:37 [PATCH 0/8] irqchip: mips-gic: Cleanups, fixes, prep for multi-cluster Paul Burton
2017-10-25 23:37 ` [PATCH 1/8] irqchip: mips-gic: Inline gic_local_irq_domain_map() Paul Burton
2017-10-25 23:37 ` [PATCH 2/8] irqchip: mips-gic: Use irq_cpu_online to (un)mask all-VP(E) IRQs Paul Burton
2017-10-30  8:00   ` Marc Zyngier
2017-10-30 16:36     ` Paul Burton
2017-10-31  1:35       ` Marc Zyngier
2017-10-31 16:41         ` [PATCH v2 0/8] irqchip: mips-gic: Cleanups, fixes, prep for multi-cluster Paul Burton
2017-10-31 16:41           ` [PATCH v2 1/8] irqchip: mips-gic: Inline gic_local_irq_domain_map() Paul Burton
2017-10-31 16:41           ` [PATCH v2 2/8] irqchip: mips-gic: Use irq_cpu_online to (un)mask all-VP(E) IRQs Paul Burton
2017-10-31 16:41           ` Paul Burton [this message]
2017-10-31 16:41           ` [PATCH v2 4/8] irqchip: mips-gic: Configure EIC when CPUs come online Paul Burton
2017-10-31 16:41           ` [PATCH v2 5/8] irqchip: mips-gic: Use num_possible_cpus() to reserve IPIs Paul Burton
2017-10-31 16:41           ` [PATCH v2 6/8] irqchip: mips-gic: Remove gic_vpes variable Paul Burton
2017-10-31 16:41           ` [PATCH v2 7/8] irqchip: mips-gic: Share register writes in gic_set_type() Paul Burton
2017-10-31 16:41           ` [PATCH v2 8/8] irqchip: mips-gic: Make IPI bitmaps static Paul Burton
2017-11-01  0:13           ` [PATCH v2 0/8] irqchip: mips-gic: Cleanups, fixes, prep for multi-cluster Marc Zyngier
2017-11-01 16:40             ` Paul Burton
2017-11-01 16:59               ` Thomas Gleixner
2017-11-02 10:44                 ` Marc Zyngier
2017-10-25 23:37 ` [PATCH 3/8] irqchip: mips-gic: Mask local interrupts when CPUs come online Paul Burton
2017-10-25 23:37 ` [PATCH 4/8] irqchip: mips-gic: Configure EIC " Paul Burton
2017-10-25 23:37 ` [PATCH 5/8] irqchip: mips-gic: Use num_possible_cpus() to reserve IPIs Paul Burton
2017-10-25 23:37 ` [PATCH 6/8] irqchip: mips-gic: Remove gic_vpes variable Paul Burton
2017-10-25 23:37 ` [PATCH 7/8] irqchip: mips-gic: Share register writes in gic_set_type() Paul Burton
2017-10-25 23:37 ` [PATCH 8/8] irqchip: mips-gic: Make IPI bitmaps static Paul Burton

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