From: Marc Zyngier <marc.zyngier@arm.com>
To: Paul Burton <paul.burton@mips.com>
Cc: Jason Cooper <jason@lakedaemon.net>,
Thomas Gleixner <tglx@linutronix.de>, <linux-mips@linux-mips.org>,
<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 2/8] irqchip: mips-gic: Use irq_cpu_online to (un)mask all-VP(E) IRQs
Date: Mon, 30 Oct 2017 08:00:08 +0000 [thread overview]
Message-ID: <86mv495alz.fsf@arm.com> (raw)
In-Reply-To: <20171025233730.22225-3-paul.burton@mips.com> (Paul Burton's message of "Wed, 25 Oct 2017 16:37:24 -0700")
On Wed, Oct 25 2017 at 5:37:24 pm BST, Paul Burton <paul.burton@mips.com> wrote:
> The gic_all_vpes_local_irq_controller chip currently attempts to operate
> on all CPUs/VPs in the system when masking or unmasking an interrupt.
> This has a few drawbacks:
>
> - In multi-cluster systems we may not always have access to all CPUs in
> the system. When all CPUs in a cluster are powered down that
> cluster's GIC may also power down, in which case we cannot configure
> its state.
>
> - Relatedly, if we power down a cluster after having configured
> interrupts for CPUs within it then the cluster's GIC may lose state &
> we need to reconfigure it. The current approach doesn't take this
> into account.
>
> - It's wasteful if we run Linux on fewer VPs than are present in the
> system. For example if we run a uniprocessor kernel on CPU0 of a
> system with 16 CPUs then there's no point in us configuring CPUs
> 1-15.
>
> - The implementation is also lacking in that it expects the range
> 0..gic_vpes-1 to represent valid Linux CPU numbers which may not
> always be the case - for example if we run on a system with more VPs
> than the kernel is configured to support.
>
> Fix all of these issues by only configuring the affected interrupts for
> CPUs which are online at the time, and recording the configuration in a
> new struct gic_all_vpes_chip_data for later use by CPUs being brought
> online. We register a CPU hotplug state (reusing
> CPUHP_AP_IRQ_GIC_STARTING which the ARM GIC driver uses, and which seems
> suitably generic for reuse with the MIPS GIC) and execute
> irq_cpu_online() in order to configure the interrupts on the newly
> onlined CPU.
>
> Signed-off-by: Paul Burton <paul.burton@mips.com>
> Cc: Jason Cooper <jason@lakedaemon.net>
> Cc: Marc Zyngier <marc.zyngier@arm.com>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: linux-mips@linux-mips.org
> ---
>
> drivers/irqchip/irq-mips-gic.c | 72 ++++++++++++++++++++++++++++++++----------
> 1 file changed, 56 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
> index 6fdcc1552fab..dd9da773db90 100644
> --- a/drivers/irqchip/irq-mips-gic.c
> +++ b/drivers/irqchip/irq-mips-gic.c
[...]
> @@ -622,6 +653,13 @@ static const struct irq_domain_ops gic_ipi_domain_ops = {
> .match = gic_ipi_domain_match,
> };
>
> +static int gic_cpu_startup(unsigned int cpu)
> +{
> + /* Invoke irq_cpu_online callbacks to enable desired interrupts */
> + irq_cpu_online();
> +
> + return 0;
> +}
>
> static int __init gic_of_init(struct device_node *node,
> struct device_node *parent)
> @@ -768,6 +806,8 @@ static int __init gic_of_init(struct device_node *node,
> }
> }
>
> - return 0;
> + return cpuhp_setup_state(CPUHP_AP_IRQ_GIC_STARTING,
> + "irqchip/mips/gic:starting",
> + gic_cpu_startup, NULL);
I'm wondering about this. CPUHP_AP_IRQ_GIC_STARTING is a symbol that is
used on ARM platforms. You're very welcome to use it (as long as nobody
builds a system with both an ARM GIC and a MIPS GIC...), but I'm a bit
worried that we could end-up breaking things if one of us decides to
reorder it in enum cpuhp_state.
The safest option would be for you to add your own state value, which
would allow the two architecture to evolve independently.
Thoughts?
M.
--
Jazz is not dead. It just smells funny.
next prev parent reply other threads:[~2017-10-30 8:00 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-25 23:37 [PATCH 0/8] irqchip: mips-gic: Cleanups, fixes, prep for multi-cluster Paul Burton
2017-10-25 23:37 ` [PATCH 1/8] irqchip: mips-gic: Inline gic_local_irq_domain_map() Paul Burton
2017-10-25 23:37 ` [PATCH 2/8] irqchip: mips-gic: Use irq_cpu_online to (un)mask all-VP(E) IRQs Paul Burton
2017-10-30 8:00 ` Marc Zyngier [this message]
2017-10-30 16:36 ` Paul Burton
2017-10-31 1:35 ` Marc Zyngier
2017-10-31 16:41 ` [PATCH v2 0/8] irqchip: mips-gic: Cleanups, fixes, prep for multi-cluster Paul Burton
2017-10-31 16:41 ` [PATCH v2 1/8] irqchip: mips-gic: Inline gic_local_irq_domain_map() Paul Burton
2017-10-31 16:41 ` [PATCH v2 2/8] irqchip: mips-gic: Use irq_cpu_online to (un)mask all-VP(E) IRQs Paul Burton
2017-10-31 16:41 ` [PATCH v2 3/8] irqchip: mips-gic: Mask local interrupts when CPUs come online Paul Burton
2017-10-31 16:41 ` [PATCH v2 4/8] irqchip: mips-gic: Configure EIC " Paul Burton
2017-10-31 16:41 ` [PATCH v2 5/8] irqchip: mips-gic: Use num_possible_cpus() to reserve IPIs Paul Burton
2017-10-31 16:41 ` [PATCH v2 6/8] irqchip: mips-gic: Remove gic_vpes variable Paul Burton
2017-10-31 16:41 ` [PATCH v2 7/8] irqchip: mips-gic: Share register writes in gic_set_type() Paul Burton
2017-10-31 16:41 ` [PATCH v2 8/8] irqchip: mips-gic: Make IPI bitmaps static Paul Burton
2017-11-01 0:13 ` [PATCH v2 0/8] irqchip: mips-gic: Cleanups, fixes, prep for multi-cluster Marc Zyngier
2017-11-01 16:40 ` Paul Burton
2017-11-01 16:59 ` Thomas Gleixner
2017-11-02 10:44 ` Marc Zyngier
2017-10-25 23:37 ` [PATCH 3/8] irqchip: mips-gic: Mask local interrupts when CPUs come online Paul Burton
2017-10-25 23:37 ` [PATCH 4/8] irqchip: mips-gic: Configure EIC " Paul Burton
2017-10-25 23:37 ` [PATCH 5/8] irqchip: mips-gic: Use num_possible_cpus() to reserve IPIs Paul Burton
2017-10-25 23:37 ` [PATCH 6/8] irqchip: mips-gic: Remove gic_vpes variable Paul Burton
2017-10-25 23:37 ` [PATCH 7/8] irqchip: mips-gic: Share register writes in gic_set_type() Paul Burton
2017-10-25 23:37 ` [PATCH 8/8] irqchip: mips-gic: Make IPI bitmaps static Paul Burton
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=86mv495alz.fsf@arm.com \
--to=marc.zyngier@arm.com \
--cc=jason@lakedaemon.net \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mips@linux-mips.org \
--cc=paul.burton@mips.com \
--cc=tglx@linutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).