From: Russell King - ARM Linux <linux@armlinux.org.uk>
To: "Liuwenliang (Abbott Liu)" <liuwenliang@huawei.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
"tixy@linaro.org" <tixy@linaro.org>,
"mhocko@suse.com" <mhocko@suse.com>,
"grygorii.strashko@linaro.org" <grygorii.strashko@linaro.org>,
"catalin.marinas@arm.com" <catalin.marinas@arm.com>,
"linux-mm@kvack.org" <linux-mm@kvack.org>,
"glider@google.com" <glider@google.com>,
"afzal.mohd.ma@gmail.com" <afzal.mohd.ma@gmail.com>,
"mingo@kernel.org" <mingo@kernel.org>,
Christoffer Dall <cdall@linaro.org>,
"opendmb@gmail.com" <opendmb@gmail.com>,
"mawilcox@microsoft.com" <mawilcox@microsoft.com>,
"kasan-dev@googlegroups.com" <kasan-dev@googlegroups.com>,
Dailei <dylix.dailei@huawei.com>,
"dvyukov@google.com" <dvyukov@google.com>,
"aryabinin@virtuozzo.com" <aryabinin@virtuozzo.com>,
"labbott@redhat.com" <labbott@redhat.com>,
"vladimir.murzin@arm.com" <vladimir.murzin@arm.com>,
"keescook@chromium.org" <keescook@chromium.org>,
"arnd@arndb.de" <arnd@arndb.de>,
Zengweilin <zengweilin@huawei.com>,
"f.fainelli@gmail.com" <f.fainelli@gmail.com>,
Heshaoliang <heshaoliang@huawei.com>,
"tglx@linutronix.de" <tglx@linutronix.de>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"ard.biesheuvel@linaro.org" <ard.biesheuvel@linaro.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Jiazhenghua <jiazhenghua@huawei.com>,
"akpm@linux-foundation.org" <akpm@linux-foundation.org>,
"robin.murphy@arm.com" <robin.murphy@arm.com>,
"thgarnie@google.com" <thgarnie@google.com>,
"kirill.shutemov@linux.intel.com"
<kirill.shutemov@linux.intel.com>
Subject: Re: [PATCH 01/11] Initialize the mapping of KASan shadow memory
Date: Thu, 23 Nov 2017 15:22:18 +0000 [thread overview]
Message-ID: <20171123152218.GQ31757@n2100.armlinux.org.uk> (raw)
In-Reply-To: <B8AC3E80E903784988AB3003E3E97330C0069083@dggemm510-mbx.china.huawei.com>
On Thu, Nov 23, 2017 at 01:54:59AM +0000, Liuwenliang (Abbott Liu) wrote:
> On Nov 23, 2017 20:30 Marc Zyngier [mailto:marc.zyngier@arm.com] wrote:
> >Please define both PAR accessors. Yes, I know the 32bit version is not
> >used yet, but it doesn't hurt to make it visible.
>
> Thanks for your review.
> I'm going to change it in the new version.
> Here is the code I tested on vexpress_a9 and vexpress_a15:
> diff --git a/arch/arm/include/asm/cp15.h b/arch/arm/include/asm/cp15.h
> index dbdbce1..b8353b1 100644
> --- a/arch/arm/include/asm/cp15.h
> +++ b/arch/arm/include/asm/cp15.h
> @@ -2,6 +2,7 @@
> #define __ASM_ARM_CP15_H
>
> #include <asm/barrier.h>
> +#include <linux/stringify.h>
>
> /*
> * CR1 bits (CP#15 CR1)
> @@ -64,8 +65,109 @@
> #define __write_sysreg(v, r, w, c, t) asm volatile(w " " c : : "r" ((t)(v)))
> #define write_sysreg(v, ...) __write_sysreg(v, __VA_ARGS__)
>
> +#define TTBR0_32 __ACCESS_CP15(c2, 0, c0, 0)
> +#define TTBR1_32 __ACCESS_CP15(c2, 0, c0, 1)
> +#define PAR_32 __ACCESS_CP15(c7, 0, c4, 0)
> +#define TTBR0_64 __ACCESS_CP15_64(0, c2)
> +#define TTBR1_64 __ACCESS_CP15_64(1, c2)
> +#define PAR_64 __ACCESS_CP15_64(0, c7)
> +#define VTTBR __ACCESS_CP15_64(6, c2)
> +#define CNTV_CVAL __ACCESS_CP15_64(3, c14)
> +#define CNTVOFF __ACCESS_CP15_64(4, c14)
> +
> +#define MIDR __ACCESS_CP15(c0, 0, c0, 0)
> +#define CSSELR __ACCESS_CP15(c0, 2, c0, 0)
> +#define VPIDR __ACCESS_CP15(c0, 4, c0, 0)
> +#define VMPIDR __ACCESS_CP15(c0, 4, c0, 5)
> +#define SCTLR __ACCESS_CP15(c1, 0, c0, 0)
> +#define CPACR __ACCESS_CP15(c1, 0, c0, 2)
> +#define HCR __ACCESS_CP15(c1, 4, c1, 0)
> +#define HDCR __ACCESS_CP15(c1, 4, c1, 1)
> +#define HCPTR __ACCESS_CP15(c1, 4, c1, 2)
> +#define HSTR __ACCESS_CP15(c1, 4, c1, 3)
> +#define TTBCR __ACCESS_CP15(c2, 0, c0, 2)
> +#define HTCR __ACCESS_CP15(c2, 4, c0, 2)
> +#define VTCR __ACCESS_CP15(c2, 4, c1, 2)
> +#define DACR __ACCESS_CP15(c3, 0, c0, 0)
> +#define DFSR __ACCESS_CP15(c5, 0, c0, 0)
> +#define IFSR __ACCESS_CP15(c5, 0, c0, 1)
> +#define ADFSR __ACCESS_CP15(c5, 0, c1, 0)
> +#define AIFSR __ACCESS_CP15(c5, 0, c1, 1)
> +#define HSR __ACCESS_CP15(c5, 4, c2, 0)
> +#define DFAR __ACCESS_CP15(c6, 0, c0, 0)
> +#define IFAR __ACCESS_CP15(c6, 0, c0, 2)
> +#define HDFAR __ACCESS_CP15(c6, 4, c0, 0)
> +#define HIFAR __ACCESS_CP15(c6, 4, c0, 2)
> +#define HPFAR __ACCESS_CP15(c6, 4, c0, 4)
> +#define ICIALLUIS __ACCESS_CP15(c7, 0, c1, 0)
> +#define ATS1CPR __ACCESS_CP15(c7, 0, c8, 0)
> +#define TLBIALLIS __ACCESS_CP15(c8, 0, c3, 0)
> +#define TLBIALL __ACCESS_CP15(c8, 0, c7, 0)
> +#define TLBIALLNSNHIS __ACCESS_CP15(c8, 4, c3, 4)
> +#define PRRR __ACCESS_CP15(c10, 0, c2, 0)
> +#define NMRR __ACCESS_CP15(c10, 0, c2, 1)
> +#define AMAIR0 __ACCESS_CP15(c10, 0, c3, 0)
> +#define AMAIR1 __ACCESS_CP15(c10, 0, c3, 1)
> +#define VBAR __ACCESS_CP15(c12, 0, c0, 0)
> +#define CID __ACCESS_CP15(c13, 0, c0, 1)
> +#define TID_URW __ACCESS_CP15(c13, 0, c0, 2)
> +#define TID_URO __ACCESS_CP15(c13, 0, c0, 3)
> +#define TID_PRIV __ACCESS_CP15(c13, 0, c0, 4)
> +#define HTPIDR __ACCESS_CP15(c13, 4, c0, 2)
> +#define CNTKCTL __ACCESS_CP15(c14, 0, c1, 0)
> +#define CNTV_CTL __ACCESS_CP15(c14, 0, c3, 1)
> +#define CNTHCTL __ACCESS_CP15(c14, 4, c1, 0)
> +
> extern unsigned long cr_alignment; /* defined in entry-armv.S */
>
> +static inline void set_par(u64 val)
> +{
> + if (IS_ENABLED(CONFIG_ARM_LPAE))
> + write_sysreg(val, PAR_64);
> + else
> + write_sysreg(val, PAR_32);
> +}
> +
> +static inline u64 get_par(void)
> +{
> + if (IS_ENABLED(CONFIG_ARM_LPAE))
> + return read_sysreg(PAR_64);
> + else
> + return (u64)read_sysreg(PAR_32);
> +}
> +
> +static inline void set_ttbr0(u64 val)
> +{
> + if (IS_ENABLED(CONFIG_ARM_LPAE))
> + write_sysreg(val, TTBR0_64);
> + else
> + write_sysreg(val, TTBR0_32);
> +}
> +
> +static inline u64 get_ttbr0(void)
> +{
> + if (IS_ENABLED(CONFIG_ARM_LPAE))
> + return read_sysreg(TTBR0_64);
> + else
> + return (u64)read_sysreg(TTBR0_32);
> +}
> +
> +static inline void set_ttbr1(u64 val)
> +{
> + if (IS_ENABLED(CONFIG_ARM_LPAE))
> + write_sysreg(val, TTBR1_64);
> + else
> + write_sysreg(val, TTBR1_32);
> +}
> +
> +static inline u64 get_ttbr1(void)
> +{
> + if (IS_ENABLED(CONFIG_ARM_LPAE))
> + return read_sysreg(TTBR1_64);
> + else
> + return (u64)read_sysreg(TTBR1_32);
> +}
> +
Please pay attention to the project coding style whenever creating code
for a program. It doesn't matter what the project coding style is, as
long as you write your code to match the style that is already there.
For the kernel, that is: tabs not spaces for indentation of code.
You seem to be using a variable number of spaces for all the new code
above.
Some of it seems to be your email client thinking it knows better about
white space - and such behaviours basically makes patches unapplyable.
See Documentation/process/email-clients.rst for hints about email
clients.
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line in suburbia: sync at 8.8Mbps down 630kbps up
According to speedtest.net: 8.21Mbps down 510kbps up
next prev parent reply other threads:[~2017-11-23 15:23 UTC|newest]
Thread overview: 83+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-11 8:22 [PATCH 00/11] KASan for arm Abbott Liu
2017-10-11 8:22 ` [PATCH 01/11] Initialize the mapping of KASan shadow memory Abbott Liu
2017-10-11 19:39 ` Florian Fainelli
2017-10-11 21:41 ` Russell King - ARM Linux
2017-10-17 13:28 ` Liuwenliang (Lamb)
2017-10-11 23:42 ` Dmitry Osipenko
2017-10-19 6:52 ` Liuwenliang (Lamb)
2017-10-19 12:01 ` Russell King - ARM Linux
2017-10-12 7:58 ` Marc Zyngier
2017-11-09 7:46 ` Liuwenliang (Abbott Liu)
2017-11-09 10:10 ` Marc Zyngier
2017-11-15 10:20 ` Liuwenliang (Abbott Liu)
2017-11-15 10:35 ` Marc Zyngier
2017-11-15 13:16 ` Liuwenliang (Abbott Liu)
2017-11-15 13:54 ` Marc Zyngier
2017-11-16 3:07 ` Liuwenliang (Abbott Liu)
2017-11-16 9:54 ` Marc Zyngier
2017-11-16 14:24 ` Liuwenliang (Abbott Liu)
2017-11-16 14:40 ` Marc Zyngier
2017-11-17 1:39 ` 答复: " Liuwenliang (Abbott Liu)
2017-11-17 7:18 ` Liuwenliang (Abbott Liu)
2017-11-17 7:35 ` Christoffer Dall
2017-11-18 10:40 ` Liuwenliang (Abbott Liu)
2017-11-18 13:48 ` Marc Zyngier
[not found] ` <B8AC3E80E903784988AB3003E3E97330C0068F12@dggemm510-mbx.china.huawei.com>
2017-11-21 9:40 ` 答复: " Russell King - ARM Linux
2017-11-21 9:46 ` Marc Zyngier
2017-11-21 12:29 ` Mark Rutland
2017-11-22 12:56 ` Liuwenliang (Abbott Liu)
2017-11-22 13:06 ` Marc Zyngier
2017-11-23 1:54 ` Liuwenliang (Abbott Liu)
2017-11-23 15:22 ` Russell King - ARM Linux [this message]
2017-11-27 1:23 ` Liuwenliang (Abbott Liu)
2017-11-23 15:31 ` Mark Rutland
2017-10-19 11:09 ` Russell King - ARM Linux
2018-02-24 14:28 ` Liuwenliang (Abbott Liu)
2017-10-11 8:22 ` [PATCH 02/11] replace memory function Abbott Liu
2017-10-19 12:05 ` Russell King - ARM Linux
2017-10-11 8:22 ` [PATCH 03/11] arm: Kconfig: enable KASan Abbott Liu
2017-10-11 19:15 ` Florian Fainelli
2017-10-19 12:34 ` Russell King - ARM Linux
2017-10-22 12:27 ` Liuwenliang (Lamb)
2017-10-11 8:22 ` [PATCH 04/11] Define the virtual space of KASan's shadow region Abbott Liu
2017-10-14 11:41 ` kbuild test robot
2017-10-16 11:42 ` Liuwenliang (Lamb)
2017-10-16 12:14 ` Ard Biesheuvel
2017-10-17 11:27 ` Liuwenliang (Lamb)
2017-10-17 11:52 ` Ard Biesheuvel
2017-10-17 13:02 ` Liuwenliang (Lamb)
2017-10-19 12:43 ` Russell King - ARM Linux
2017-10-22 12:12 ` Liuwenliang (Lamb)
2017-10-19 12:41 ` Russell King - ARM Linux
2017-10-19 12:40 ` Russell King - ARM Linux
2017-10-11 8:22 ` [PATCH 05/11] Disable kasan's instrumentation Abbott Liu
2017-10-11 19:16 ` Florian Fainelli
2017-10-19 12:47 ` Russell King - ARM Linux
2017-11-15 10:19 ` Liuwenliang (Abbott Liu)
2017-10-11 8:22 ` [PATCH 06/11] change memory_is_poisoned_16 for aligned error Abbott Liu
2017-10-11 23:23 ` Andrew Morton
2017-10-12 7:16 ` Dmitry Vyukov
2017-10-12 11:27 ` Liuwenliang (Lamb)
2017-10-19 12:51 ` Russell King - ARM Linux
2017-12-05 14:19 ` Liuwenliang (Abbott Liu)
2017-12-05 17:08 ` Ard Biesheuvel
2018-01-16 8:39 ` Liuwenliang (Abbott Liu)
2017-10-11 8:22 ` [PATCH 07/11] Avoid cleaning the KASan shadow area's mapping table Abbott Liu
2017-10-11 8:22 ` [PATCH 08/11] Add support arm LPAE Abbott Liu
2017-10-11 8:22 ` [PATCH 09/11] Don't need to map the shadow of KASan's shadow memory Abbott Liu
2017-10-19 12:55 ` Russell King - ARM Linux
2017-10-22 12:31 ` Liuwenliang (Lamb)
2017-10-11 8:22 ` [PATCH 10/11] Change mapping of kasan_zero_page int readonly Abbott Liu
2017-10-11 19:19 ` Florian Fainelli
2017-10-11 8:22 ` [PATCH 11/11] Add KASan layout Abbott Liu
2017-10-11 19:13 ` [PATCH 00/11] KASan for arm Florian Fainelli
2017-10-11 19:50 ` Florian Fainelli
2017-10-11 21:36 ` Florian Fainelli
2017-10-11 22:10 ` Laura Abbott
2017-10-11 22:58 ` Russell King - ARM Linux
2017-10-17 12:41 ` Liuwenliang (Lamb)
2017-10-12 4:55 ` Liuwenliang (Lamb)
2017-10-12 7:38 ` Arnd Bergmann
2017-10-17 1:04 ` 答复: " Liuwenliang (Lamb)
2018-02-13 18:40 ` Florian Fainelli
2018-02-23 2:10 ` Liuwenliang (Abbott Liu)
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20171123152218.GQ31757@n2100.armlinux.org.uk \
--to=linux@armlinux.org.uk \
--cc=afzal.mohd.ma@gmail.com \
--cc=akpm@linux-foundation.org \
--cc=ard.biesheuvel@linaro.org \
--cc=arnd@arndb.de \
--cc=aryabinin@virtuozzo.com \
--cc=catalin.marinas@arm.com \
--cc=cdall@linaro.org \
--cc=dvyukov@google.com \
--cc=dylix.dailei@huawei.com \
--cc=f.fainelli@gmail.com \
--cc=glider@google.com \
--cc=grygorii.strashko@linaro.org \
--cc=heshaoliang@huawei.com \
--cc=jiazhenghua@huawei.com \
--cc=kasan-dev@googlegroups.com \
--cc=keescook@chromium.org \
--cc=kirill.shutemov@linux.intel.com \
--cc=labbott@redhat.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mm@kvack.org \
--cc=liuwenliang@huawei.com \
--cc=marc.zyngier@arm.com \
--cc=mark.rutland@arm.com \
--cc=mawilcox@microsoft.com \
--cc=mhocko@suse.com \
--cc=mingo@kernel.org \
--cc=opendmb@gmail.com \
--cc=robin.murphy@arm.com \
--cc=tglx@linutronix.de \
--cc=thgarnie@google.com \
--cc=tixy@linaro.org \
--cc=vladimir.murzin@arm.com \
--cc=zengweilin@huawei.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).