* [PATCH 0/3] EDAC: support for Armada 38x and 98dx3236 SoCs @ 2018-01-08 22:31 Chris Packham 2018-01-08 22:31 ` [PATCH 1/3] ARM: dts: enable L2 cache parity and ecc on db-xc3-24g4xg board Chris Packham ` (2 more replies) 0 siblings, 3 replies; 9+ messages in thread From: Chris Packham @ 2018-01-08 22:31 UTC (permalink / raw) To: jlu, linux, bp, linux-arm-kernel, linux-edac; +Cc: linux-kernel, Chris Packham This series applies on top of Jan Lubbe's "EDAC drivers for Armada XP L2 and DDR" series[1]. The Armada 38x as well as the 98dx3236 and similar switch chips with integrated CPUs use the same SDRAM controller block as the Armada XP. The key difference is the width of the DDR interface. [1] - https://marc.info/?l=linux-edac&m=151030475715706&w=2 Chris Packham (3): ARM: dts: enable L2 cache parity and ecc on db-xc3-24g4xg board ARM: dts: mvebu: add sdram controller node to Armada-38x EDAC: armada_xp: Add support for more SoCs arch/arm/boot/dts/armada-38x.dtsi | 5 +++++ arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts | 5 +++++ drivers/edac/armada_xp_edac.c | 5 +++++ 3 files changed, 15 insertions(+) -- 2.15.1 ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/3] ARM: dts: enable L2 cache parity and ecc on db-xc3-24g4xg board 2018-01-08 22:31 [PATCH 0/3] EDAC: support for Armada 38x and 98dx3236 SoCs Chris Packham @ 2018-01-08 22:31 ` Chris Packham 2018-01-10 8:24 ` Gregory CLEMENT 2018-01-08 22:31 ` [PATCH 2/3] ARM: dts: mvebu: add sdram controller node to Armada-38x Chris Packham 2018-01-08 22:31 ` [PATCH 3/3] EDAC: armada_xp: Add support for more SoCs Chris Packham 2 siblings, 1 reply; 9+ messages in thread From: Chris Packham @ 2018-01-08 22:31 UTC (permalink / raw) To: jlu, linux, bp, linux-arm-kernel, linux-edac Cc: linux-kernel, Chris Packham, Jason Cooper, Andrew Lunn, Gregory Clement, Sebastian Hesselbarth, Rob Herring, Mark Rutland, devicetree Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> --- arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts b/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts index 06fce35d7491..00ca489fc788 100644 --- a/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts +++ b/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts @@ -70,6 +70,11 @@ }; }; +&L2 { + arm,parity-enable; + marvell,ecc-enable; +}; + &devbus_bootcs { status = "okay"; -- 2.15.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 1/3] ARM: dts: enable L2 cache parity and ecc on db-xc3-24g4xg board 2018-01-08 22:31 ` [PATCH 1/3] ARM: dts: enable L2 cache parity and ecc on db-xc3-24g4xg board Chris Packham @ 2018-01-10 8:24 ` Gregory CLEMENT 2018-01-10 20:08 ` Chris Packham 0 siblings, 1 reply; 9+ messages in thread From: Gregory CLEMENT @ 2018-01-10 8:24 UTC (permalink / raw) To: Chris Packham Cc: jlu, linux, bp, linux-arm-kernel, linux-edac, linux-kernel, Jason Cooper, Andrew Lunn, Sebastian Hesselbarth, Rob Herring, Mark Rutland, devicetree Hi Chris, On mar., janv. 09 2018, Chris Packham <chris.packham@alliedtelesis.co.nz> wrote: Could you have add a (even small) message in the commit log? Also could you improve the title by specify that it applies on armada-xp, like this: ARM: dts: armada-xp: enable L2 cache parity and ecc on db-xc3-24g4xg > Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> > --- > arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts b/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts > index 06fce35d7491..00ca489fc788 100644 > --- a/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts > +++ b/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts > @@ -70,6 +70,11 @@ > }; > }; > > +&L2 { > + arm,parity-enable; > + marvell,ecc-enable; It is not a problem for me to already applied the device tree change even if the driver is not merged yet. But I would like to have an acked-by on this new property by either a device tree maintainer or at least the EDAC maintainer, of course having both acked-by would be perfect ! :) Thanks, Gregory > +}; > + > &devbus_bootcs { > status = "okay"; > > -- > 2.15.1 > -- Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/3] ARM: dts: enable L2 cache parity and ecc on db-xc3-24g4xg board 2018-01-10 8:24 ` Gregory CLEMENT @ 2018-01-10 20:08 ` Chris Packham 0 siblings, 0 replies; 9+ messages in thread From: Chris Packham @ 2018-01-10 20:08 UTC (permalink / raw) To: Gregory CLEMENT Cc: jlu, linux, bp, linux-arm-kernel, linux-edac, linux-kernel, Jason Cooper, Andrew Lunn, Sebastian Hesselbarth, Rob Herring, Mark Rutland, devicetree Hi Gregory, On 10/01/18 21:24, Gregory CLEMENT wrote: > Hi Chris, > > On mar., janv. 09 2018, Chris Packham <chris.packham@alliedtelesis.co.nz> wrote: > > Could you have add a (even small) message in the commit log? > > Also could you improve the title by specify that it applies on > armada-xp, like this: > > ARM: dts: armada-xp: enable L2 cache parity and ecc on db-xc3-24g4xg > Will do. >> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> >> --- >> arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts | 5 +++++ >> 1 file changed, 5 insertions(+) >> >> diff --git a/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts b/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts >> index 06fce35d7491..00ca489fc788 100644 >> --- a/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts >> +++ b/arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts >> @@ -70,6 +70,11 @@ >> }; >> }; >> >> +&L2 { >> + arm,parity-enable; >> + marvell,ecc-enable; > > It is not a problem for me to already applied the device tree change > even if the driver is not merged yet. But I would like to have an > acked-by on this new property by either a device tree maintainer or at > least the EDAC maintainer, of course having both acked-by would be > perfect ! :) Thanks, I was hoping you would say that. That way I can keep this independent of the EDAC driver changes. > > Thanks, > > Gregory > > > > >> +}; >> + >> &devbus_bootcs { >> status = "okay"; >> >> -- >> 2.15.1 >> > ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 2/3] ARM: dts: mvebu: add sdram controller node to Armada-38x 2018-01-08 22:31 [PATCH 0/3] EDAC: support for Armada 38x and 98dx3236 SoCs Chris Packham 2018-01-08 22:31 ` [PATCH 1/3] ARM: dts: enable L2 cache parity and ecc on db-xc3-24g4xg board Chris Packham @ 2018-01-08 22:31 ` Chris Packham 2018-01-10 8:31 ` Gregory CLEMENT 2018-01-08 22:31 ` [PATCH 3/3] EDAC: armada_xp: Add support for more SoCs Chris Packham 2 siblings, 1 reply; 9+ messages in thread From: Chris Packham @ 2018-01-08 22:31 UTC (permalink / raw) To: jlu, linux, bp, linux-arm-kernel, linux-edac Cc: linux-kernel, Chris Packham, Jason Cooper, Andrew Lunn, Gregory Clement, Sebastian Hesselbarth, Rob Herring, Mark Rutland, devicetree The Armada-38x uses an SDRAM controller that is compatible with the Armada-XP. The key difference is the width of the bus (XP is 64/32, 38x is 32/16). The SDRAM controller registers are the same between the two SoCs. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> --- arch/arm/boot/dts/armada-38x.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index 00ff549d4e39..6d34c5ec178f 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -138,6 +138,11 @@ #size-cells = <1>; ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; + sdramc@1400 { + compatible = "marvell,armada-xp-sdram-controller"; + reg = <0x1400 0x500>; + }; + L2: cache-controller@8000 { compatible = "arm,pl310-cache"; reg = <0x8000 0x1000>; -- 2.15.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 2/3] ARM: dts: mvebu: add sdram controller node to Armada-38x 2018-01-08 22:31 ` [PATCH 2/3] ARM: dts: mvebu: add sdram controller node to Armada-38x Chris Packham @ 2018-01-10 8:31 ` Gregory CLEMENT 2018-01-10 20:19 ` Chris Packham 0 siblings, 1 reply; 9+ messages in thread From: Gregory CLEMENT @ 2018-01-10 8:31 UTC (permalink / raw) To: Chris Packham Cc: jlu, linux, bp, linux-arm-kernel, linux-edac, linux-kernel, Jason Cooper, Andrew Lunn, Sebastian Hesselbarth, Rob Herring, Mark Rutland, devicetree Hi Chris, On mar., janv. 09 2018, Chris Packham <chris.packham@alliedtelesis.co.nz> wrote: > The Armada-38x uses an SDRAM controller that is compatible with the > Armada-XP. The key difference is the width of the bus (XP is 64/32, 38x > is 32/16). The SDRAM controller registers are the same between the two > SoCs. > > Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> > --- > arch/arm/boot/dts/armada-38x.dtsi | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi > index 00ff549d4e39..6d34c5ec178f 100644 > --- a/arch/arm/boot/dts/armada-38x.dtsi > +++ b/arch/arm/boot/dts/armada-38x.dtsi > @@ -138,6 +138,11 @@ > #size-cells = <1>; > ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; > > + sdramc@1400 { Could you add a label? Thanks to this it would be possible to enable/disable it at board level in a esay way. > + compatible = "marvell,armada-xp-sdram-controller"; > + reg = <0x1400 0x500>; What about adding status = "disabled" ? Thanks to this we can enable it at board level only if we really want it, it would avoid nasty regression on boards that don't need it, if an issue occurs. Unless you are sure that it is completely safe to enable it for everyone. Thanks, Gregory > + }; > + > L2: cache-controller@8000 { > compatible = "arm,pl310-cache"; > reg = <0x8000 0x1000>; > -- > 2.15.1 > -- Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/3] ARM: dts: mvebu: add sdram controller node to Armada-38x 2018-01-10 8:31 ` Gregory CLEMENT @ 2018-01-10 20:19 ` Chris Packham 2018-01-11 9:06 ` Gregory CLEMENT 0 siblings, 1 reply; 9+ messages in thread From: Chris Packham @ 2018-01-10 20:19 UTC (permalink / raw) To: Gregory CLEMENT Cc: jlu, linux, bp, linux-arm-kernel, linux-edac, linux-kernel, Jason Cooper, Andrew Lunn, Sebastian Hesselbarth, Rob Herring, Mark Rutland, devicetree On 10/01/18 21:31, Gregory CLEMENT wrote: > Hi Chris, > > On mar., janv. 09 2018, Chris Packham <chris.packham@alliedtelesis.co.nz> wrote: > >> The Armada-38x uses an SDRAM controller that is compatible with the >> Armada-XP. The key difference is the width of the bus (XP is 64/32, 38x >> is 32/16). The SDRAM controller registers are the same between the two >> SoCs. >> >> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> >> --- >> arch/arm/boot/dts/armada-38x.dtsi | 5 +++++ >> 1 file changed, 5 insertions(+) >> >> diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi >> index 00ff549d4e39..6d34c5ec178f 100644 >> --- a/arch/arm/boot/dts/armada-38x.dtsi >> +++ b/arch/arm/boot/dts/armada-38x.dtsi >> @@ -138,6 +138,11 @@ >> #size-cells = <1>; >> ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; >> >> + sdramc@1400 { > > Could you add a label? Thanks to this it would be possible to > enable/disable it at board level in a esay way. > Sure. Any suggestions for a name better than "sdramc:"? It's probably worth adding the same label to armada-xp.dtsi and armada-xp-98dx3236.dtsi. >> + compatible = "marvell,armada-xp-sdram-controller"; >> + reg = <0x1400 0x500>; > > What about adding status = "disabled" ? > > Thanks to this we can enable it at board level only if we really want > it, it would avoid nasty regression on boards that don't need it, if an > issue occurs. Unless you are sure that it is completely safe to enable > it for everyone. The EDAC driver (which is default n) will not probe the device if ECC has not been enabled so that should be safe. Other than the EDAC driver the only other code that looks at this is in arch/arm/mach-mvebu/pm.c and it almost seems like an omission that this code is not active on armada-38x. The armada-38x platforms I have access to don't use suspend/resume so I can't verify this. ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/3] ARM: dts: mvebu: add sdram controller node to Armada-38x 2018-01-10 20:19 ` Chris Packham @ 2018-01-11 9:06 ` Gregory CLEMENT 0 siblings, 0 replies; 9+ messages in thread From: Gregory CLEMENT @ 2018-01-11 9:06 UTC (permalink / raw) To: Chris Packham Cc: jlu, linux, bp, linux-arm-kernel, linux-edac, linux-kernel, Jason Cooper, Andrew Lunn, Sebastian Hesselbarth, Rob Herring, Mark Rutland, devicetree Hi Chris, On mer., janv. 10 2018, Chris Packham <Chris.Packham@alliedtelesis.co.nz> wrote: > On 10/01/18 21:31, Gregory CLEMENT wrote: >> Hi Chris, >> >> On mar., janv. 09 2018, Chris Packham <chris.packham@alliedtelesis.co.nz> wrote: >> >>> The Armada-38x uses an SDRAM controller that is compatible with the >>> Armada-XP. The key difference is the width of the bus (XP is 64/32, 38x >>> is 32/16). The SDRAM controller registers are the same between the two >>> SoCs. >>> >>> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> >>> --- >>> arch/arm/boot/dts/armada-38x.dtsi | 5 +++++ >>> 1 file changed, 5 insertions(+) >>> >>> diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi >>> index 00ff549d4e39..6d34c5ec178f 100644 >>> --- a/arch/arm/boot/dts/armada-38x.dtsi >>> +++ b/arch/arm/boot/dts/armada-38x.dtsi >>> @@ -138,6 +138,11 @@ >>> #size-cells = <1>; >>> ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; >>> >>> + sdramc@1400 { >> >> Could you add a label? Thanks to this it would be possible to >> enable/disable it at board level in a esay way. >> > > Sure. Any suggestions for a name better than "sdramc:"? For me sdramc: is fine. > > It's probably worth adding the same label to armada-xp.dtsi and > armada-xp-98dx3236.dtsi. Right. > >>> + compatible = "marvell,armada-xp-sdram-controller"; >>> + reg = <0x1400 0x500>; >> >> What about adding status = "disabled" ? >> >> Thanks to this we can enable it at board level only if we really want >> it, it would avoid nasty regression on boards that don't need it, if an >> issue occurs. Unless you are sure that it is completely safe to enable >> it for everyone. > > The EDAC driver (which is default n) will not probe the device if ECC > has not been enabled so that should be safe. OK in this case no need to disable it by default. Thanks, Gregory > > Other than the EDAC driver the only other code that looks at this is in > arch/arm/mach-mvebu/pm.c and it almost seems like an omission that this > code is not active on armada-38x. The armada-38x platforms I have access > to don't use suspend/resume so I can't verify this. > -- Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 3/3] EDAC: armada_xp: Add support for more SoCs 2018-01-08 22:31 [PATCH 0/3] EDAC: support for Armada 38x and 98dx3236 SoCs Chris Packham 2018-01-08 22:31 ` [PATCH 1/3] ARM: dts: enable L2 cache parity and ecc on db-xc3-24g4xg board Chris Packham 2018-01-08 22:31 ` [PATCH 2/3] ARM: dts: mvebu: add sdram controller node to Armada-38x Chris Packham @ 2018-01-08 22:31 ` Chris Packham 2 siblings, 0 replies; 9+ messages in thread From: Chris Packham @ 2018-01-08 22:31 UTC (permalink / raw) To: jlu, linux, bp, linux-arm-kernel, linux-edac Cc: linux-kernel, Chris Packham, Mauro Carvalho Chehab The Armada 38x and other integrated SoCs use a reduced pin count so the width of the SDRAM interface is smaller than the Armada XP SoCs. This means that the definition of "full" and "half" width is reduced from 64/32 to 32/16. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> --- drivers/edac/armada_xp_edac.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/edac/armada_xp_edac.c b/drivers/edac/armada_xp_edac.c index cb9173b30aa9..40cef261e61b 100644 --- a/drivers/edac/armada_xp_edac.c +++ b/drivers/edac/armada_xp_edac.c @@ -347,6 +347,11 @@ static int armada_xp_mc_edac_probe(struct platform_device *pdev) armada_xp_mc_edac_read_config(mci); + /* These SoCs have a reduced width bus */ + if (of_machine_is_compatible("marvell,armada380") || + of_machine_is_compatible("marvell,armadaxp-98dx3236")) + drvdata->width /= 2; + /* configure SBE threshold */ /* it seems that SBEs are not captured otherwise */ writel(1 << SDRAM_ERR_CTRL_ERR_THR_OFFSET, -- 2.15.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
end of thread, other threads:[~2018-01-11 9:06 UTC | newest] Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2018-01-08 22:31 [PATCH 0/3] EDAC: support for Armada 38x and 98dx3236 SoCs Chris Packham 2018-01-08 22:31 ` [PATCH 1/3] ARM: dts: enable L2 cache parity and ecc on db-xc3-24g4xg board Chris Packham 2018-01-10 8:24 ` Gregory CLEMENT 2018-01-10 20:08 ` Chris Packham 2018-01-08 22:31 ` [PATCH 2/3] ARM: dts: mvebu: add sdram controller node to Armada-38x Chris Packham 2018-01-10 8:31 ` Gregory CLEMENT 2018-01-10 20:19 ` Chris Packham 2018-01-11 9:06 ` Gregory CLEMENT 2018-01-08 22:31 ` [PATCH 3/3] EDAC: armada_xp: Add support for more SoCs Chris Packham
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