[PATCH 1/4] arm64: dts: qcom: msm8916: Add msm8916 A53 PLL DT node

[PATCH 1/4] arm64: dts: qcom: msm8916: Add msm8916 A53 PLL DT node

[Georgi Djakov]

Add a device tree node for the A53 PLL, which exists on msm8916
platforms.

Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
---
 arch/arm64/boot/dts/qcom/msm8916.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index e51b04900726..d3592b19cfc9 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -326,6 +326,12 @@
 			status = "disabled";
 		};
 
+		a53pll: clock@b016000 {
+			compatible = "qcom,msm8916-a53pll";
+			reg = <0xb016000 0x40>;
+			#clock-cells = <0>;
+		};
+
 		apcs: syscon@b011000 {
 			compatible = "syscon";
 			reg = <0x0b011000 0x1000>;

[PATCH 2/4] arm64: dts: qcom: msm8916: Probe the APCS mailbox driver

[Georgi Djakov]

The APCS block was exposed until now as a syscon, but now we have a
proper driver for this block. Add the compatible string of the new
driver to probe and register the mailbox functionality.

Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
---
 arch/arm64/boot/dts/qcom/msm8916.dtsi | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index d3592b19cfc9..5414f53a0fa1 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -332,9 +332,10 @@
 			#clock-cells = <0>;
 		};
 
-		apcs: syscon@b011000 {
-			compatible = "syscon";
-			reg = <0x0b011000 0x1000>;
+		apcs: mailbox@b011000 {
+			compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
+			reg = <0xb011000 0x1000>;
+			#mbox-cells = <1>;
 		};
 
 		blsp1_uart2: serial@78b0000 {

[PATCH 3/4] arm64: dts: qcom: msm8916: Add clock properties to the APCS node

[Georgi Djakov]

There are clock controller registers in the APCS block, which purpose
is to control the main CPU mux and divider. Add the clock properties as
part of the APCS device-tree node.

Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
---
 arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 5414f53a0fa1..4539571a36b2 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -336,6 +336,8 @@
 			compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
 			reg = <0xb011000 0x1000>;
 			#mbox-cells = <1>;
+			clocks = <&a53pll>;
+			#clock-cells = <0>;
 		};
 
 		blsp1_uart2: serial@78b0000 {

Re: [PATCH 3/4] arm64: dts: qcom: msm8916: Add clock properties to the APCS node

[Amit Kucheria]

On Mon, Feb 5, 2018 at 8:16 PM, Georgi Djakov <georgi.djakov@linaro.org> wrote:
> There are clock controller registers in the APCS block, which purpose

If you respin this, s/which/whose

> is to control the main CPU mux and divider. Add the clock properties as
> part of the APCS device-tree node.
>
> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
> ---
>  arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> index 5414f53a0fa1..4539571a36b2 100644
> --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> @@ -336,6 +336,8 @@
>                         compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
>                         reg = <0xb011000 0x1000>;
>                         #mbox-cells = <1>;
> +                       clocks = <&a53pll>;
> +                       #clock-cells = <0>;
>                 };
>
>                 blsp1_uart2: serial@78b0000 {
> --
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Re: [PATCH 3/4] arm64: dts: qcom: msm8916: Add clock properties to the APCS node

[Andy Gross]

On Wed, Feb 07, 2018 at 03:30:47PM +0530, Amit Kucheria wrote:
> On Mon, Feb 5, 2018 at 8:16 PM, Georgi Djakov <georgi.djakov@linaro.org> wrote:
> > There are clock controller registers in the APCS block, which purpose
> 
> If you respin this, s/which/whose

I can fix this when I apply them.  I'll make a note.  No need to respin.

Regards,

Andy

[PATCH 4/4] arm64: dts: qcom: msm8916: Add CPU frequency scaling support

[Georgi Djakov]

Add a CPU OPP table to allow CPU frequency scaling on msm8916 platforms.

Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
---
 arch/arm64/boot/dts/qcom/msm8916.dtsi | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 4539571a36b2..e4682779eec7 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -113,6 +113,8 @@
 			next-level-cache = <&L2_0>;
 			enable-method = "psci";
 			cpu-idle-states = <&CPU_SPC>;
+			clocks = <&apcs 0>;
+			operating-points-v2 = <&cpu_opp_table>;
 		};
 
 		CPU1: cpu@1 {
@@ -122,6 +124,8 @@
 			next-level-cache = <&L2_0>;
 			enable-method = "psci";
 			cpu-idle-states = <&CPU_SPC>;
+			clocks = <&apcs 0>;
+			operating-points-v2 = <&cpu_opp_table>;
 		};
 
 		CPU2: cpu@2 {
@@ -131,6 +135,8 @@
 			next-level-cache = <&L2_0>;
 			enable-method = "psci";
 			cpu-idle-states = <&CPU_SPC>;
+			clocks = <&apcs 0>;
+			operating-points-v2 = <&cpu_opp_table>;
 		};
 
 		CPU3: cpu@3 {
@@ -140,6 +146,8 @@
 			next-level-cache = <&L2_0>;
 			enable-method = "psci";
 			cpu-idle-states = <&CPU_SPC>;
+			clocks = <&apcs 0>;
+			operating-points-v2 = <&cpu_opp_table>;
 		};
 
 		L2_0: l2-cache {
@@ -212,6 +220,24 @@
 
 	};
 
+	cpu_opp_table: cpu_opp_table {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp-200000000 {
+			opp-hz = /bits/ 64 <200000000>;
+		};
+		opp-400000000 {
+			opp-hz = /bits/ 64 <400000000>;
+		};
+		opp-800000000 {
+			opp-hz = /bits/ 64 <800000000>;
+		};
+		opp-998400000 {
+			opp-hz = /bits/ 64 <998400000>;
+		};
+	};
+
 	gpu_opp_table: opp_table {
 		compatible = "operating-points-v2";
 

Re: [PATCH 4/4] arm64: dts: qcom: msm8916: Add CPU frequency scaling support

[Amit Kucheria]

On Mon, Feb 5, 2018 at 8:16 PM, Georgi Djakov <georgi.djakov@linaro.org> wrote:
> Add a CPU OPP table to allow CPU frequency scaling on msm8916 platforms.
>
> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>

For this series, please feel free to add my

Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>
Tested-by: Amit Kucheria <amit.kucheria@linaro.org>

It enables basic cpufreq on the DB410c in mainline after enabling
QCOM_APCS_IPC. I'll send out another patch to automatically select
this Kconfig option.

> ---
>  arch/arm64/boot/dts/qcom/msm8916.dtsi | 26 ++++++++++++++++++++++++++
>  1 file changed, 26 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> index 4539571a36b2..e4682779eec7 100644
> --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> @@ -113,6 +113,8 @@
>                         next-level-cache = <&L2_0>;
>                         enable-method = "psci";
>                         cpu-idle-states = <&CPU_SPC>;
> +                       clocks = <&apcs 0>;
> +                       operating-points-v2 = <&cpu_opp_table>;
>                 };
>
>                 CPU1: cpu@1 {
> @@ -122,6 +124,8 @@
>                         next-level-cache = <&L2_0>;
>                         enable-method = "psci";
>                         cpu-idle-states = <&CPU_SPC>;
> +                       clocks = <&apcs 0>;
> +                       operating-points-v2 = <&cpu_opp_table>;
>                 };
>
>                 CPU2: cpu@2 {
> @@ -131,6 +135,8 @@
>                         next-level-cache = <&L2_0>;
>                         enable-method = "psci";
>                         cpu-idle-states = <&CPU_SPC>;
> +                       clocks = <&apcs 0>;
> +                       operating-points-v2 = <&cpu_opp_table>;
>                 };
>
>                 CPU3: cpu@3 {
> @@ -140,6 +146,8 @@
>                         next-level-cache = <&L2_0>;
>                         enable-method = "psci";
>                         cpu-idle-states = <&CPU_SPC>;
> +                       clocks = <&apcs 0>;
> +                       operating-points-v2 = <&cpu_opp_table>;
>                 };
>
>                 L2_0: l2-cache {
> @@ -212,6 +220,24 @@
>
>         };
>
> +       cpu_opp_table: cpu_opp_table {
> +               compatible = "operating-points-v2";
> +               opp-shared;
> +
> +               opp-200000000 {
> +                       opp-hz = /bits/ 64 <200000000>;
> +               };
> +               opp-400000000 {
> +                       opp-hz = /bits/ 64 <400000000>;
> +               };
> +               opp-800000000 {
> +                       opp-hz = /bits/ 64 <800000000>;
> +               };
> +               opp-998400000 {
> +                       opp-hz = /bits/ 64 <998400000>;
> +               };
> +       };
> +
>         gpu_opp_table: opp_table {
>                 compatible = "operating-points-v2";
>