[RFC 0/4] Add Ingenic X1000 SoC Support

[RFC 0/4] Add Ingenic X1000 SoC Support

[PrasannaKumar Muralidharan]

Add support for Ingenic X1000 SoC. This patch set provides enough bits
to boot a kernel to an initramfs user space.

I implemented this code during 2016. Boot stuck at "calibrating delay
loop ...". Now I have fixed the issue by setting the correct irq. I do
not have access to this device anymore so could not test the fix.
Marking this patch series as RFC as this needs to be tested.

Test and feedback appreciated.

This series enables uart, timer and interrupt controller. As this is
very minimal a static elf binary should be used as init and should be
available in initramfs.

PrasannaKumar Muralidharan (4):
  dt-bindings: Add Ingenic X1000 SoC clock define
  clk: Add Ingenic X1000 CGU driver
  MIPS: Ingenic: Initial X1000 SoC support
  MIPS: Ingenic: Add Halley2 development board support

 arch/mips/boot/dts/ingenic/Makefile    |   1 +
 arch/mips/boot/dts/ingenic/halley2.dts |  46 ++++++++
 arch/mips/boot/dts/ingenic/x1000.dtsi  |  93 +++++++++++++++
 arch/mips/configs/halley2_defconfig    |  61 ++++++++++
 arch/mips/jz4740/Kconfig               |  10 ++
 arch/mips/jz4740/time.c                |   2 +-
 drivers/clk/ingenic/Makefile           |   1 +
 drivers/clk/ingenic/x1000-cgu.c        | 203 +++++++++++++++++++++++++++++++++
 include/dt-bindings/clock/x1000-cgu.h  |  46 ++++++++
 9 files changed, 462 insertions(+), 1 deletion(-)
 create mode 100644 arch/mips/boot/dts/ingenic/halley2.dts
 create mode 100644 arch/mips/boot/dts/ingenic/x1000.dtsi
 create mode 100644 arch/mips/configs/halley2_defconfig
 create mode 100644 drivers/clk/ingenic/x1000-cgu.c
 create mode 100644 include/dt-bindings/clock/x1000-cgu.h

-- 
2.10.0

[RFC 1/4] dt-bindings: Add Ingenic X1000 SoC clock define

[PrasannaKumar Muralidharan]

Ingenic X1000 SoC has different set of peripherals than JZ4780 and
JZ4740. Add a new device tree binding for the clock.

Signed-off-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
---
 include/dt-bindings/clock/x1000-cgu.h | 46 +++++++++++++++++++++++++++++++++++
 1 file changed, 46 insertions(+)
 create mode 100644 include/dt-bindings/clock/x1000-cgu.h

diff --git a/include/dt-bindings/clock/x1000-cgu.h b/include/dt-bindings/clock/x1000-cgu.h
new file mode 100644
index 0000000..17f05bc
--- /dev/null
+++ b/include/dt-bindings/clock/x1000-cgu.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2016 PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_X1000_CGU_H__
+#define __DT_BINDINGS_CLOCK_X1000_CGU_H__
+
+/* Add details for other peripherals when their support is added */
+#define X1000_CLK_EXCLK		0
+#define X1000_CLK_RTCLK		(X1000_CLK_EXCLK + 1)
+#define X1000_CLK_APLL		(X1000_CLK_RTCLK + 1)
+#define X1000_CLK_MPLL		(X1000_CLK_APLL + 1)
+
+#define X1000_CLK_SCLKA		(X1000_CLK_MPLL + 1)
+#define X1000_CLK_CPUMUX	(X1000_CLK_SCLKA + 1)
+#define X1000_CLK_CPU		(X1000_CLK_CPUMUX + 1)
+#define X1000_CLK_L2CACHE	(X1000_CLK_CPU + 1)
+#define X1000_CLK_AHB0		(X1000_CLK_L2CACHE + 1)
+#define X1000_CLK_AHB2PMUX	(X1000_CLK_AHB0 + 1)
+#define X1000_CLK_AHB2		(X1000_CLK_AHB2PMUX + 1)
+#define X1000_CLK_PCLK		(X1000_CLK_AHB2 + 1)
+#define X1000_CLK_DDR		(X1000_CLK_PCLK + 1)
+#define X1000_CLK_MSCMUX	(X1000_CLK_DDR + 1)
+#define X1000_CLK_MSC0		(X1000_CLK_MSCMUX + 1)
+#define X1000_CLK_MSC1		(X1000_CLK_MSC0 + 1)
+#define X1000_CLK_CIMMCLK	(X1000_CLK_MSC1 + 1)
+#define X1000_CLK_PCMPLL	(X1000_CLK_CIMMCLK + 1)
+#define X1000_CLK_PCM		(X1000_CLK_PCMPLL + 1)
+#define X1000_CLK_NEMC		(X1000_CLK_PCM + 1)
+#define X1000_CLK_UART0		(X1000_CLK_NEMC + 1)
+#define X1000_CLK_UART1		(X1000_CLK_UART0 + 1)
+#define X1000_CLK_UART2		(X1000_CLK_UART1 + 1)
+#define X1000_CLK_PDMA		(X1000_CLK_UART2 + 1)
+#define X1000_CLK_CIM		(X1000_CLK_PDMA + 1)
+#define X1000_CLK_DDR0		(X1000_CLK_CIM + 1)
+#define X1000_CLK_DDR1		(X1000_CLK_DDR0 + 1)
+#define X1000_CLK_CORE1		(X1000_CLK_DDR1	+ 1)
+
+#define X1000_CLK_I2SPLL	(X1000_CLK_CORE1 + 1)
+#define X1000_CLK_I2S		(X1000_CLK_I2SPLL + 1)
+
+#endif /* __DT_BINDINGS_CLOCK_X1000_CGU_H__ */
-- 
2.10.0

[RFC 2/4] clk: Add Ingenic X1000 CGU driver

[PrasannaKumar Muralidharan]

Add support for the clocks provided by CGU in Ingenic X1000 SoC.

Signed-off-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
---
 drivers/clk/ingenic/Makefile    |   1 +
 drivers/clk/ingenic/x1000-cgu.c | 203 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 204 insertions(+)
 create mode 100644 drivers/clk/ingenic/x1000-cgu.c

diff --git a/drivers/clk/ingenic/Makefile b/drivers/clk/ingenic/Makefile
index cd47b06..89c665b 100644
--- a/drivers/clk/ingenic/Makefile
+++ b/drivers/clk/ingenic/Makefile
@@ -1,3 +1,4 @@
 obj-y				+= cgu.o
 obj-$(CONFIG_MACH_JZ4740)	+= jz4740-cgu.o
 obj-$(CONFIG_MACH_JZ4780)	+= jz4780-cgu.o
+obj-$(CONFIG_MACH_X1000)	+= x1000-cgu.o
diff --git a/drivers/clk/ingenic/x1000-cgu.c b/drivers/clk/ingenic/x1000-cgu.c
new file mode 100644
index 0000000..a228688
--- /dev/null
+++ b/drivers/clk/ingenic/x1000-cgu.c
@@ -0,0 +1,203 @@
+/*
+ * Ingenic X1000 SoC CGU driver
+ *
+ * Copyright (c) 2016 PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/of.h>
+#include <dt-bindings/clock/x1000-cgu.h>
+#include "cgu.h"
+
+/* CGU register offsets */
+#define CGU_REG_CLOCKCONTROL	0x00
+#define CGU_REG_APLL		0x10
+#define CGU_REG_MPLL		0x14
+
+/* CLKGR0, OPCR are not defined in X1000, JZ4780 PM so assuming them to be correct */
+#define CGU_REG_CLKGR0		0x20
+#define CGU_REG_OPCR		0x24
+#define CGU_REG_CLKGR1		0x28
+#define CGU_REG_DDRCDR		0x2c
+
+/* bits within the OPCR register */
+#define OPCR_SPENDN0		(1 << 7)
+#define OPCR_SPENDN1		(1 << 6)
+
+static struct ingenic_cgu *cgu;
+
+static const s8 pll_od_encoding[16] = {
+	0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7,
+	0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
+};
+
+static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
+
+	/* External clocks */
+
+	[X1000_CLK_EXCLK] = { "ext", CGU_CLK_EXT },
+	[X1000_CLK_RTCLK] = { "rtc", CGU_CLK_EXT },
+
+	/* PLLs */
+
+#define DEF_PLL(name) { \
+	.reg = CGU_REG_ ## name, \
+	.m_shift = 19, \
+	.m_bits = 13, \
+	.m_offset = 1, \
+	.n_shift = 13, \
+	.n_bits = 6, \
+	.n_offset = 1, \
+	.od_shift = 9, \
+	.od_bits = 4, \
+	.od_max = 16, \
+	.od_encoding = pll_od_encoding, \
+	.stable_bit = 6, \
+	.bypass_bit = 1, \
+	.enable_bit = 0, \
+}
+
+	[X1000_CLK_APLL] = {
+		"apll", CGU_CLK_PLL,
+		.parents = { X1000_CLK_EXCLK, -1, -1, -1 },
+		.pll = DEF_PLL(APLL),
+	},
+
+	[X1000_CLK_MPLL] = {
+		"mpll", CGU_CLK_PLL,
+		.parents = { X1000_CLK_EXCLK, -1, -1, -1 },
+		.pll = DEF_PLL(MPLL),
+	},
+
+#undef DEF_PLL
+
+	/* Muxes & dividers */
+
+	[X1000_CLK_SCLKA] = {
+		"sclk_a", CGU_CLK_MUX,
+		.parents = { -1, X1000_CLK_APLL, X1000_CLK_EXCLK,
+			     X1000_CLK_RTCLK },
+		.mux = { CGU_REG_CLOCKCONTROL, 30, 2 },
+	},
+
+	[X1000_CLK_CPUMUX] = {
+		"cpumux", CGU_CLK_MUX,
+		.parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL,
+			     -1 },
+		.mux = { CGU_REG_CLOCKCONTROL, 28, 2 },
+	},
+
+	[X1000_CLK_CPU] = {
+		"cpu", CGU_CLK_DIV,
+		.parents = { X1000_CLK_CPUMUX, -1, -1, -1 },
+		.div = { CGU_REG_CLOCKCONTROL, 0, 1, 4, 22, -1, -1 },
+	},
+
+	[X1000_CLK_L2CACHE] = {
+		"l2cache", CGU_CLK_DIV,
+		.parents = { X1000_CLK_CPUMUX, -1, -1, -1 },
+		.div = { CGU_REG_CLOCKCONTROL, 4, 1, 4, -1, -1, -1 },
+	},
+
+	[X1000_CLK_AHB0] = {
+		"ahb0", CGU_CLK_MUX | CGU_CLK_DIV,
+		.parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL,
+			     -1 },
+		.mux = { CGU_REG_CLOCKCONTROL, 26, 2 },
+		.div = { CGU_REG_CLOCKCONTROL, 8, 1, 4, 21, -1, -1 },
+	},
+
+	[X1000_CLK_AHB2PMUX] = {
+		"ahb2_apb_mux", CGU_CLK_MUX,
+		.parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL,
+			     X1000_CLK_RTCLK },
+		.mux = { CGU_REG_CLOCKCONTROL, 24, 2 },
+	},
+
+	[X1000_CLK_AHB2] = {
+		"ahb2", CGU_CLK_DIV,
+		.parents = { X1000_CLK_AHB2PMUX, -1, -1, -1 },
+		.div = { CGU_REG_CLOCKCONTROL, 12, 1, 4, 20, -1, -1 },
+	},
+
+	[X1000_CLK_PCLK] = {
+		"pclk", CGU_CLK_DIV,
+		.parents = { X1000_CLK_AHB2PMUX, -1, -1, -1 },
+		.div = { CGU_REG_CLOCKCONTROL, 16, 1, 4, 20, -1, -1 },
+	},
+
+	[X1000_CLK_DDR] = {
+		"ddr", CGU_CLK_MUX | CGU_CLK_DIV,
+		.parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
+		.mux = { CGU_REG_DDRCDR, 30, 2 },
+		.div = { CGU_REG_DDRCDR, 0, 1, 4, 29, 28, 27 },
+	},
+
+	/* Gate-only clocks */
+
+	[X1000_CLK_UART0] = {
+		"uart0", CGU_CLK_GATE,
+		.parents = { X1000_CLK_EXCLK, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR0, 15 },
+	},
+
+	[X1000_CLK_UART1] = {
+		"uart1", CGU_CLK_GATE,
+		.parents = { X1000_CLK_EXCLK, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR0, 16 },
+	},
+
+	[X1000_CLK_UART2] = {
+		"uart2", CGU_CLK_GATE,
+		.parents = { X1000_CLK_EXCLK, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR0, 17 },
+	},
+
+	[X1000_CLK_PDMA] = {
+		"pdma", CGU_CLK_GATE,
+		.parents = { X1000_CLK_EXCLK, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR0, 21 },
+	},
+
+	[X1000_CLK_DDR0] = {
+		"ddr0", CGU_CLK_GATE,
+		.parents = { X1000_CLK_DDR, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR0, 30 },
+	},
+
+	[X1000_CLK_DDR1] = {
+		"ddr1", CGU_CLK_GATE,
+		.parents = { X1000_CLK_DDR, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR0, 31 },
+	},
+
+	[X1000_CLK_CORE1] = {
+		"core1", CGU_CLK_GATE,
+		.parents = { X1000_CLK_CPU, -1, -1, -1 },
+		.gate = { CGU_REG_CLKGR1, 15 },
+	},
+};
+
+static void __init x1000_cgu_init(struct device_node *np)
+{
+	int retval;
+
+	cgu = ingenic_cgu_new(x1000_cgu_clocks,
+			      ARRAY_SIZE(x1000_cgu_clocks), np);
+	if (!cgu) {
+		pr_err("%s: failed to initialise CGU\n", __func__);
+		return;
+	}
+
+	retval = ingenic_cgu_register_clocks(cgu);
+	if (retval) {
+		pr_err("%s: failed to register CGU Clocks\n", __func__);
+		return;
+	}
+}
+CLK_OF_DECLARE(x1000_cgu, "ingenic,x1000-cgu", x1000_cgu_init);
-- 
2.10.0

[RFC 3/4] MIPS: Ingenic: Initial X1000 SoC support

[PrasannaKumar Muralidharan]

Add initial Ingenic X1000 SoC support. Provide minimum necessary
information to boot kernel to an initramfs userspace.

Signed-off-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
---
 arch/mips/boot/dts/ingenic/x1000.dtsi | 93 +++++++++++++++++++++++++++++++++++
 arch/mips/jz4740/Kconfig              |  6 +++
 arch/mips/jz4740/time.c               |  2 +-
 3 files changed, 100 insertions(+), 1 deletion(-)
 create mode 100644 arch/mips/boot/dts/ingenic/x1000.dtsi

diff --git a/arch/mips/boot/dts/ingenic/x1000.dtsi b/arch/mips/boot/dts/ingenic/x1000.dtsi
new file mode 100644
index 0000000..abbb9ec
--- /dev/null
+++ b/arch/mips/boot/dts/ingenic/x1000.dtsi
@@ -0,0 +1,93 @@
+/*
+ * Copyright (C) 2016 PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <dt-bindings/clock/x1000-cgu.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	compatible = "ingenic,x1000";
+
+	cpuintc: interrupt-controller {
+		#address-cells = <0>;
+		#interrupt-cells = <1>;
+		interrupt-controller;
+		compatible = "mti,cpu-interrupt-controller";
+	};
+
+	intc: interrupt-controller@10001000 {
+		compatible = "ingenic,x1000-intc", "ingenic,jz4780-intc";
+		reg = <0x10001000 0x50>;
+
+		interrupt-controller;
+		#interrupt-cells = <1>;
+
+		interrupt-parent = <&cpuintc>;
+		interrupts = <2>;
+	};
+
+	ext: ext {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+	};
+
+	rtc: rtc {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+	};
+
+	cgu: jz4780-cgu@10000000 {
+		compatible = "ingenic,x1000-cgu";
+		reg = <0x10000000 0x100>;
+
+		clocks = <&ext>, <&rtc>;
+		clock-names = "ext", "rtc";
+
+		#clock-cells = <1>;
+	};
+
+	uart0: serial@10030000 {
+		compatible = "ingenic,x1000-uart", "ingenic,jz4780-uart";
+		reg = <0x10030000 0x100>;
+
+		interrupt-parent = <&intc>;
+		interrupts = <51>;
+
+		clocks = <&ext>, <&cgu X1000_CLK_UART0>;
+		clock-names = "baud", "module";
+
+		status = "disabled";
+	};
+
+	uart1: serial@10031000 {
+		compatible = "ingenic,x1000-uart", "ingenic,jz4780-uart";
+		reg = <0x10031000 0x100>;
+
+		interrupt-parent = <&intc>;
+		interrupts = <50>;
+
+		clocks = <&ext>, <&cgu X1000_CLK_UART1>;
+		clock-names = "baud", "module";
+
+		status = "disabled";
+	};
+
+	uart2: serial@10032000 {
+		compatible = "ingenic,x1000-uart", "ingenic,jz4780-uart";
+		reg = <0x10032000 0x100>;
+
+		interrupt-parent = <&intc>;
+		interrupts = <49>;
+
+		clocks = <&ext>, <&cgu X1000_CLK_UART2>;
+		clock-names = "baud", "module";
+
+		status = "disabled";
+	};
+};
diff --git a/arch/mips/jz4740/Kconfig b/arch/mips/jz4740/Kconfig
index 36f8201..338bc3f 100644
--- a/arch/mips/jz4740/Kconfig
+++ b/arch/mips/jz4740/Kconfig
@@ -22,3 +22,9 @@ config MACH_JZ4780
 	select MIPS_CPU_SCACHE
 	select SYS_HAS_CPU_MIPS32_R2
 	select SYS_SUPPORTS_HIGHMEM
+
+config MACH_X1000
+	bool
+	select MIPS_CPU_SCACHE
+	select SYS_HAS_CPU_MIPS32_R2
+	select SYS_HAS_EARLY_PRINTK
diff --git a/arch/mips/jz4740/time.c b/arch/mips/jz4740/time.c
index bb1ad51..e28c734 100644
--- a/arch/mips/jz4740/time.c
+++ b/arch/mips/jz4740/time.c
@@ -113,7 +113,7 @@ static struct clock_event_device jz4740_clockevent = {
 #ifdef CONFIG_MACH_JZ4740
 	.irq = JZ4740_IRQ_TCU0,
 #endif
-#ifdef CONFIG_MACH_JZ4780
+#if defined CONFIG_MACH_JZ4780 || defined CONFIG_MACH_X1000
 	.irq = JZ4780_IRQ_TCU2,
 #endif
 };
-- 
2.10.0

[RFC 4/4] MIPS: Ingenic: Add Halley2 development board support

[PrasannaKumar Muralidharan]

Halley2 is a development board from Ingenic using X1000 SoC. It comes
with either 32MB or 64MB of RAM. Add support for halley2 development
board.

Signed-off-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
---
 arch/mips/boot/dts/ingenic/Makefile    |  1 +
 arch/mips/boot/dts/ingenic/halley2.dts | 46 +++++++++++++++++++++++++
 arch/mips/configs/halley2_defconfig    | 61 ++++++++++++++++++++++++++++++++++
 arch/mips/jz4740/Kconfig               |  4 +++
 4 files changed, 112 insertions(+)
 create mode 100644 arch/mips/boot/dts/ingenic/halley2.dts
 create mode 100644 arch/mips/configs/halley2_defconfig

diff --git a/arch/mips/boot/dts/ingenic/Makefile b/arch/mips/boot/dts/ingenic/Makefile
index f2b864f..68e942c 100644
--- a/arch/mips/boot/dts/ingenic/Makefile
+++ b/arch/mips/boot/dts/ingenic/Makefile
@@ -1,5 +1,6 @@
 dtb-$(CONFIG_JZ4740_QI_LB60)	+= qi_lb60.dtb
 dtb-$(CONFIG_JZ4780_CI20)	+= ci20.dtb
+dtb-$(CONFIG_X1000_HALLEY2)	+= halley2.dtb
 
 obj-y				+= $(patsubst %.dtb, %.dtb.o, $(dtb-y))
 
diff --git a/arch/mips/boot/dts/ingenic/halley2.dts b/arch/mips/boot/dts/ingenic/halley2.dts
new file mode 100644
index 0000000..9b37119
--- /dev/null
+++ b/arch/mips/boot/dts/ingenic/halley2.dts
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2016 PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+#include "x1000.dtsi"
+
+/ {
+	compatible = "ingenic,halley2", "ingenic,x1000";
+
+	aliases {
+		serial0 = &uart0;
+		serial1 = &uart1;
+		serial2 = &uart2;
+	};
+
+	chosen {
+		stdout-path = &uart2;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x2000000>;
+	};
+};
+
+&ext {
+	clock-frequency = <24000000>;
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
diff --git a/arch/mips/configs/halley2_defconfig b/arch/mips/configs/halley2_defconfig
new file mode 100644
index 0000000..2c49fb7
--- /dev/null
+++ b/arch/mips/configs/halley2_defconfig
@@ -0,0 +1,61 @@
+CONFIG_MACH_INGENIC=y
+CONFIG_X1000_HALLEY2=y
+CONFIG_MACH_X1000=y
+
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=3
+CONFIG_SERIAL_8250_RUNTIME_UARTS=3
+CONFIG_SERIAL_8250_INGENIC=y
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_EARLY_PRINTK is not set
+CONFIG_MEMORY=y
+
+CONFIG_PRINTK_TIME=y
+CONFIG_DEBUG_INFO=y
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_DEBUG_FS=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_LOCKUP_DETECTOR=y
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
+CONFIG_PANIC_ON_OOPS=y
+CONFIG_PANIC_TIMEOUT=10
+CONFIG_STACKTRACE=y
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="earlycon console=ttyS2,115200n8 clk_ignore_unused"
+
+CONFIG_HZ_100=y
+CONFIG_HIGHMEM=y
+CONFIG_PREEMPT=y
+CONFIG_KERNEL_XZ=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_FHANDLE=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_CGROUPS=y
+CONFIG_MEMCG=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CPUSETS=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_NAMESPACES=y
+CONFIG_USER_NS=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_LEGACY_PTY_COUNT=2
+
+# CONFIG_SUSPEND is not set
+# CONFIG_HIBERNATION is not set
+# CONFIG_PM is not set
diff --git a/arch/mips/jz4740/Kconfig b/arch/mips/jz4740/Kconfig
index 338bc3f..7c66a4b 100644
--- a/arch/mips/jz4740/Kconfig
+++ b/arch/mips/jz4740/Kconfig
@@ -11,6 +11,10 @@ config JZ4780_CI20
 	bool "MIPS Creator CI20"
 	select MACH_JZ4780
 
+config X1000_HALLEY2
+	bool "Ingenic X1000 Halley2 Development board"
+	select MACH_X1000
+
 endchoice
 
 config MACH_JZ4740
-- 
2.10.0

Re: [RFC 2/4] clk: Add Ingenic X1000 CGU driver

[Stephen Boyd]

On 09/27, PrasannaKumar Muralidharan wrote:
> Add support for the clocks provided by CGU in Ingenic X1000 SoC.
> 
> Signed-off-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
> ---

Acked-by: Stephen Boyd <sboyd@codeaurora.org>

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [RFC 3/4] MIPS: Ingenic: Initial X1000 SoC support

[James Hogan]

[-- Attachment #1: Type: text/plain, Size: 1671 bytes --]

On Wed, Sep 27, 2017 at 08:45:26PM +0530, PrasannaKumar Muralidharan wrote:
> Add initial Ingenic X1000 SoC support. Provide minimum necessary
> information to boot kernel to an initramfs userspace.
> 
> Signed-off-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
> ---
>  arch/mips/boot/dts/ingenic/x1000.dtsi | 93 +++++++++++++++++++++++++++++++++++
>  arch/mips/jz4740/Kconfig              |  6 +++
>  arch/mips/jz4740/time.c               |  2 +-
>  3 files changed, 100 insertions(+), 1 deletion(-)
>  create mode 100644 arch/mips/boot/dts/ingenic/x1000.dtsi

arch/mips/jz4780/setup.c, specifically get_board_mach_type() and
get_system_type() will need updating too.

Does X1000 use a different PRID, or is it basically just a JZ4780 core
with different SoC peripherals?

> diff --git a/arch/mips/boot/dts/ingenic/x1000.dtsi b/arch/mips/boot/dts/ingenic/x1000.dtsi
> new file mode 100644
> index 0000000..abbb9ec
> --- /dev/null
> +++ b/arch/mips/boot/dts/ingenic/x1000.dtsi
> @@ -0,0 +1,93 @@
> +/*
> + * Copyright (C) 2016 PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.

(these will need updating to use SPDX identifiers if you respin)

> +	cgu: jz4780-cgu@10000000 {

not sure jz4780 is appropriate here.

> +		compatible = "ingenic,x1000-cgu";
> +		reg = <0x10000000 0x100>;
> +
> +		clocks = <&ext>, <&rtc>;
> +		clock-names = "ext", "rtc";
> +
> +		#clock-cells = <1>;
> +	};

Cheers
James

[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

Re: [RFC 3/4] MIPS: Ingenic: Initial X1000 SoC support

[PrasannaKumar Muralidharan]

Hi James,

Thanks for reviewing this.

On 6 March 2018 at 05:38, James Hogan <jhogan@kernel.org> wrote:
> On Wed, Sep 27, 2017 at 08:45:26PM +0530, PrasannaKumar Muralidharan wrote:
>> Add initial Ingenic X1000 SoC support. Provide minimum necessary
>> information to boot kernel to an initramfs userspace.
>>
>> Signed-off-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
>> ---
>>  arch/mips/boot/dts/ingenic/x1000.dtsi | 93 +++++++++++++++++++++++++++++++++++
>>  arch/mips/jz4740/Kconfig              |  6 +++
>>  arch/mips/jz4740/time.c               |  2 +-
>>  3 files changed, 100 insertions(+), 1 deletion(-)
>>  create mode 100644 arch/mips/boot/dts/ingenic/x1000.dtsi
>
> arch/mips/jz4780/setup.c, specifically get_board_mach_type() and
> get_system_type() will need updating too.

Missed it. Will make necessary changes.

> Does X1000 use a different PRID, or is it basically just a JZ4780 core
> with different SoC peripherals?

Yes X1000 does have a different PRID (PRID = 0x2ed1024f). X1000 has
single CPU core so it is definitely not JZ4780.

>> diff --git a/arch/mips/boot/dts/ingenic/x1000.dtsi b/arch/mips/boot/dts/ingenic/x1000.dtsi
>> new file mode 100644
>> index 0000000..abbb9ec
>> --- /dev/null
>> +++ b/arch/mips/boot/dts/ingenic/x1000.dtsi
>> @@ -0,0 +1,93 @@
>> +/*
>> + * Copyright (C) 2016 PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
>> + *
>> + * This file is licensed under the terms of the GNU General Public
>> + * License version 2. This program is licensed "as is" without any
>> + * warranty of any kind, whether express or implied.
>
> (these will need updating to use SPDX identifiers if you respin)

Sure. Will take care while submitting next version.

>> +     cgu: jz4780-cgu@10000000 {
>
> not sure jz4780 is appropriate here.

No, it is not. Copy pasted from jz4780.dtsi but missed updating this.

>> +             compatible = "ingenic,x1000-cgu";
>> +             reg = <0x10000000 0x100>;
>> +
>> +             clocks = <&ext>, <&rtc>;
>> +             clock-names = "ext", "rtc";
>> +
>> +             #clock-cells = <1>;
>> +     };
>
> Cheers
> James

I used to get my code tested from Domink but I could not reach him for
quite some time. Before buying the development board myself I would
like to see if anyone can help me in testing. Do you have any contact
with Ingenic who can help in testing this?

Thanks,
PrasannaKumar

Re: [RFC 3/4] MIPS: Ingenic: Initial X1000 SoC support

[Jiaxun Yang]

在 2018-03-07三的 19:14 +0530，PrasannaKumar Muralidharan写道：
> 
> I used to get my code tested from Domink but I could not reach him
> for
> quite some time. Before buying the development board myself I would
> like to see if anyone can help me in testing. Do you have any contact
> with Ingenic who can help in testing this?
> 

Hi PrasannaKumar

I'm resently working on Ingenic chips too. Ingentic guys have sent me a
X1000 development broad and it will arrive in about two weeks. I have a
ejtag debugger also (but not very suit with X1000 because X1000 have
different ejtag interface with standard MIPS cores, maybe we need some
modification on openocd). So maybe I can help in testing this after I
get my broad. Just ask if you need any help.
Thanks
-- 
Jiaxun Yang <jiaxun.yang@flygoat.com>

Re: [RFC 3/4] MIPS: Ingenic: Initial X1000 SoC support

[James Hogan]

[-- Attachment #1: Type: text/plain, Size: 905 bytes --]

On Wed, Mar 07, 2018 at 07:14:49PM +0530, PrasannaKumar Muralidharan wrote:
> > Does X1000 use a different PRID, or is it basically just a JZ4780 core
> > with different SoC peripherals?
> 
> Yes X1000 does have a different PRID (PRID = 0x2ed1024f). X1000 has

Right, so thats 0x2e000000 | PRID_COMP_INGENIC_D1 | PRID_IMP_JZRISC |
0x4f, which cpu-probe.c already handles (apparently the D1 company code
is used for JZ4770 & JZ4775 too).

> I used to get my code tested from Domink but I could not reach him for
> quite some time. Before buying the development board myself I would
> like to see if anyone can help me in testing. Do you have any contact
> with Ingenic who can help in testing this?

Not personally, but I'll ask around. Of course if nobody much cares
about it in practice and nobody has the hardware, there may be little
value in supporting it upstream.

Cheers
James

[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

Re: [RFC 3/4] MIPS: Ingenic: Initial X1000 SoC support

[PrasannaKumar Muralidharan]

Hi James,

On 7 March 2018 at 20:05, James Hogan <jhogan@kernel.org> wrote:
> On Wed, Mar 07, 2018 at 07:14:49PM +0530, PrasannaKumar Muralidharan wrote:
>> > Does X1000 use a different PRID, or is it basically just a JZ4780 core
>> > with different SoC peripherals?
>>
>> Yes X1000 does have a different PRID (PRID = 0x2ed1024f). X1000 has
>
> Right, so thats 0x2e000000 | PRID_COMP_INGENIC_D1 | PRID_IMP_JZRISC |
> 0x4f, which cpu-probe.c already handles (apparently the D1 company code
> is used for JZ4770 & JZ4775 too).

Okay. Does this mean I need not modify get_board_mach_type() and
get_system_type()?

>> I used to get my code tested from Domink but I could not reach him for
>> quite some time. Before buying the development board myself I would
>> like to see if anyone can help me in testing. Do you have any contact
>> with Ingenic who can help in testing this?
>
> Not personally, but I'll ask around. Of course if nobody much cares
> about it in practice and nobody has the hardware, there may be little
> value in supporting it upstream.

Seems Jiaxun is interested in the board and is willing to help.

I have been told that Ingenic is focusing on IoT market and X1000 is
intended for IoT segment. I think that they would be selling several
100Ks of chip over the coming years. But I feel Ingenic spends time
only on maintaining their Linux port which is usually based on very
old kernel version.

> Cheers
> James

Thanks and regards,
PrasannaKumar

Re: [RFC 3/4] MIPS: Ingenic: Initial X1000 SoC support

[James Hogan]

[-- Attachment #1: Type: text/plain, Size: 1432 bytes --]

On Wed, Mar 07, 2018 at 08:35:00PM +0530, PrasannaKumar Muralidharan wrote:
> On 7 March 2018 at 20:05, James Hogan <jhogan@kernel.org> wrote:
> > On Wed, Mar 07, 2018 at 07:14:49PM +0530, PrasannaKumar Muralidharan wrote:
> >> > Does X1000 use a different PRID, or is it basically just a JZ4780 core
> >> > with different SoC peripherals?
> >>
> >> Yes X1000 does have a different PRID (PRID = 0x2ed1024f). X1000 has
> >
> > Right, so thats 0x2e000000 | PRID_COMP_INGENIC_D1 | PRID_IMP_JZRISC |
> > 0x4f, which cpu-probe.c already handles (apparently the D1 company code
> > is used for JZ4770 & JZ4775 too).
> 
> Okay. Does this mean I need not modify get_board_mach_type() and
> get_system_type()?

You still need to modify them, otherwise it won't understand
"ingenic,x1000" compatible string, and will call it a JZ4740 in
/proc/cpuinfo.

> >> I used to get my code tested from Domink but I could not reach him for
> >> quite some time. Before buying the development board myself I would
> >> like to see if anyone can help me in testing. Do you have any contact
> >> with Ingenic who can help in testing this?
> >
> > Not personally, but I'll ask around. Of course if nobody much cares
> > about it in practice and nobody has the hardware, there may be little
> > value in supporting it upstream.
> 
> Seems Jiaxun is interested in the board and is willing to help.

Okay, cool.

Cheers
James

[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

Re: [RFC 3/4] MIPS: Ingenic: Initial X1000 SoC support

[PrasannaKumar Muralidharan]

Hi Jiaxun,

On 7 March 2018 at 19:49, Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
> 在 2018-03-07三的 19:14 +0530，PrasannaKumar Muralidharan写道：
>>
>> I used to get my code tested from Domink but I could not reach him
>> for
>> quite some time. Before buying the development board myself I would
>> like to see if anyone can help me in testing. Do you have any contact
>> with Ingenic who can help in testing this?
>>
>
> Hi PrasannaKumar
>
> I'm resently working on Ingenic chips too. Ingentic guys have sent me a
> X1000 development broad and it will arrive in about two weeks. I have a
> ejtag debugger also (but not very suit with X1000 because X1000 have
> different ejtag interface with standard MIPS cores, maybe we need some
> modification on openocd). So maybe I can help in testing this after I
> get my broad. Just ask if you need any help.
> Thanks
> --
> Jiaxun Yang <jiaxun.yang@flygoat.com>

Really nice to hear. I will ask for help once I make changes.

Thanks,
PrasannaKumar

Re: [RFC 3/4] MIPS: Ingenic: Initial X1000 SoC support

[PrasannaKumar Muralidharan]

On 7 March 2018 at 20:40, James Hogan <jhogan@kernel.org> wrote:
> On Wed, Mar 07, 2018 at 08:35:00PM +0530, PrasannaKumar Muralidharan wrote:
>> On 7 March 2018 at 20:05, James Hogan <jhogan@kernel.org> wrote:
>> > On Wed, Mar 07, 2018 at 07:14:49PM +0530, PrasannaKumar Muralidharan wrote:
>> >> > Does X1000 use a different PRID, or is it basically just a JZ4780 core
>> >> > with different SoC peripherals?
>> >>
>> >> Yes X1000 does have a different PRID (PRID = 0x2ed1024f). X1000 has
>> >
>> > Right, so thats 0x2e000000 | PRID_COMP_INGENIC_D1 | PRID_IMP_JZRISC |
>> > 0x4f, which cpu-probe.c already handles (apparently the D1 company code
>> > is used for JZ4770 & JZ4775 too).
>>
>> Okay. Does this mean I need not modify get_board_mach_type() and
>> get_system_type()?
>
> You still need to modify them, otherwise it won't understand
> "ingenic,x1000" compatible string, and will call it a JZ4740 in
> /proc/cpuinfo.

Oh okay. Will make the changes.

>> >> I used to get my code tested from Domink but I could not reach him for
>> >> quite some time. Before buying the development board myself I would
>> >> like to see if anyone can help me in testing. Do you have any contact
>> >> with Ingenic who can help in testing this?
>> >
>> > Not personally, but I'll ask around. Of course if nobody much cares
>> > about it in practice and nobody has the hardware, there may be little
>> > value in supporting it upstream.
>>
>> Seems Jiaxun is interested in the board and is willing to help.
>
> Okay, cool.
>
> Cheers
> James

Re: [RFC 3/4] MIPS: Ingenic: Initial X1000 SoC support

[Jiaxun Yang]

在 2018-03-07三的 20:35 +0530，PrasannaKumar Muralidharan写道：
> Hi James,
> 
> Seems Jiaxun is interested in the board and is willing to help.
> 
> I have been told that Ingenic is focusing on IoT market and X1000 is
> intended for IoT segment. I think that they would be selling several
> 100Ks of chip over the coming years. But I feel Ingenic spends time
> only on maintaining their Linux port which is usually based on very
> old kernel version.

Ingenic is going to release their XBrust2 core with it's products such
as X2000 a few days later. Witch is a pure MIPS64r5 with MXU2(A
superset of MIPS's MSA SIMD instruction set). The newest kernel port of
X1000 maintain by Ingenic is based on Linux-4.4 [1]. After communicated
with Ingenic, they said they are forcusing on China domestic market.
But they're looking for partners to enter foriegn market. 

[1] https://pan.baidu.com/s/1o8MeYts (Well you can download from this
Chinese website, ingenic have a gerrit but I don't have access to it.
As my experience, it's hard to develop on Chinese-made chips wihout
reading Chinese documents.)  
> 
> > 

Re: [RFC 3/4] MIPS: Ingenic: Initial X1000 SoC support

[PrasannaKumar Muralidharan]

On 7 March 2018 at 21:22, Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
> 在 2018-03-07三的 20:35 +0530，PrasannaKumar Muralidharan写道：
>> Hi James,
>>
>> Seems Jiaxun is interested in the board and is willing to help.
>>
>> I have been told that Ingenic is focusing on IoT market and X1000 is
>> intended for IoT segment. I think that they would be selling several
>> 100Ks of chip over the coming years. But I feel Ingenic spends time
>> only on maintaining their Linux port which is usually based on very
>> old kernel version.
>
> Ingenic is going to release their XBrust2 core with it's products such
> as X2000 a few days later. Witch is a pure MIPS64r5 with MXU2(A
> superset of MIPS's MSA SIMD instruction set). The newest kernel port of
> X1000 maintain by Ingenic is based on Linux-4.4 [1]. After communicated
> with Ingenic, they said they are forcusing on China domestic market.
> But they're looking for partners to enter foriegn market.
>
> [1] https://pan.baidu.com/s/1o8MeYts (Well you can download from this
> Chinese website, ingenic have a gerrit but I don't have access to it.
> As my experience, it's hard to develop on Chinese-made chips wihout
> reading Chinese documents.)

Can you take a diff and upload it somewhere else? Download speed is a
couple of bytes per second. Can you put the diff in github or similar
other service?
I would like to see if the port uses DT.

Re: [RFC 3/4] MIPS: Ingenic: Initial X1000 SoC support

[Mathieu Malaterre]

On Wed, Mar 7, 2018 at 5:25 PM, PrasannaKumar Muralidharan
<prasannatsmkumar@gmail.com> wrote:
> On 7 March 2018 at 21:22, Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
>> 在 2018-03-07三的 20:35 +0530，PrasannaKumar Muralidharan写道：
>>> Hi James,
>>>
>>> Seems Jiaxun is interested in the board and is willing to help.
>>>
>>> I have been told that Ingenic is focusing on IoT market and X1000 is
>>> intended for IoT segment. I think that they would be selling several
>>> 100Ks of chip over the coming years. But I feel Ingenic spends time
>>> only on maintaining their Linux port which is usually based on very
>>> old kernel version.
>>
>> Ingenic is going to release their XBrust2 core with it's products such
>> as X2000 a few days later. Witch is a pure MIPS64r5 with MXU2(A
>> superset of MIPS's MSA SIMD instruction set). The newest kernel port of
>> X1000 maintain by Ingenic is based on Linux-4.4 [1]. After communicated
>> with Ingenic, they said they are forcusing on China domestic market.
>> But they're looking for partners to enter foriegn market.
>>
>> [1] https://pan.baidu.com/s/1o8MeYts (Well you can download from this
>> Chinese website, ingenic have a gerrit but I don't have access to it.
>> As my experience, it's hard to develop on Chinese-made chips wihout
>> reading Chinese documents.)
>
> Can you take a diff and upload it somewhere else? Download speed is a
> couple of bytes per second. Can you put the diff in github or similar
> other service?
> I would like to see if the port uses DT.

Technically this was documented here:

ftp://ftp.ingenic.cn/DevSupport/Linux/Linux-3.0.8/JZ4780/JZ4780_linux_development_guide_EN.pdf

Go to §2.1 Download Source Code:

1) Download repo a) $ mkdir b) $ cd c) $ wget
http://git.ingenic.cn:8082/bj/repo d) $ chmod +x repo

However everything seems to be gone (including the gerrit page).

2ctc

Re: [RFC 3/4] MIPS: Ingenic: Initial X1000 SoC support

[Jiaxun Yang]

在 2018-03-07三的 19:13 +0100，Mathieu Malaterre写道：
> > > [1] https://pan.baidu.com/s/1o8MeYts (Well you can download from
> > > this
> > > Chinese website, ingenic have a gerrit but I don't have access to
> > > it.
> > > As my experience, it's hard to develop on Chinese-made chips
> > > wihout
> > > reading Chinese documents.)
> > 
> > Can you take a diff and upload it somewhere else? Download speed is
> > a
> > couple of bytes per second. Can you put the diff in github or
> > similar
> > other service?
> > I would like to see if the port uses DT.
> 
> Technically this was documented here:
Well that's only Technically for the English world. Most Ingeinc
costumers are Chinese so they're providing detailed support for Chinese
world.
According Ingenic's announcement, the ftp have been deprecated for a
long time and it's only exsiting for archive reason.

> 
> ftp://ftp.ingenic.cn/DevSupport/Linux/Linux-3.0.8/JZ4780/JZ4780_linux
> _development_guide_EN.pdf
> 
> Go to §2.1 Download Source Code:
> 
> 1) Download repo a) $ mkdir b) $ cd c) $ wget
> http://git.ingenic.cn:8082/bj/repo d) $ chmod +x repo
> 
Repo is a sourcecode managing system used by Android. The gerrit is
still here but need extra premission to reach. Now ingenic release
there soucecode by "Baidu Netdisk". It's hard to access by foreign
users. So we put the shourcecode here: https://github.com/Ingenic-commu
nity/linux-xburst-bsp

Thanks
-- 
Jiaxun Yang <jiaxun.yang@flygoat.com>