From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: "Linus Walleij" <linus.walleij@linaro.org>,
"Rob Herring" <robh+dt@kernel.org>,
"Andreas Färber" <afaerber@suse.de>, 刘炜 <liuwei@actions-semi.com>,
mp-cs@actions-semi.com, 96boards@ucrobotics.com,
devicetree <devicetree@vger.kernel.org>,
"Daniel Thompson" <daniel.thompson@linaro.org>,
amit.kucheria@linaro.org,
"linux-arm Mailing List" <linux-arm-kernel@lists.infradead.org>,
"open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
"Linux Kernel Mailing List" <linux-kernel@vger.kernel.org>,
hzhang@ucrobotics.com, bdong@ucrobotics.com,
"Mani Sadhasivam" <manivannanece23@gmail.com>
Subject: Re: [PATCH v6 3/9] pinctrl: actions: Add Actions S900 pinctrl driver
Date: Tue, 3 Apr 2018 22:30:16 +0530 [thread overview]
Message-ID: <20180403170016.w3scjt57ssvk6zyi@linaro.org> (raw)
In-Reply-To: <CAHp75VeRh9hORs=4nPqc=rUOCRzAfp0z2_1_xpJUScAeE07yqw@mail.gmail.com>
Hi Andy,
On Sat, Mar 31, 2018 at 12:16:49AM +0300, Andy Shevchenko wrote:
> On Wed, Mar 28, 2018 at 8:46 PM, Manivannan Sadhasivam
> <manivannan.sadhasivam@linaro.org> wrote:
> > Add pinctrl driver for Actions Semi S900 SoC. The driver supports
> > pinctrl, pinmux and pinconf functionalities through a range of registers
> > common to both gpio driver and pinctrl driver.
> >
> > Pinmux functionality is available only for the pin groups while the
> > pinconf functionality is available for both pin groups and individual
> > pins.
>
> > +static void owl_update_bits(void __iomem *base, u32 mask, u32 val)
> > +{
> > + u32 reg_val;
> > +
> > + reg_val = readl_relaxed(base);
> > +
> > + reg_val &= ~mask;
> > + reg_val |= val;
>
> Usual pattern here is
>
> reg_val = (reg_val & ~mask) | (val & mask);
>
> This will allow to avoid possible overflow.
>
Ack.
> > +
> > + writel_relaxed(reg_val, base);
> > +}
>
> > + tmp = readl_relaxed(pctrl->base + reg);
> > + mask = (1 << width) - 1;
> > + arg = (tmp >> bit) & mask;
>
> This looks like a candidate for a helper function. You have at least
> one more same code.
>
> Something like
>
> ..._read_field(reg, mask, shift)
>
>
Okay. Will add owl_read_field helper function.
> > + mask = (1 << width) - 1;
> > + mask = mask << bit;
> > +
> > + owl_update_bits(pctrl->base + reg, mask, (arg << bit));
>
> Similar here,
>
> ..._write_field(regm mask, shift, arg)
>
Will add owl_write_field helper function.
> > + tmp = readl_relaxed(pctrl->base + reg);
> > + mask = (1 << width) - 1;
> > + arg = (tmp >> bit) & mask;
>
> > + mask = (1 << width) - 1;
> > + mask = mask << bit;
> > +
> > + owl_update_bits(pctrl->base + reg, mask, (arg << bit));
>
> > +static const struct pinconf_ops owl_pinconf_ops = {
> > + .is_generic = true,
> > + .pin_config_get = owl_pin_config_get,
> > + .pin_config_set = owl_pin_config_set,
> > + .pin_config_group_get = owl_group_config_get,
> > + .pin_config_group_set = owl_group_config_set
>
> It's still good idea to leave comma here...
>
I'm confused. What is the criteria for removing/keeping comma for last member
of struct? I followed your gpio driver suggestion.
Thanks,
Mani
> > +};
> > +
> > +static struct pinctrl_desc owl_pinctrl_desc = {
> > + .pctlops = &owl_pinctrl_ops,
> > + .pmxops = &owl_pinmux_ops,
> > + .confops = &owl_pinconf_ops,
> > + .owner = THIS_MODULE
>
> ...and here, and in all similar places.
>
> > +};
> > +
>
> --
> With Best Regards,
> Andy Shevchenko
next prev parent reply other threads:[~2018-04-03 17:00 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-28 17:46 [PATCH v6 0/9] Add Actions Semi S900 pinctrl and gpio support Manivannan Sadhasivam
2018-03-28 17:46 ` [PATCH v6 1/9] arm64: dts: actions: Add pinctrl node for S900 Manivannan Sadhasivam
2018-03-28 17:46 ` [PATCH v6 2/9] arm64: actions: Enable PINCTRL in platforms Kconfig Manivannan Sadhasivam
2018-03-28 17:46 ` [PATCH v6 3/9] pinctrl: actions: Add Actions S900 pinctrl driver Manivannan Sadhasivam
2018-03-30 21:16 ` Andy Shevchenko
2018-04-03 17:00 ` Manivannan Sadhasivam [this message]
2018-04-03 17:03 ` Andreas Färber
2018-04-03 17:14 ` Manivannan Sadhasivam
2018-04-06 14:01 ` Andy Shevchenko
2018-03-28 17:46 ` [PATCH v6 4/9] dt-bindings: gpio: Add gpio nodes for Actions S900 SoC Manivannan Sadhasivam
2018-04-12 8:54 ` Linus Walleij
2018-03-28 17:46 ` [PATCH v6 5/9] arm64: dts: actions: Add S900 gpio nodes Manivannan Sadhasivam
2018-03-28 17:47 ` [PATCH v6 6/9] arm64: dts: actions: Add gpio line names to Bubblegum-96 board Manivannan Sadhasivam
2018-03-28 17:47 ` [PATCH v6 7/9] gpio: Add gpio driver for Actions OWL S900 SoC Manivannan Sadhasivam
2018-03-30 21:04 ` Andy Shevchenko
2018-03-28 17:47 ` [PATCH v6 8/9] MAINTAINERS: Add reviewer for ACTIONS platforms Manivannan Sadhasivam
2018-03-28 17:47 ` [PATCH v6 9/9] MAINTAINERS: Add Actions Semi S900 pinctrl and gpio entries Manivannan Sadhasivam
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