* [PATCH] clk: mvebu: use correct bit for 98DX3236 NAND
@ 2018-05-24 5:23 Chris Packham
2018-06-01 19:46 ` Stephen Boyd
0 siblings, 1 reply; 2+ messages in thread
From: Chris Packham @ 2018-05-24 5:23 UTC (permalink / raw)
To: sboyd, linux-clk; +Cc: Chris Packham, Michael Turquette, linux-kernel
The correct fieldbit value for the NAND PLL reload trigger is 27.
Fixes: commit e120c17a70e5 ("clk: mvebu: support for 98DX3236 SoC")
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---
I can't remember where the value of 26 came from. Looking at the lsp source I
have from Marvell it's always been 27, so I suspect I just messed up when
porting. The only documentation I have is that register field is bits 21:27
without adding any detail as to which clock trees correspond to the individual
bits so I'm not sure which clock tree was being triggered.
drivers/clk/mvebu/clk-corediv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/mvebu/clk-corediv.c b/drivers/clk/mvebu/clk-corediv.c
index 8491979f4096..68f05c53d40e 100644
--- a/drivers/clk/mvebu/clk-corediv.c
+++ b/drivers/clk/mvebu/clk-corediv.c
@@ -72,7 +72,7 @@ static const struct clk_corediv_desc mvebu_corediv_desc[] = {
};
static const struct clk_corediv_desc mv98dx3236_corediv_desc[] = {
- { .mask = 0x0f, .offset = 6, .fieldbit = 26 }, /* NAND clock */
+ { .mask = 0x0f, .offset = 6, .fieldbit = 27 }, /* NAND clock */
};
#define to_corediv_clk(p) container_of(p, struct clk_corediv, hw)
--
2.17.0
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] clk: mvebu: use correct bit for 98DX3236 NAND
2018-05-24 5:23 [PATCH] clk: mvebu: use correct bit for 98DX3236 NAND Chris Packham
@ 2018-06-01 19:46 ` Stephen Boyd
0 siblings, 0 replies; 2+ messages in thread
From: Stephen Boyd @ 2018-06-01 19:46 UTC (permalink / raw)
To: Chris Packham, linux-clk; +Cc: Chris Packham, Michael Turquette, linux-kernel
Quoting Chris Packham (2018-05-23 22:23:41)
> The correct fieldbit value for the NAND PLL reload trigger is 27.
>
> Fixes: commit e120c17a70e5 ("clk: mvebu: support for 98DX3236 SoC")
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> ---
Applied to clk-next
^ permalink raw reply [flat|nested] 2+ messages in thread
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